From 148241053123f3c2388d755807438fbe44dd2139 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Thu, 22 Mar 2012 12:00:31 +0000 Subject: MX53: DDR: Fix ZQHWCTRL field TZQ_CS Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x02 - 128 cycles. Signed-off-by: Troy Kisky Acked-by: Fabio Estevam --- board/freescale/mx53evk/imximage.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/freescale/mx53evk/imximage.cfg') diff --git a/board/freescale/mx53evk/imximage.cfg b/board/freescale/mx53evk/imximage.cfg index dd7528c95f..915fb2cff5 100644 --- a/board/freescale/mx53evk/imximage.cfg +++ b/board/freescale/mx53evk/imximage.cfg @@ -108,5 +108,5 @@ DATA 4 0x63fd901c 0x00448039 DATA 4 0x63fd9020 0x00005800 DATA 4 0x63fd9058 0x00033335 DATA 4 0x63fd901c 0x00000000 -DATA 4 0x63fd9040 0x04b80003 +DATA 4 0x63fd9040 0x05380003 DATA 4 0x53fa8004 0x00194005 -- cgit v1.2.3