From 72ce140a5ffa5371c1951aaba871230ce5ea3e59 Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Wed, 16 Mar 2016 20:57:28 +0100
Subject: sunxi: Fix clock_twi_onoff for sun8i-a83

clock_sun8i_a83.c did not contain a clock_twi_onoff implementation
at all, this is fixed by moving the clock_sun6i.c implementation,
which is correct for the a83 too, to a shared location.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---
 arch/arm/cpu/armv7/sunxi/clock.c       | 35 ++++++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 31 ------------------------------
 2 files changed, 35 insertions(+), 31 deletions(-)

(limited to 'arch')

diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index 5cc5d25d2b..0b8fc94711 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/prcm.h>
 #include <asm/arch/sys_proto.h>
 
 __weak void clock_init_sec(void)
@@ -28,3 +29,37 @@ int clock_init(void)
 
 	return 0;
 }
+
+/* These functions are shared between various SoCs so put them here. */
+#if defined CONFIG_SUNXI_GEN_SUN6I && !defined CONFIG_MACH_SUN9I
+int clock_twi_onoff(int port, int state)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	if (port == 5) {
+		if (state)
+			prcm_apb0_enable(
+				PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+		else
+			prcm_apb0_disable(
+				PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
+		return 0;
+	}
+
+	/* set the apb clock gate and reset for twi */
+	if (state) {
+		setbits_le32(&ccm->apb2_gate,
+			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
+		setbits_le32(&ccm->apb2_reset_cfg,
+			     1 << (APB2_RESET_TWI_SHIFT + port));
+	} else {
+		clrbits_le32(&ccm->apb2_reset_cfg,
+			     1 << (APB2_RESET_TWI_SHIFT + port));
+		clrbits_le32(&ccm->apb2_gate,
+			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT + port));
+	}
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 4e1e1a4090..15272c9e71 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -85,37 +85,6 @@ void clock_init_uart(void)
 #endif
 }
 
-int clock_twi_onoff(int port, int state)
-{
-	struct sunxi_ccm_reg *const ccm =
-		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
-	if (port == 5) {
-		if (state)
-			prcm_apb0_enable(
-				PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
-		else
-			prcm_apb0_disable(
-				PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
-		return 0;
-	}
-
-	/* set the apb clock gate and reset for twi */
-	if (state) {
-		setbits_le32(&ccm->apb2_gate,
-			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
-		setbits_le32(&ccm->apb2_reset_cfg,
-			     1 << (APB2_RESET_TWI_SHIFT + port));
-	} else {
-		clrbits_le32(&ccm->apb2_reset_cfg,
-			     1 << (APB2_RESET_TWI_SHIFT + port));
-		clrbits_le32(&ccm->apb2_gate,
-			     CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
-	}
-
-	return 0;
-}
-
 #ifdef CONFIG_SPL_BUILD
 void clock_set_pll1(unsigned int clk)
 {
-- 
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