From b263302aa588464cec3bbdde09e2b52765dbae9e Mon Sep 17 00:00:00 2001 From: David Feng Date: Sat, 31 Jan 2015 11:55:28 +0800 Subject: ARMv8: enable pre-allocation malloc Allocate memory space for pre-allocation malloc and zero global data. This code is partly from crt0.S. Signed-off-by: David Feng --- arch/arm/include/asm/config.h | 4 ---- arch/arm/lib/crt0_64.S | 13 +++++++++++-- 2 files changed, 11 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index be80434dee..7a34a0186c 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -7,10 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#ifdef __aarch64__ -#define CONFIG_SYS_GENERIC_GLOBAL_DATA -#endif - #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 77563967e5..1654011432 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -62,9 +62,18 @@ ENTRY(_main) * Set up initial C runtime environment and call board_init_f(0). */ ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) - sub x0, x0, #GD_SIZE /* allocate one GD above SP */ + sub x18, x0, #GD_SIZE /* allocate one GD above SP */ + bic x18, x18, #0x7 /* 8-byte alignment for GD */ +zero_gd: + sub x0, x0, #0x8 + str xzr, [x0] + cmp x0, x18 + b.gt zero_gd +#if defined(CONFIG_SYS_MALLOC_F_LEN) + sub x0, x18, #CONFIG_SYS_MALLOC_F_LEN + str x0, [x18, #GD_MALLOC_BASE] +#endif bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ - mov x18, sp /* GD is above SP */ mov x0, #0 bl board_init_f -- cgit v1.2.3 From 0edb3a8ec9a48725bf323e99b2167318fae4315a Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Mar 2015 12:04:34 -0600 Subject: ARM: tegra: pinctrl: move Tegra210 code to the correct dir Patches that added the Tegra210 pinctrl driver and renamed directories arch/arm/cpu/tegra{$soc}-common -> arch/arm/mach-tegra/tegra-${soc} crossed. Move the Tegra210 pinctrl driver to the correct location. This wasn't detected since Tegra210 support is in the process of being added, and isn't buildable yet. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/cpu/tegra210-common/pinmux.c | 195 ---------------------------------- arch/arm/mach-tegra/tegra210/pinmux.c | 195 ++++++++++++++++++++++++++++++++++ 2 files changed, 195 insertions(+), 195 deletions(-) delete mode 100644 arch/arm/cpu/tegra210-common/pinmux.c create mode 100644 arch/arm/mach-tegra/tegra210/pinmux.c (limited to 'arch') diff --git a/arch/arm/cpu/tegra210-common/pinmux.c b/arch/arm/cpu/tegra210-common/pinmux.c deleted file mode 100644 index a29c76b1fa..0000000000 --- a/arch/arm/cpu/tegra210-common/pinmux.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define PIN(pin, f0, f1, f2, f3) \ - { \ - .funcs = { \ - PMUX_FUNC_##f0, \ - PMUX_FUNC_##f1, \ - PMUX_FUNC_##f2, \ - PMUX_FUNC_##f3, \ - }, \ - } - -#define PIN_RESERVED {} - -static const struct pmux_pingrp_desc tegra210_pingroups[] = { - /* pin, f0, f1, f2, f3 */ - /* Offset 0x3000 */ - PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3), - PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3), - PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3), - PIN_RESERVED, - /* Offset 0x301c */ - PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN_RESERVED, - /* Offset 0x3038 */ - PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3), - PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3), - PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3), - PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3), - PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3), - PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3), - PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3), - PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3), - PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3), - PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3), - PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3), - PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3), - PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3), - PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3), - PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3), - PIN_RESERVED, - /* Offset 0x30a4 */ - PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3), - PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3), - PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3), - PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3), - PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3), - PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3), - PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3), - PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3), - PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3), - PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3), - PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3), - PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3), - PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3), - PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3), - PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3), - PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3), - PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3), - PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART), - PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART), - PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART), - PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART), - PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3), - PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3), - PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3), - PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3), - PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3), - PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3), - PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3), - PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3), - PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3), - PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3), - PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3), - PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3), - PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3), - PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3), - PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3), - PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3), - PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3), - PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3), - PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3), - PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3), - PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3), - PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3), - PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3), - PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3), - PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3), - PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3), - PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3), - PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3), - PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3), - PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3), - PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3), - PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3), - PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3), - PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3), - PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3), - PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3), - PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3), - PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3), - PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3), - PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3), - PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3), - PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3), - PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1), - PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3), - PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(PA6, SATA, RSVD1, RSVD2, RSVD3), - PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3), - PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3), - PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3), - PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3), - PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3), - PIN(PL1, SOC, RSVD1, RSVD2, RSVD3), - PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3), - PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3), - PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3), - PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3), - PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3), - PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3), -}; -const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups; diff --git a/arch/arm/mach-tegra/tegra210/pinmux.c b/arch/arm/mach-tegra/tegra210/pinmux.c new file mode 100644 index 0000000000..a29c76b1fa --- /dev/null +++ b/arch/arm/mach-tegra/tegra210/pinmux.c @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define PIN(pin, f0, f1, f2, f3) \ + { \ + .funcs = { \ + PMUX_FUNC_##f0, \ + PMUX_FUNC_##f1, \ + PMUX_FUNC_##f2, \ + PMUX_FUNC_##f3, \ + }, \ + } + +#define PIN_RESERVED {} + +static const struct pmux_pingrp_desc tegra210_pingroups[] = { + /* pin, f0, f1, f2, f3 */ + /* Offset 0x3000 */ + PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3), + PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3), + PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3), + PIN_RESERVED, + /* Offset 0x301c */ + PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN_RESERVED, + /* Offset 0x3038 */ + PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3), + PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3), + PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3), + PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3), + PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3), + PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3), + PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3), + PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3), + PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3), + PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3), + PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3), + PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3), + PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3), + PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3), + PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3), + PIN_RESERVED, + /* Offset 0x30a4 */ + PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3), + PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3), + PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3), + PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3), + PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3), + PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3), + PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3), + PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3), + PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3), + PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3), + PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3), + PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3), + PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3), + PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3), + PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3), + PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3), + PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3), + PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART), + PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART), + PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART), + PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART), + PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3), + PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3), + PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3), + PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3), + PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3), + PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3), + PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3), + PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3), + PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3), + PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3), + PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3), + PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3), + PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3), + PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3), + PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3), + PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3), + PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3), + PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3), + PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3), + PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3), + PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3), + PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3), + PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3), + PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3), + PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3), + PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3), + PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3), + PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3), + PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3), + PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3), + PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3), + PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3), + PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3), + PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3), + PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3), + PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3), + PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3), + PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3), + PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3), + PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3), + PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3), + PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3), + PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1), + PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3), + PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(PA6, SATA, RSVD1, RSVD2, RSVD3), + PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3), + PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3), + PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3), + PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3), + PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3), + PIN(PL1, SOC, RSVD1, RSVD2, RSVD3), + PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3), + PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3), + PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3), + PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3), + PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3), + PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3), +}; +const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups; -- cgit v1.2.3 From c21478bc6e527f57cb2e3251c7d6baa3e54514c2 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Mar 2015 12:04:35 -0600 Subject: ARM: tegra: pinctrl: minor cleanup Move struct pmux_pingrp_desc type and tegra_soc_pingroups variable declaration together with other pin/mux level definitions. Now the whole file is grouped/ordered pin/mux-related then drvgrp-related definitions. Fix typo in ifdef comment. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 20 ++++++++++---------- arch/arm/mach-tegra/pinmux-common.c | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index 4212e57699..e3eb706fcb 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -170,6 +170,16 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, int len); +struct pmux_pingrp_desc { + u8 funcs[4]; +#if defined(CONFIG_TEGRA20) + u8 ctl_id; + u8 pull_id; +#endif /* CONFIG_TEGRA20 */ +}; + +extern const struct pmux_pingrp_desc *tegra_soc_pingroups; + #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS #define PMUX_SLWF_MIN 0 @@ -219,14 +229,4 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ -struct pmux_pingrp_desc { - u8 funcs[4]; -#if defined(CONFIG_TEGRA20) - u8 ctl_id; - u8 pull_id; -#endif /* CONFIG_TEGRA20 */ -}; - -extern const struct pmux_pingrp_desc *tegra_soc_pingroups; - #endif /* _TEGRA_PINMUX_H_ */ diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 912f65e98b..96dbb5e89b 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -695,4 +695,4 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, for (i = 0; i < len; i++) pinmux_config_drvgrp(&config[i]); } -#endif /* TEGRA_PMX_HAS_DRVGRPS */ +#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ -- cgit v1.2.3 From 5ee7ec7bafe6d02ebacdde06bb536f55cff4cdd8 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Mar 2015 12:04:36 -0600 Subject: ARM: tegra: pinctrl: add support for MIPI PAD control groups Some pinmux controls are in a different register set. Add support for manipulating those in a similar way to existing pins/groups. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/pinmux.h | 16 +++++++++ arch/arm/mach-tegra/pinmux-common.c | 57 ++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index e3eb706fcb..3cc52dd773 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -229,4 +229,20 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ +#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS +struct pmux_mipipadctrlgrp_config { + u32 grp:16; /* pin group PMUX_MIPIPADCTRLGRP_x */ + u32 func:8; /* function to assign PMUX_FUNC_... */ +}; + +void pinmux_config_mipipadctrlgrp_table( + const struct pmux_mipipadctrlgrp_config *config, int len); + +struct pmux_mipipadctrlgrp_desc { + u8 funcs[2]; +}; + +extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups; +#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ + #endif /* _TEGRA_PINMUX_H_ */ diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c index 96dbb5e89b..b4a1432afc 100644 --- a/arch/arm/mach-tegra/pinmux-common.c +++ b/arch/arm/mach-tegra/pinmux-common.c @@ -108,6 +108,8 @@ #define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4)) +#define MIPIPADCTRL_REG(group) _R(TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG + ((group) * 4)) + /* * We could force arch-tegraNN/pinmux.h to define all of these. However, * that's a lot of defines, and for now it's manageable to just put a @@ -696,3 +698,58 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, pinmux_config_drvgrp(&config[i]); } #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ + +#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS + +#define pmux_mipipadctrlgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_MIPIPADCTRLGRP_COUNT)) + +static void pinmux_mipipadctrl_set_func(enum pmux_mipipadctrlgrp grp, + enum pmux_func func) +{ + u32 *reg = MIPIPADCTRL_REG(grp); + int i, mux = -1; + u32 val; + + if (func == PMUX_FUNC_DEFAULT) + return; + + /* Error check grp and func */ + assert(pmux_mipipadctrlgrp_isvalid(grp)); + assert(pmux_func_isvalid(func)); + + if (func >= PMUX_FUNC_RSVD1) { + mux = (func - PMUX_FUNC_RSVD1) & 1; + } else { + /* Search for the appropriate function */ + for (i = 0; i < 2; i++) { + if (tegra_soc_mipipadctrl_groups[grp].funcs[i] + == func) { + mux = i; + break; + } + } + } + assert(mux != -1); + + val = readl(reg); + val &= ~(1 << 1); + val |= (mux << 1); + writel(val, reg); +} + +static void pinmux_config_mipipadctrlgrp(const struct pmux_mipipadctrlgrp_config *config) +{ + enum pmux_mipipadctrlgrp grp = config->grp; + + pinmux_mipipadctrl_set_func(grp, config->func); +} + +void pinmux_config_mipipadctrlgrp_table( + const struct pmux_mipipadctrlgrp_config *config, int len) +{ + int i; + + for (i = 0; i < len; i++) + pinmux_config_mipipadctrlgrp(&config[i]); +} +#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ -- cgit v1.2.3 From 89d9437356ce9121f99889c11b55ed28fb8851b2 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 25 Mar 2015 12:04:37 -0600 Subject: ARM: tegra: enable MIPI PAD CTRL support for Tegra124 This allows selection between CSI and DSI_B on the MIPI pads. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra124/pinmux.h | 9 +++++++++ arch/arm/mach-tegra/tegra124/pinmux.c | 17 +++++++++++++++++ 2 files changed, 26 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index 78bc9e6f17..9fcbb0f80b 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -246,6 +246,11 @@ enum pmux_drvgrp { PMUX_DRVGRP_COUNT, }; +enum pmux_mipipadctrlgrp { + PMUX_MIPIPADCTRLGRP_DSI_B, + PMUX_MIPIPADCTRLGRP_COUNT, +}; + enum pmux_func { PMUX_FUNC_DEFAULT, PMUX_FUNC_BLINK, @@ -255,6 +260,7 @@ enum pmux_func { PMUX_FUNC_CLK, PMUX_FUNC_CLK12, PMUX_FUNC_CPU, + PMUX_FUNC_CSI, PMUX_FUNC_DAP, PMUX_FUNC_DAP1, PMUX_FUNC_DAP2, @@ -263,6 +269,7 @@ enum pmux_func { PMUX_FUNC_DISPLAYA_ALT, PMUX_FUNC_DISPLAYB, PMUX_FUNC_DP, + PMUX_FUNC_DSI_B, PMUX_FUNC_DTV, PMUX_FUNC_EXTPERIPH1, PMUX_FUNC_EXTPERIPH2, @@ -336,8 +343,10 @@ enum pmux_func { }; #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 +#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS +#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS #define TEGRA_PMX_GRPS_HAVE_LPMD #define TEGRA_PMX_GRPS_HAVE_SCHMT #define TEGRA_PMX_GRPS_HAVE_HSM diff --git a/arch/arm/mach-tegra/tegra124/pinmux.c b/arch/arm/mach-tegra/tegra124/pinmux.c index c6685eaae1..4629b4676c 100644 --- a/arch/arm/mach-tegra/tegra124/pinmux.c +++ b/arch/arm/mach-tegra/tegra124/pinmux.c @@ -304,3 +304,20 @@ static const struct pmux_pingrp_desc tegra124_pingroups[] = { PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4), }; const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups; + +#define MIPIPADCTRL_GRP(grp, f0, f1) \ + { \ + .funcs = { \ + PMUX_FUNC_##f0, \ + PMUX_FUNC_##f1, \ + }, \ + } + +#define MIPIPADCTRL_RESERVED {} + +static const struct pmux_mipipadctrlgrp_desc tegra124_mipipadctrl_groups[] = { + /* pin, f0, f1 */ + /* Offset 0x820 */ + MIPIPADCTRL_GRP(DSI_B, CSI, DSI_B), +}; +const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups = tegra124_mipipadctrl_groups; -- cgit v1.2.3 From e57c6e5b50d330516e30f61b824613d551316086 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 26 Mar 2015 01:31:54 +0100 Subject: ARM: tegra: rename colibri_t20 board/configuration/device-tree In accordance with our other modules supported by U-Boot and as agreed upon for Apalis/Colibri T30 get rid of the carrier board in the board/ configuration/device-tree naming. While at it also bring the prompt more in line with our other products. Signed-off-by: Marcel Ziswiler Signed-off-by: Tom Warren --- arch/arm/dts/Makefile | 2 +- arch/arm/dts/tegra20-colibri.dts | 49 +++++++++++++++++++++++++++++++ arch/arm/dts/tegra20-colibri_t20_iris.dts | 49 ------------------------------- arch/arm/mach-tegra/tegra20/Kconfig | 4 +-- 4 files changed, 52 insertions(+), 52 deletions(-) create mode 100644 arch/arm/dts/tegra20-colibri.dts delete mode 100644 arch/arm/dts/tegra20-colibri_t20_iris.dts (limited to 'arch') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index cbe5b86755..f897e6d969 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -24,7 +24,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-trimslice.dtb \ tegra20-ventana.dtb \ tegra20-whistler.dtb \ - tegra20-colibri_t20_iris.dtb \ + tegra20-colibri.dtb \ tegra30-apalis.dtb \ tegra30-beaver.dtb \ tegra30-cardhu.dtb \ diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts new file mode 100644 index 0000000000..3131b9201b --- /dev/null +++ b/arch/arm/dts/tegra20-colibri.dts @@ -0,0 +1,49 @@ +/dts-v1/; + +#include "tegra20.dtsi" + +/ { + model = "Toradex Colibri T20"; + compatible = "toradex,t20", "nvidia,tegra20"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + usb0 = "/usb@c5008000"; + usb1 = "/usb@c5000000"; + usb2 = "/usb@c5004000"; + sdhci0 = "/sdhci@c8000600"; + }; + + usb@c5000000 { + dr_mode = "otg"; + }; + + usb@c5004000 { + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; + }; + + usb@c5008000 { + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + }; + + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; + nvidia,width = <8>; + nvidia,timing = <15 100 25 80 25 10 15 10 100>; + + nand@0 { + reg = <0>; + compatible = "nand-flash"; + }; + }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + bus-width = <4>; + }; +}; diff --git a/arch/arm/dts/tegra20-colibri_t20_iris.dts b/arch/arm/dts/tegra20-colibri_t20_iris.dts deleted file mode 100644 index 3131b9201b..0000000000 --- a/arch/arm/dts/tegra20-colibri_t20_iris.dts +++ /dev/null @@ -1,49 +0,0 @@ -/dts-v1/; - -#include "tegra20.dtsi" - -/ { - model = "Toradex Colibri T20"; - compatible = "toradex,t20", "nvidia,tegra20"; - - chosen { - stdout-path = &uarta; - }; - - aliases { - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5000000"; - usb2 = "/usb@c5004000"; - sdhci0 = "/sdhci@c8000600"; - }; - - usb@c5000000 { - dr_mode = "otg"; - }; - - usb@c5004000 { - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; - nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; - }; - - usb@c5008000 { - nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - }; - - nand-controller@70008000 { - nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; - nvidia,width = <8>; - nvidia,timing = <15 100 25 80 25 10 15 10 100>; - - nand@0 { - reg = <0>; - compatible = "nand-flash"; - }; - }; - - sdhci@c8000600 { - status = "okay"; - cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; - bus-width = <4>; - }; -}; diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index a354e2ad1f..7f09f819cc 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -30,7 +30,7 @@ config TARGET_VENTANA config TARGET_WHISTLER bool "NVIDIA Tegra20 Whistler evaluation board" -config TARGET_COLIBRI_T20_IRIS +config TARGET_COLIBRI_T20 bool "Toradex Colibri T20 board" endchoice @@ -47,6 +47,6 @@ source "board/avionic-design/tec/Kconfig" source "board/compulab/trimslice/Kconfig" source "board/nvidia/ventana/Kconfig" source "board/nvidia/whistler/Kconfig" -source "board/toradex/colibri_t20_iris/Kconfig" +source "board/toradex/colibri_t20/Kconfig" endif -- cgit v1.2.3 From 1ed056e84db0ea5c4365a5e0a79dd94ff1bc4b0b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 26 Mar 2015 02:16:33 +0100 Subject: ARM: tegra: fix colibri_t20 machine type A while ago I got Russell to change the machine type of our Colibri T20 from COLIBRI_TEGRA2 to COLIBRI_T20 which at least in parts is also reflected in his machine registry: http://www.arm.linux.org.uk/developer/machines/list.php?id=3323 For us it is really very beneficial to actually still be able to boot downstream L4T kernel with its working hardware accelerated graphics/multimedia stack albeit it being proprietary/closed-source. Signed-off-by: Marcel Ziswiler Acked-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/mach-types.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index d4a447b2b8..c424a22442 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -936,7 +936,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_CWME9210 3320 #define MACH_TYPE_CWME9210JS 3321 #define MACH_TYPE_PGS_SITARA 3322 -#define MACH_TYPE_COLIBRI_TEGRA2 3323 +#define MACH_TYPE_COLIBRI_T20 3323 #define MACH_TYPE_W21 3324 #define MACH_TYPE_POLYSAT1 3325 #define MACH_TYPE_DATAWAY 3326 @@ -12197,16 +12197,16 @@ extern unsigned int __machine_arch_type; # define machine_is_pgs_v1() (0) #endif -#ifdef CONFIG_MACH_COLIBRI_TEGRA2 +#ifdef CONFIG_MACH_COLIBRI_T20 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_COLIBRI_TEGRA2 +# define machine_arch_type MACH_TYPE_COLIBRI_T20 # endif -# define machine_is_colibri_tegra2() (machine_arch_type == MACH_TYPE_COLIBRI_TEGRA2) +# define machine_is_colibri_t20() (machine_arch_type == MACH_TYPE_COLIBRI_T20) #else -# define machine_is_colibri_tegra2() (0) +# define machine_is_colibri_t20() (0) #endif #ifdef CONFIG_MACH_W21 -- cgit v1.2.3 From 9b219d4dfb1f358fa0dfa03f6e529c82f9299dd2 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 27 Mar 2015 01:31:44 +0100 Subject: tegra: pinmux: fix FUNCMUX_NDFLASH_KBC_8_BIT Even the 8-bit case needs KBCB configured, as pin D7 is located in this pingroup. Please note that pingroup ATC seems to come out of reset with its config set to NAND so one needs to explicitly configure some other function to this group in order to avoid clashing settings which is outside the scope of this patch. Signed-off-by: Lucas Stach Signed-off-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Signed-off-by: Tom Warren --- arch/arm/mach-tegra/tegra20/funcmux.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra20/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c index 0df4a0738d..44a85c5f1d 100644 --- a/arch/arm/mach-tegra/tegra20/funcmux.c +++ b/arch/arm/mach-tegra/tegra20/funcmux.c @@ -252,12 +252,14 @@ int funcmux_select(enum periph_id id, int config) break; case FUNCMUX_NDFLASH_KBC_8_BIT: pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND); + pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND); pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND); pinmux_tristate_disable(PMUX_PINGRP_KBCA); + pinmux_tristate_disable(PMUX_PINGRP_KBCB); pinmux_tristate_disable(PMUX_PINGRP_KBCC); pinmux_tristate_disable(PMUX_PINGRP_KBCD); pinmux_tristate_disable(PMUX_PINGRP_KBCE); -- cgit v1.2.3