From 535a159ab677d553652843b1bd1c16106c42f66f Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 21 May 2012 08:43:11 +0000 Subject: powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB The fix for errata workaround is to avoid covering physical address 0xff000000 to 0xffffffff during the implementation. Early commit eb672e92 works until DDR size exceeds 4GB. This fix works for DDR size up to 64GB. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index 18e9cc5b8b..81961def1b 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -50,7 +50,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, csn = i; csn_bnds_backup = regs->cs[i].bnds; csn_bnds_t = (unsigned int *) ®s->cs[i].bnds; - *csn_bnds_t = regs->cs[i].bnds ^ 0x0F000F00; + if (cs_ea > 0xeff) + *csn_bnds_t = regs->cs[i].bnds + 0x01000000; + else + *csn_bnds_t = regs->cs[i].bnds + 0x01000100; debug("Found cs%d_bns (0x%08x) covering 0xff000000, " "change it to 0x%x\n", csn, csn_bnds_backup, regs->cs[i].bnds); @@ -310,9 +313,15 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, /* 7. Wait for 400ms/GB */ total_gb_size_per_controller = 0; for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - total_gb_size_per_controller += + if (i == csn) { + total_gb_size_per_controller += + ((csn_bnds_backup & 0xFFFF) >> 6) + - (csn_bnds_backup >> 22) + 1; + } else { + total_gb_size_per_controller += ((regs->cs[i].bnds & 0xFFFF) >> 6) - (regs->cs[i].bnds >> 22) + 1; + } } if (in_be32(&ddr->sdram_cfg) & 0x80000) total_gb_size_per_controller <<= 1; -- cgit v1.2.3 From 98de369b1ca49a3c6d1b6408e78d05cbf2f3ea5d Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Thu, 28 Jun 2012 23:36:38 +0000 Subject: powerpc/ddr: fix fsl_ddr_get_dimm_params compile error fsl_ddr_get_dimm_params() should be wrapped by CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of using SPD, it will cause compile error. Signed-off-by: Shaohui Xie Acked-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index f52ad9f691..c2a03e334c 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -366,7 +366,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, } } -#else +#elif defined(CONFIG_SYS_DDR_RAW_TIMING) case STEP_COMPUTE_DIMM_PARMS: for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { -- cgit v1.2.3 From 7ee411071f31c856107e6b29fcd8df53ae4d7349 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 6 Jul 2012 07:39:26 +0000 Subject: powerpc/85xx: improve definition of BR_PHYS_ADDR macro The BR_PHYS_ADDR(x) macro was missing parentheses around "x" in the macro definition, so callers had to supply their own parenthesis. Signed-off-by: Timur Tabi Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/fsl_lbc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 2a23d84cba..d1def75c66 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -82,10 +82,10 @@ void lbc_sdram_init(void); /* Convert an address into the right format for the BR registers */ #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC) -#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ - ((x & 0x300000000ULL) >> 19))) +#define BR_PHYS_ADDR(x) \ + ((u32)(((x) & 0x0ffff8000ULL) | (((x) & 0x300000000ULL) >> 19))) #else -#define BR_PHYS_ADDR(x) (x & 0xffff8000) +#define BR_PHYS_ADDR(x) ((u32)(x) & 0xffff8000) #endif /* OR - Option Registers -- cgit v1.2.3 From 718f2b318764233cb5dec5e740962a66eecbabad Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 20 Jul 2012 10:59:38 +0000 Subject: powerpc/mpc85xx: Ignore E bit for BSC9130/1 Commit 48f6a5c34 removed E bit. BSC9130/1 were left out due to patch apply timing. Remove them now. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/processor.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 4eb88e9096..dc009d6604 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1100,9 +1100,7 @@ #define SVR_8641D 0x809001 #define SVR_9130 0x860001 -#define SVR_9130_E 0x860801 #define SVR_9131 0x860000 -#define SVR_9131_E 0x860800 #define SVR_Unknown 0xFFFFFF -- cgit v1.2.3 From 5c5befda58e4a3f198a033e8a9952b2b309acc86 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Wed, 25 Jul 2012 11:03:34 +0000 Subject: powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs The SET_PCI_LIODN() macro takes a compatible property string as a parameter, so that it knows which PCI device tree node to look for. The calls to these macros are using a hard-coded string, but we already have the CONFIG_SYS_FSL_PCIE_COMPAT macro which contains the same string, so we should use that. Signed-off-by: Timur Tabi Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/p2041_ids.c | 6 +++--- arch/powerpc/cpu/mpc85xx/p3041_ids.c | 8 ++++---- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 6 +++--- arch/powerpc/cpu/mpc85xx/p5020_ids.c | 8 ++++---- 4 files changed, 14 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index b99b54d6bc..91d9cac568 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -62,9 +62,9 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index c50b442801..e46a714dcc 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -62,10 +62,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index a6ea6af64f..5c287fbf46 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -52,9 +52,9 @@ struct liodn_id_table liodn_tbl[] = { SET_SDHC_LIODN(1, 156), - SET_PCI_LIODN("fsl,p4080-pcie", 1, 193), - SET_PCI_LIODN("fsl,p4080-pcie", 2, 194), - SET_PCI_LIODN("fsl,p4080-pcie", 3, 195), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), SET_DMA_LIODN(1, 196), SET_DMA_LIODN(2, 197), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index ff57a193bb..e8c26bf44c 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -62,10 +62,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 127), SET_SATA_LIODN(2, 128), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), SET_DMA_LIODN(1, 197), SET_DMA_LIODN(2, 198), -- cgit v1.2.3