From 07806977878130dd27dfc926ef7002041f6cf288 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 20 Dec 2015 04:00:09 +0100 Subject: arm: socfpga: Actually enable L2 cache The L2 cache was never enabled in the v7_outer_cache_enable(), fix this and enable the L2 cache. Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See --- arch/arm/mach-socfpga/misc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index b110f5bb42..a54d2b9faa 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -54,14 +54,23 @@ void enable_caches(void) void v7_outer_cache_enable(void) { - /* disable the L2 cache */ - writel(0, &pl310->pl310_ctrl); + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | L310_AUX_CTRL_INST_PREFETCH_MASK | L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + +void v7_outer_cache_disable(void) +{ + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } /* -- cgit v1.2.3