From 1cd9158eb4e5961e225a870195ccc8eed5d90adc Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 8 Feb 2013 17:04:58 +0800 Subject: blackfin: Change the member's type in dma structures. Signed-off-by: Sonic Zhang --- arch/blackfin/include/asm/dma.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'arch/blackfin/include/asm') diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h index ef1db6e99c..8a7c07933e 100644 --- a/arch/blackfin/include/asm/dma.h +++ b/arch/blackfin/include/asm/dma.h @@ -17,21 +17,21 @@ struct dmasg_large { void *next_desc_addr; - unsigned long start_addr; - unsigned short cfg; - unsigned short x_count; - short x_modify; - unsigned short y_count; - short y_modify; + u32 start_addr; + u16 cfg; + u16 x_count; + s16 x_modify; + u16 y_count; + s16 y_modify; } __attribute__((packed)); struct dmasg { - unsigned long start_addr; - unsigned short cfg; - unsigned short x_count; - short x_modify; - unsigned short y_count; - short y_modify; + u32 start_addr; + u16 cfg; + u16 x_count; + s16 x_modify; + u16 y_count; + s16 y_modify; } __attribute__((packed)); struct dma_register { -- cgit v1.2.3 From f4d8038439fb372c91c3a27121a911c359603bcf Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Tue, 5 Feb 2013 18:57:49 +0800 Subject: blackfin: run core1 from L1 code sram start address in uboot init code on core 0 Define core 1 L1 code sram start address. Add function to enable core 1 for BF609 and BF561. Add config macro to allow customer to run core 1 in uboot init code on core 0. Signed-off-by: Sonic Zhang --- arch/blackfin/include/asm/mach-bf561/BF561_def.h | 2 ++ arch/blackfin/include/asm/mach-bf609/BF609_def.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch/blackfin/include/asm') diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h index a7ff5a3feb..8fd552f2a1 100644 --- a/arch/blackfin/include/asm/mach-bf561/BF561_def.h +++ b/arch/blackfin/include/asm/mach-bf561/BF561_def.h @@ -714,4 +714,6 @@ #define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1) #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) +#define COREB_L1_CODE_START 0xFF600000 + #endif /* __BFIN_DEF_ADSP_BF561_proc__ */ diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h index 8c1dcd006e..4d3b003409 100644 --- a/arch/blackfin/include/asm/mach-bf609/BF609_def.h +++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h @@ -244,4 +244,6 @@ #define L1_INST_SRAM_SIZE 0x8000 #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) +#define COREB_L1_CODE_START 0xFF600000 + #endif /* __BFIN_DEF_ADSP_BF609_proc__ */ -- cgit v1.2.3 From 79f2b3992f52334b510214c6b1b60c4200133658 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Tue, 5 Feb 2013 19:10:34 +0800 Subject: blackfin: Set correct early debug serial baudrate. Calculate the early uart clock from the system clock registers set by the bootrom other than the predefine uboot clock macros. Split the early baudrate setting function and the normal baudrate setting one. Signed-off-by: Sonic Zhang --- arch/blackfin/include/asm/clock.h | 74 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 arch/blackfin/include/asm/clock.h (limited to 'arch/blackfin/include/asm') diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h new file mode 100644 index 0000000000..df6cd68171 --- /dev/null +++ b/arch/blackfin/include/asm/clock.h @@ -0,0 +1,74 @@ + +/* + * Copyright (C) 2012 Analog Devices Inc. + * Licensed under the GPL-2 or later. + */ + +#ifndef __CLOCK_H__ +#define __CLOCK_H__ + +#include +#ifdef PLL_CTL +#include +# define pll_is_bypassed() (bfin_read_PLL_STAT() & DF) +#else +#include +# define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP) +# define bfin_read_PLL_CTL() bfin_read_CGU_CTL() +# define bfin_read_PLL_DIV() bfin_read_CGU_DIV() +# define SSEL SYSSEL +# define SSEL_P SYSSEL_P +#endif + +__attribute__((always_inline)) +static inline uint32_t early_division(uint32_t dividend, uint32_t divisor) +{ + uint32_t quotient; + uint32_t i, j; + + for (quotient = 1, i = 1; dividend > divisor; ++i) { + j = divisor << i; + if (j > dividend || (j & 0x80000000)) { + --i; + quotient += (1 << i); + dividend -= (divisor << i); + i = 0; + } + } + + return quotient; +} + +__attribute__((always_inline)) +static inline uint32_t early_get_uart_clk(void) +{ + uint32_t msel, pll_ctl, vco; + uint32_t div, ssel, sclk, uclk; + + pll_ctl = bfin_read_PLL_CTL(); + msel = (pll_ctl & MSEL) >> MSEL_P; + if (msel == 0) + msel = (MSEL >> MSEL_P) + 1; + + vco = (CONFIG_CLKIN_HZ >> (pll_ctl & DF)) * msel; + sclk = vco; + if (!pll_is_bypassed()) { + div = bfin_read_PLL_DIV(); + ssel = (div & SSEL) >> SSEL_P; + sclk = early_division(vco, ssel); + } + uclk = sclk; +#ifdef CGU_DIV + ssel = (div & S0SEL) >> S0SEL_P; + uclk = early_division(sclk, ssel); +#endif + return uclk; +} + +#ifdef CGU_DIV +# define get_uart_clk get_sclk0 +#else +# define get_uart_clk get_sclk +#endif + +#endif -- cgit v1.2.3 From ab80b6595765a01f774ad2a29fde8b0c325533ac Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 30 Nov 2012 17:39:32 +0800 Subject: blackfin: Correct early serial mess output in BYPASS boot mode. The early serial should not be configured again in initcode() for BYPASS boot mode and in start() for the other LDR boot modes. In BYPASS boot mode, the start up code is located in Nor flash address other than the DRAM address defined in link script. The code embedded string can't be addressed by its compile time symbol. Calculate it according to the flash offset. Signed-off-by: Sonic Zhang --- arch/blackfin/include/asm/clock.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch/blackfin/include/asm') diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h index df6cd68171..f1fcd40499 100644 --- a/arch/blackfin/include/asm/clock.h +++ b/arch/blackfin/include/asm/clock.h @@ -10,7 +10,7 @@ #include #ifdef PLL_CTL #include -# define pll_is_bypassed() (bfin_read_PLL_STAT() & DF) +# define pll_is_bypassed() (bfin_read_PLL_CTL() & BYPASS) #else #include # define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP) @@ -55,7 +55,11 @@ static inline uint32_t early_get_uart_clk(void) if (!pll_is_bypassed()) { div = bfin_read_PLL_DIV(); ssel = (div & SSEL) >> SSEL_P; +#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS + sclk = vco/ssel; +#else sclk = early_division(vco, ssel); +#endif } uclk = sclk; #ifdef CGU_DIV -- cgit v1.2.3 From 7d861d95a315852532d581884b3b72536c25032c Mon Sep 17 00:00:00 2001 From: Bob Liu Date: Tue, 5 Feb 2013 19:05:41 +0800 Subject: blackfin: bf609: add softswitch config command Add softswitch_output command for bf609-ezkit to enable softswitches. Signed-off-by: Bob Liu Signed-off-by: Sonic Zhang --- arch/blackfin/include/asm/soft_switch.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 arch/blackfin/include/asm/soft_switch.h (limited to 'arch/blackfin/include/asm') diff --git a/arch/blackfin/include/asm/soft_switch.h b/arch/blackfin/include/asm/soft_switch.h new file mode 100644 index 0000000000..ff8e44d8be --- /dev/null +++ b/arch/blackfin/include/asm/soft_switch.h @@ -0,0 +1,18 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2008-2012 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __SOFT_SWITCH_H__ +#define __SOFT_SWITCH_H__ + +#define IO_PORT_A 0 +#define IO_PORT_B 1 +#define IO_PORT_INPUT 0 +#define IO_PORT_OUTPUT 1 + +int config_switch_bit(int num, int port, int bit, int dir, uchar value); +#endif -- cgit v1.2.3 From 13262d4cdab79b6ee8d9c6089f84132a4c9372a4 Mon Sep 17 00:00:00 2001 From: Scott Jiang Date: Mon, 1 Apr 2013 15:55:14 -0400 Subject: bf609: add SPI register base address - BF609 spi driver depend on this. Signed-off-by: Scott Jiang Signed-off-by: Sonic Zhang --- arch/blackfin/include/asm/mach-bf609/BF609_def.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/blackfin/include/asm') diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h index 4d3b003409..02b81d3fd1 100644 --- a/arch/blackfin/include/asm/mach-bf609/BF609_def.h +++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h @@ -128,6 +128,9 @@ #define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */ #define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */ +#define SPI0_REGBASE 0xFFC40400 /* SPI0 Base Address */ +#define SPI1_REGBASE 0xFFC40500 /* SPI1 Base Address */ + #define DMA10_DSCPTR_NXT 0xFFC05000 /* DMA10 Pointer to Next Initial Desc */ #define DMA10_ADDRSTART 0xFFC05004 /* DMA10 Start Address of Current Buf */ #define DMA10_CFG 0xFFC05008 /* DMA10 Configuration Register */ -- cgit v1.2.3 From 9d803fc8125a3528f700da9064d1bfa3fbc56b13 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Sun, 7 Apr 2013 19:04:14 +0800 Subject: blackfin: Move blackfin serial driver out of blackfin arch folder. - Move blackfin serial driver to the generic driver folder. - Move blackfin serial headers to blackfin arch head folder. - Update the include path to blackfin serial header in start up code. Signed-off-by: Sonic Zhang --- arch/blackfin/include/asm/serial.h | 131 ++++++++++++++ arch/blackfin/include/asm/serial1.h | 342 ++++++++++++++++++++++++++++++++++++ arch/blackfin/include/asm/serial4.h | 150 ++++++++++++++++ 3 files changed, 623 insertions(+) create mode 100644 arch/blackfin/include/asm/serial.h create mode 100644 arch/blackfin/include/asm/serial1.h create mode 100644 arch/blackfin/include/asm/serial4.h (limited to 'arch/blackfin/include/asm') diff --git a/arch/blackfin/include/asm/serial.h b/arch/blackfin/include/asm/serial.h new file mode 100644 index 0000000000..87a337d1b4 --- /dev/null +++ b/arch/blackfin/include/asm/serial.h @@ -0,0 +1,131 @@ +/* + * serial.h - common serial defines for early debug and serial driver. + * any functions defined here must be always_inline since + * initcode cannot have function calls. + * + * Copyright (c) 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_CPU_SERIAL_H__ +#define __BFIN_CPU_SERIAL_H__ + +#include +#include + +#ifndef CONFIG_UART_CONSOLE +# define CONFIG_UART_CONSOLE 0 +#endif + +#ifdef CONFIG_DEBUG_EARLY_SERIAL +# define BFIN_DEBUG_EARLY_SERIAL 1 +#else +# define BFIN_DEBUG_EARLY_SERIAL 0 +#endif + +#if defined(__ADSPBF60x__) +# define BFIN_UART_HW_VER 4 +#elif defined(__ADSPBF50x__) || defined(__ADSPBF54x__) +# define BFIN_UART_HW_VER 2 +#else +# define BFIN_UART_HW_VER 1 +#endif + +#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx +#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx) +#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin) +#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin) + +#define pUART ((volatile struct bfin_mmr_serial *)uart_base) + +#ifndef __ASSEMBLY__ +__attribute__((always_inline)) +static inline void serial_do_portmux(void); +#endif + +#if BFIN_UART_HW_VER < 4 +# include "serial1.h" +#else +# include "serial4.h" +#endif + +#ifndef __ASSEMBLY__ + +__attribute__((always_inline)) +static inline void serial_do_portmux(void) +{ + if (!BFIN_DEBUG_EARLY_SERIAL) { + const unsigned short pins[] = { P_UART(RX), P_UART(TX), 0, }; + peripheral_request_list(pins, "bfin-uart"); + return; + } + + serial_early_do_portmux(); +} + +#ifndef BFIN_IN_INITCODE +__attribute__((always_inline)) +static inline void serial_early_puts(const char *s) +{ + if (BFIN_DEBUG_EARLY_SERIAL) { + serial_puts("Early: "); + serial_puts(s); + } +} +#endif + +#else + +.macro serial_early_init +#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM) + call __serial_early_init; +#endif +.endm + +.macro serial_early_set_baud +#if defined(CONFIG_DEBUG_EARLY_SERIAL) && !defined(CONFIG_UART_MEM) + R0.L = LO(CONFIG_BAUDRATE); + R0.H = HI(CONFIG_BAUDRATE); + call __serial_early_set_baud; +#endif +.endm + +#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS +#define update_serial_early_string_addr \ + R1.L = _start; \ + R1.H = _start; \ + R0 = R0 - R1; \ + R1.L = 0; \ + R1.H = 0x2000; \ + R0 = R0 + R1; +#else +#define update_serial_early_string_addr +#endif + +/* Since we embed the string right into our .text section, we need + * to find its address. We do this by getting our PC and adding 2 + * bytes (which is the length of the jump instruction). Then we + * pass this address to serial_puts(). + */ +#ifdef CONFIG_DEBUG_EARLY_SERIAL +# define serial_early_puts(str) \ + .section .rodata; \ + 7: \ + .ascii "Early:"; \ + .ascii __FILE__; \ + .ascii ": "; \ + .ascii str; \ + .asciz "\n"; \ + .previous; \ + R0.L = 7b; \ + R0.H = 7b; \ + update_serial_early_string_addr \ + call _uart_early_puts; +#else +# define serial_early_puts(str) +#endif + +#endif + +#endif diff --git a/arch/blackfin/include/asm/serial1.h b/arch/blackfin/include/asm/serial1.h new file mode 100644 index 0000000000..467d3817f1 --- /dev/null +++ b/arch/blackfin/include/asm/serial1.h @@ -0,0 +1,342 @@ +/* + * serial.h - common serial defines for early debug and serial driver. + * any functions defined here must be always_inline since + * initcode cannot have function calls. + * + * Copyright (c) 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_CPU_SERIAL1_H__ +#define __BFIN_CPU_SERIAL1_H__ + +#include + +#ifndef __ASSEMBLY__ + +#include + +#define MMR_UART(n) _PASTE_UART(n, UART, DLL) +#ifdef UART_DLL +# define UART0_DLL UART_DLL +# if CONFIG_UART_CONSOLE != 0 +# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART +# endif +#endif +#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE) + +#define LOB(x) ((x) & 0xFF) +#define HIB(x) (((x) >> 8) & 0xFF) + +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +struct bfin_mmr_serial { +#if BFIN_UART_HW_VER == 2 + u16 dll; + u16 __pad_0; + u16 dlh; + u16 __pad_1; + u16 gctl; + u16 __pad_2; + u16 lcr; + u16 __pad_3; + u16 mcr; + u16 __pad_4; + u16 lsr; + u16 __pad_5; + u16 msr; + u16 __pad_6; + u16 scr; + u16 __pad_7; + u16 ier_set; + u16 __pad_8; + u16 ier_clear; + u16 __pad_9; + u16 thr; + u16 __pad_10; + u16 rbr; + u16 __pad_11; +#else + union { + u16 dll; + u16 thr; + const u16 rbr; + }; + const u16 __spad0; + union { + u16 dlh; + u16 ier; + }; + const u16 __spad1; + const u16 iir; + u16 __pad_0; + u16 lcr; + u16 __pad_1; + u16 mcr; + u16 __pad_2; + u16 lsr; + u16 __pad_3; + u16 msr; + u16 __pad_4; + u16 scr; + u16 __pad_5; + const u32 __spad2; + u16 gctl; + u16 __pad_6; +#endif +}; + +#define uart_lsr_t uint32_t +#define _lsr_read(p) bfin_read(&p->lsr) +#define _lsr_write(p, v) bfin_write(&p->lsr, v) + +#if BFIN_UART_HW_VER == 2 +# define ACCESS_LATCH() +# define ACCESS_PORT_IER() +#else +# define ACCESS_LATCH() bfin_write_or(&pUART->lcr, DLAB) +# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB) +#endif + +__attribute__((always_inline)) +static inline void serial_early_do_mach_portmux(char port, int mux_mask, + int mux_func, int port_pin) +{ + switch (port) { +#if defined(__ADSPBF54x__) + case 'B': + bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin); + break; + case 'E': + bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin); + break; +#endif +#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__) + case 'F': + bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin); + break; + case 'G': + bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin); + break; + case 'H': + bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin); + break; +#endif + default: + break; + } +} + +__attribute__((always_inline)) +static inline void serial_early_do_portmux(void) +{ +#if defined(__ADSPBF50x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */ + serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */ + break; + case 1: + serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK, + PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */ + serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK, + PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */ + break; + } +#elif defined(__ADSPBF51x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */ + serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */ + break; + case 1: + serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK, + PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */ + serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK, + PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */ + break; + } +#elif defined(__ADSPBF52x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK, + PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */ + serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK, + PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */ + break; + case 1: + serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */ + serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */ + break; + } +#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) + const uint16_t func[] = { PFDE, PFTE, }; + bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]); + bfin_write_PORTF_FER(bfin_read_PORTF_FER() | + (1 << P_IDENT(P_UART(RX))) | + (1 << P_IDENT(P_UART(TX)))); +#elif defined(__ADSPBF54x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */ + serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK, + PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */ + break; + case 1: + serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK, + PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */ + serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK, + PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */ + break; + case 2: + serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK, + PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */ + serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK, + PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */ + break; + case 3: + serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK, + PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */ + serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */ + break; + } +#elif defined(__ADSPBF561__) + /* UART pins could be GPIO, but they aren't pin muxed. */ +#else +# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) +# error "missing portmux logic for UART" +# endif +#endif + SSYNC(); +} + +__attribute__((always_inline)) +static inline int uart_init(uint32_t uart_base) +{ + /* always enable UART -- avoids anomalies 05000309 and 05000350 */ + bfin_write(&pUART->gctl, UCEN); + + /* Set LCR to Word Lengh 8-bit word select */ + bfin_write(&pUART->lcr, WLS_8); + + SSYNC(); + + return 0; +} + +__attribute__((always_inline)) +static inline int serial_early_init(uint32_t uart_base) +{ + /* handle portmux crap on different Blackfins */ + serial_do_portmux(); + + return uart_init(uart_base); +} + +__attribute__((always_inline)) +static inline int serial_early_uninit(uint32_t uart_base) +{ + /* disable the UART by clearing UCEN */ + bfin_write(&pUART->gctl, 0); + + return 0; +} + +__attribute__((always_inline)) +static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor) +{ + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH(); + SSYNC(); + + /* Program the divisor to get the baud rate we want */ + bfin_write(&pUART->dll, LOB(divisor)); + bfin_write(&pUART->dlh, HIB(divisor)); + SSYNC(); + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER(); + SSYNC(); +} + +__attribute__((always_inline)) +static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) +{ + /* Translate from baud into divisor in terms of SCLK. The + * weird multiplication is to make sure we over sample just + * a little rather than under sample the incoming signals. + */ +#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS + uint16_t divisor = (early_get_uart_clk() + baud * 8) / (baud * 16) + - ANOMALY_05000230; +#else + uint16_t divisor = early_division(early_get_uart_clk() + (baud * 8), + baud * 16) - ANOMALY_05000230; +#endif + + serial_set_divisor(uart_base, divisor); +} + +__attribute__((always_inline)) +static inline void serial_early_put_div(uint16_t divisor) +{ + uint32_t uart_base = UART_BASE; + + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH(); + SSYNC(); + + /* Program the divisor to get the baud rate we want */ + bfin_write(&pUART->dll, LOB(divisor)); + bfin_write(&pUART->dlh, HIB(divisor)); + SSYNC(); + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER(); + SSYNC(); +} + +__attribute__((always_inline)) +static inline uint16_t serial_early_get_div(void) +{ + uint32_t uart_base = UART_BASE; + + /* Set DLAB in LCR to Access DLL and DLH */ + ACCESS_LATCH(); + SSYNC(); + + uint8_t dll = bfin_read(&pUART->dll); + uint8_t dlh = bfin_read(&pUART->dlh); + uint16_t divisor = (dlh << 8) | dll; + + /* Clear DLAB in LCR to Access THR RBR IER */ + ACCESS_PORT_IER(); + SSYNC(); + + return divisor; +} + +#endif + +#endif diff --git a/arch/blackfin/include/asm/serial4.h b/arch/blackfin/include/asm/serial4.h new file mode 100644 index 0000000000..65483960b9 --- /dev/null +++ b/arch/blackfin/include/asm/serial4.h @@ -0,0 +1,150 @@ +/* + * serial.h - common serial defines for early debug and serial driver. + * any functions defined here must be always_inline since + * initcode cannot have function calls. + * + * Copyright (c) 2004-2011 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __BFIN_CPU_SERIAL4_H__ +#define __BFIN_CPU_SERIAL4_H__ + +#include + +#ifndef __ASSEMBLY__ + +#include + +#define MMR_UART(n) _PASTE_UART(n, UART, REVID) +#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE) + +struct bfin_mmr_serial { + u32 revid; + u32 control; + u32 status; + u32 scr; + u32 clock; + u32 emask; + u32 emaskst; + u32 emaskcl; + u32 rbr; + u32 thr; + u32 taip; + u32 tsr; + u32 rsr; + u32 txdiv_cnt; + u32 rxdiv_cnt; +}; +#define uart_lsr_t uint32_t +#define _lsr_read(p) bfin_read(&p->status) +#define _lsr_write(p, v) bfin_write(&p->status, v) + +__attribute__((always_inline)) +static inline void serial_early_do_mach_portmux(char port, int mux_mask, + int mux_func, int port_pin) +{ + switch (port) { + case 'D': + bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTD_FER_SET(port_pin); + break; + case 'G': + bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & + ~mux_mask) | mux_func); + bfin_write_PORTG_FER_SET(port_pin); + break; + } +} + +__attribute__((always_inline)) +static inline void serial_early_do_portmux(void) +{ +#if defined(__ADSPBF60x__) + switch (CONFIG_UART_CONSOLE) { + case 0: + serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK, + PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */ + serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK, + PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */ + break; + case 1: + serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK, + PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */ + serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK, + PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */ + break; + } +#else +# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED) +# error "missing portmux logic for UART" +# endif +#endif + SSYNC(); +} + +__attribute__((always_inline)) +static inline int uart_init(uint32_t uart_base) +{ + /* always enable UART to 8-bit mode */ + bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8); + + SSYNC(); + + return 0; +} + +__attribute__((always_inline)) +static inline int serial_early_init(uint32_t uart_base) +{ + /* handle portmux crap on different Blackfins */ + serial_do_portmux(); + + return uart_init(uart_base); +} + +__attribute__((always_inline)) +static inline int serial_early_uninit(uint32_t uart_base) +{ + /* disable the UART by clearing UEN */ + bfin_write(&pUART->control, 0); + + return 0; +} + +__attribute__((always_inline)) +static inline void serial_set_divisor(uint32_t uart_base, uint16_t divisor) +{ + /* Program the divisor to get the baud rate we want */ + bfin_write(&pUART->clock, divisor); + SSYNC(); +} + +__attribute__((always_inline)) +static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud) +{ + uint16_t divisor = early_division(early_get_uart_clk(), baud * 16); + + /* Program the divisor to get the baud rate we want */ + serial_set_divisor(uart_base, divisor); +} + +__attribute__((always_inline)) +static inline void serial_early_put_div(uint32_t divisor) +{ + uint32_t uart_base = UART_BASE; + bfin_write(&pUART->clock, divisor); +} + +__attribute__((always_inline)) +static inline uint32_t serial_early_get_div(void) +{ + uint32_t uart_base = UART_BASE; + return bfin_read(&pUART->clock); +} + +#endif + +#endif -- cgit v1.2.3 From da34aae5fba36c1f1989fdd41fffa723f300eaad Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 2 May 2013 13:46:21 +0800 Subject: bfin: Move gpio support for bf54x and bf60x into the generic driver folder. The gpio spec for bf54x and bf60x differ a lot from the old gpio driver for bf5xx. A lot of machine macros are used to accomodate both code in one gpio driver. This patch split the old gpio driver and move new gpio2 support to the generic gpio driver folder. - To enable gpio2 driver, macro CONFIG_ADI_GPIO2 should be defined in the board's config header file. - The gpio2 driver supports bf54x, bf60x and future ADI processors, while the older gpio driver supports bf50x, bf51x, bf52x, bf53x and bf561. - All blackfin specific gpio function names are replaced by the generic gpio APIs. Signed-off-by: Sonic Zhang --- arch/blackfin/include/asm/gpio.h | 62 ++++++------------------------------- arch/blackfin/include/asm/portmux.h | 5 --- 2 files changed, 10 insertions(+), 57 deletions(-) (limited to 'arch/blackfin/include/asm') diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h index 05131b5e8b..58a6191107 100644 --- a/arch/blackfin/include/asm/gpio.h +++ b/arch/blackfin/include/asm/gpio.h @@ -7,6 +7,8 @@ #ifndef __ARCH_BLACKFIN_GPIO_H__ #define __ARCH_BLACKFIN_GPIO_H__ +#include + #define gpio_bank(x) ((x) >> 4) #define gpio_bit(x) (1<<((x) & 0xF)) #define gpio_sub_n(x) ((x) & 0xF) @@ -65,10 +67,11 @@ #define PERIPHERAL_USAGE 1 #define GPIO_USAGE 0 +#define MAX_GPIOS MAX_BLACKFIN_GPIOS #ifndef __ASSEMBLY__ -#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x) +#ifdef CONFIG_ADI_GPIO1 void set_gpio_dir(unsigned, unsigned short); void set_gpio_inen(unsigned, unsigned short); void set_gpio_polar(unsigned, unsigned short); @@ -140,61 +143,16 @@ struct gpio_port_t { }; #endif -#ifdef CONFIG_BFIN_GPIO_TRACK -void bfin_gpio_labels(void); -void bfin_gpio_free(unsigned gpio); -#else -#define bfin_gpio_labels() -#define bfin_gpio_free(gpio) -#define bfin_gpio_request(gpio, label) bfin_gpio_request(gpio) -#define bfin_special_gpio_request(gpio, label) bfin_special_gpio_request(gpio) -#endif - -#ifdef BFIN_SPECIAL_GPIO_BANKS -void bfin_special_gpio_free(unsigned gpio); -int bfin_special_gpio_request(unsigned gpio, const char *label); +#ifdef ADI_SPECIAL_GPIO_BANKS +void special_gpio_free(unsigned gpio); +int special_gpio_request(unsigned gpio, const char *label); #endif -int bfin_gpio_request(unsigned gpio, const char *label); -int bfin_gpio_direction_input(unsigned gpio); -int bfin_gpio_direction_output(unsigned gpio, int value); -int bfin_gpio_get_value(unsigned gpio); -void bfin_gpio_set_value(unsigned gpio, int value); -void bfin_gpio_toggle_value(unsigned gpio); - -static inline int gpio_request(unsigned gpio, const char *label) -{ - return bfin_gpio_request(gpio, label); -} - -static inline void gpio_free(unsigned gpio) -{ - return bfin_gpio_free(gpio); -} - -static inline int gpio_direction_input(unsigned gpio) -{ - return bfin_gpio_direction_input(gpio); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return bfin_gpio_direction_output(gpio, value); -} - -static inline int gpio_get_value(unsigned gpio) -{ - return bfin_gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - return bfin_gpio_set_value(gpio, value); -} +void gpio_labels(void); static inline int gpio_is_valid(int number) { - return number >= 0 && number < MAX_BLACKFIN_GPIOS; + return number >= 0 && number < MAX_GPIOS; } #include @@ -248,7 +206,7 @@ static inline int name_to_gpio(const char *name) } #define name_to_gpio(n) name_to_gpio(n) -#define gpio_status() bfin_gpio_labels() +#define gpio_status() gpio_labels() #endif /* __ASSEMBLY__ */ diff --git a/arch/blackfin/include/asm/portmux.h b/arch/blackfin/include/asm/portmux.h index 300ef44fd1..003694b515 100644 --- a/arch/blackfin/include/asm/portmux.h +++ b/arch/blackfin/include/asm/portmux.h @@ -17,11 +17,6 @@ #define P_MAYSHARE 0x2000 #define P_DONTCARE 0x1000 -#ifndef CONFIG_BFIN_GPIO_TRACK -#define peripheral_request(per, label) peripheral_request(per) -#define peripheral_request_list(per, label) peripheral_request_list(per) -#endif - #ifndef __ASSEMBLY__ int peripheral_request(unsigned short per, const char *label); -- cgit v1.2.3