From d83b47b778805e2d3cfc9f6b14437f389f9da49f Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Feb 2016 13:04:17 -0800 Subject: arm: ls1021aqds: Convert to driver model and enable serial support Split duart configuration as device tree file. Move /chosen node out of board commone device tree. Convert ls1021aqds nor and SD configurations to driver model support (qspi already uses DM). Enable ns16550 DM serial driver for nor configurations. Signed-off-by: York Sun CC: Alison Wang CC: Bin Meng Reviewed-by: Bin Meng Reviewed-by: Alison Wang --- arch/arm/dts/Makefile | 2 +- arch/arm/dts/ls1021a-qds-duart.dts | 16 +++ arch/arm/dts/ls1021a-qds.dts | 216 ---------------------------------- arch/arm/dts/ls1021a-qds.dtsi | 215 +++++++++++++++++++++++++++++++++ configs/ls1021aqds_ddr4_nor_defconfig | 4 + configs/ls1021aqds_nor_defconfig | 4 + configs/ls1021aqds_qspi_defconfig | 2 +- configs/ls1021aqds_sdcard_defconfig | 3 + include/configs/ls1021aqds.h | 2 + 9 files changed, 246 insertions(+), 218 deletions(-) create mode 100644 arch/arm/dts/ls1021a-qds-duart.dts delete mode 100644 arch/arm/dts/ls1021a-qds.dts create mode 100644 arch/arm/dts/ls1021a-qds.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b574284262..7af45bb20f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -96,7 +96,7 @@ dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb -dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ +dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-rdb.dtb diff --git a/arch/arm/dts/ls1021a-qds-duart.dts b/arch/arm/dts/ls1021a-qds-duart.dts new file mode 100644 index 0000000000..bc568673ce --- /dev/null +++ b/arch/arm/dts/ls1021a-qds-duart.dts @@ -0,0 +1,16 @@ +/* + * Freescale ls1021a QDS board common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ls1021a-qds.dtsi" + +/ { + chosen { + stdout-path = &uart0; + }; +}; diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts deleted file mode 100644 index e634292359..0000000000 --- a/arch/arm/dts/ls1021a-qds.dts +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Freescale ls1021a QDS board device tree source - * - * Copyright 2013-2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/dts-v1/; -#include "ls1021a.dtsi" - -/ { - model = "LS1021A QDS Board"; - - aliases { - enet0_rgmii_phy = &rgmii_phy1; - enet1_rgmii_phy = &rgmii_phy2; - enet2_rgmii_phy = &rgmii_phy3; - enet0_sgmii_phy = &sgmii_phy1c; - enet1_sgmii_phy = &sgmii_phy1d; - spi0 = &qspi; - spi1 = &dspi0; - }; -}; - -&dspi0 { - bus-num = <0>; - status = "okay"; - - dspiflash: at45db021d@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,dataflash"; - spi-max-frequency = <16000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; -}; - -&qspi { - bus-num = <0>; - status = "okay"; - - qflash0: s25fl128s@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-flash"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; - - pca9547: mux@77 { - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - - ds3232: rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - interrupts = ; - }; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; - - ina220@40 { - compatible = "ti,ina220"; - reg = <0x40>; - shunt-resistor = <1000>; - }; - - ina220@41 { - compatible = "ti,ina220"; - reg = <0x41>; - shunt-resistor = <1000>; - }; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - eeprom@56 { - compatible = "atmel,24c512"; - reg = <0x56>; - }; - - eeprom@57 { - compatible = "atmel,24c512"; - reg = <0x57>; - }; - - adt7461a@4c { - compatible = "adi,adt7461a"; - reg = <0x4c>; - }; - }; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0x0 0x0 0x60000000 0x08000000 - 0x2 0x0 0x7e800000 0x00010000 - 0x3 0x0 0x7fb00000 0x00000100>; - status = "okay"; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; - - fpga: board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - reg = <0x3 0x0 0x0000100>; - bank-width = <1>; - device-width = <1>; - ranges = <0 3 0 0x100>; - - mdio-mux-emi1 { - compatible = "mdio-mux-mmioreg"; - mdio-parent-bus = <&mdio0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x54 1>; /* BRDCFG4 */ - mux-mask = <0xe0>; /* EMI1[2:0] */ - - /* Onboard PHYs */ - ls1021amdio0: mdio@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - }; - - ls1021amdio1: mdio@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - }; - - ls1021amdio2: mdio@40 { - reg = <0x40>; - #address-cells = <1>; - #size-cells = <0>; - rgmii_phy3: ethernet-phy@3 { - reg = <0x3>; - }; - }; - - ls1021amdio3: mdio@60 { - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - sgmii_phy1c: ethernet-phy@1c { - reg = <0x1c>; - }; - }; - - ls1021amdio4: mdio@80 { - reg = <0x80>; - #address-cells = <1>; - #size-cells = <0>; - sgmii_phy1d: ethernet-phy@1d { - reg = <0x1d>; - }; - }; - }; - }; -}; - -&lpuart0 { - status = "okay"; -}; - -&mdio0 { - tbi0: tbi-phy@8 { - reg = <0x8>; - device_type = "tbi-phy"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; diff --git a/arch/arm/dts/ls1021a-qds.dtsi b/arch/arm/dts/ls1021a-qds.dtsi new file mode 100644 index 0000000000..ca9e835a06 --- /dev/null +++ b/arch/arm/dts/ls1021a-qds.dtsi @@ -0,0 +1,215 @@ +/* + * Freescale ls1021a QDS board common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "ls1021a.dtsi" + +/ { + model = "LS1021A QDS Board"; + + aliases { + enet0_rgmii_phy = &rgmii_phy1; + enet1_rgmii_phy = &rgmii_phy2; + enet2_rgmii_phy = &rgmii_phy3; + enet0_sgmii_phy = &sgmii_phy1c; + enet1_sgmii_phy = &sgmii_phy1d; + spi0 = &qspi; + spi1 = &dspi0; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dspiflash: at45db021d@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,dataflash"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; + + pca9547: mux@77 { + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + ds3232: rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + interrupts = ; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + eeprom@56 { + compatible = "atmel,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "atmel,24c512"; + reg = <0x57>; + }; + + adt7461a@4c { + compatible = "adi,adt7461a"; + reg = <0x4c>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x7fb00000 0x00000100>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + reg = <0x3 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 3 0 0x100>; + + mdio-mux-emi1 { + compatible = "mdio-mux-mmioreg"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1[2:0] */ + + /* Onboard PHYs */ + ls1021amdio0: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + + ls1021amdio1: mdio@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + ls1021amdio2: mdio@40 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + }; + + ls1021amdio3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy1c: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + + ls1021amdio4: mdio@80 { + reg = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy1d: ethernet-phy@1d { + reg = <0x1d>; + }; + }; + }; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + tbi0: tbi-phy@8 { + reg = <0x8>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 2f16339d18..842f645d6c 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -1,7 +1,11 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" # CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index 6878df4980..f4c81e2ae0 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -1,6 +1,10 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" # CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 0f740fd902..2e98d6c28b 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds" +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/ls1021aqds_sdcard_defconfig b/configs/ls1021aqds_sdcard_defconfig index 3249b4884f..e283f69629 100644 --- a/configs/ls1021aqds_sdcard_defconfig +++ b/configs/ls1021aqds_sdcard_defconfig @@ -1,8 +1,11 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" # CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index f6efc55059..5bdc124475 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -375,7 +375,9 @@ unsigned long get_board_ddr_clk(void); #else #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 +#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif -- cgit v1.2.3 From 2f7d70082c55c0560da5a95c68dabb15abbeca5a Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Feb 2016 13:47:29 -0800 Subject: arm: ls1021aqds: Enable driver model lpuart serial driver Convert ls1021aqds_nor_lpuart and ls1021aqds_ddr4_nor_lpuart to driver model suport. Enable lpuart port driver. Signed-off-by: York Sun CC: Alison Wang CC: Bin Meng Reviewed-by: Bin Meng Reviewed-by: Alison Wang --- arch/arm/dts/Makefile | 1 + arch/arm/dts/ls1021a-qds-lpuart.dts | 16 ++++++++++++++++ configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 4 ++++ configs/ls1021aqds_nor_lpuart_defconfig | 4 ++++ 4 files changed, 25 insertions(+) create mode 100644 arch/arm/dts/ls1021a-qds-lpuart.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7af45bb20f..578038be21 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -97,6 +97,7 @@ dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \ + ls1021a-qds-lpuart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-rdb.dtb diff --git a/arch/arm/dts/ls1021a-qds-lpuart.dts b/arch/arm/dts/ls1021a-qds-lpuart.dts new file mode 100644 index 0000000000..1d16ffd975 --- /dev/null +++ b/arch/arm/dts/ls1021a-qds-lpuart.dts @@ -0,0 +1,16 @@ +/* + * Freescale ls1021a QDS board common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ls1021a-qds.dtsi" + +/ { + chosen { + stdout-path = &lpuart0; + }; +}; diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index 44b2a0d1e5..0e1a59d3e9 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -1,7 +1,11 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" # CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_FSL_LPUART=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 1186af2a14..e81448dc0e 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -1,7 +1,11 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart" CONFIG_SYS_EXTRA_OPTIONS="LPUART" # CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_FSL_LPUART=y -- cgit v1.2.3 From 9e71bb9ca232038e8cdc1090cf218871afb6904a Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Thu, 14 Jan 2016 18:12:29 +0530 Subject: armv8: ls2080a: Increase default hugepage count Increase default hugepage count to 256 from 16 Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 2 +- include/configs/ls2080ardb.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index def0a6f3f0..31c6e85b6c 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -269,7 +269,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ - " hugepagesz=2m hugepages=16" + " hugepagesz=2m hugepages=256" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 10 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 116dbcde5b..356d254159 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -333,7 +333,7 @@ unsigned long get_board_sys_clk(void); #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0600" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ - " hugepagesz=2m hugepages=16" + " hugepagesz=2m hugepages=256" /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET -- cgit v1.2.3 From 7f4736bd657afca7c224efb27cab496acd9ee021 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Fri, 22 Jan 2016 16:12:55 +0530 Subject: drivers/crypto/fsl : Allocate output ring with size aligned to CACHELNE SIZE The output ring needs to be invalidated before enqueuing the job to SEC. While allocation of space to output ring, it should be taken care that the size is cacheline size aligned inorder to prevent invalidating valid data. The patch also correct the method of aligning end of structs while flushing caches Since start = align(start_of_struct), it is incorrect to assign end = align(start + struct_size). It should instead be, end = align(start_of_struct + struct_size). Signed-off-by: Saksham Jain Signed-off-by: Ruchika Gupta Reviewed-by: York Sun --- drivers/crypto/fsl/jr.c | 28 ++++++++++++++++------------ drivers/crypto/fsl/jr.h | 2 ++ 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index b553e3c583..4566ec3671 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -95,14 +95,16 @@ static int jr_init(void) JR_SIZE * sizeof(dma_addr_t)); if (!jr.input_ring) return -1; + + jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring), + ARCH_DMA_MINALIGN); jr.output_ring = - (struct op_ring *)memalign(ARCH_DMA_MINALIGN, - JR_SIZE * sizeof(struct op_ring)); + (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size); if (!jr.output_ring) return -1; memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t)); - memset(jr.output_ring, 0, JR_SIZE * sizeof(struct op_ring)); + memset(jr.output_ring, 0, jr.op_size); start_jr0(); @@ -190,8 +192,8 @@ static int jr_enqueue(uint32_t *desc_addr, unsigned long start = (unsigned long)&jr.info[head] & ~(ARCH_DMA_MINALIGN - 1); - unsigned long end = ALIGN(start + sizeof(struct jr_info), - ARCH_DMA_MINALIGN); + unsigned long end = ALIGN((unsigned long)&jr.info[head] + + sizeof(struct jr_info), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); #ifdef CONFIG_PHYS_64BIT @@ -216,11 +218,19 @@ static int jr_enqueue(uint32_t *desc_addr, #endif /* ifdef CONFIG_PHYS_64BIT */ start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); - end = ALIGN(start + sizeof(phys_addr_t), ARCH_DMA_MINALIGN); + end = ALIGN((unsigned long)&jr.input_ring[head] + + sizeof(dma_addr_t), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); jr.head = (head + 1) & (jr.size - 1); + /* Invalidate output ring */ + start = (unsigned long)jr.output_ring & + ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)jr.output_ring + jr.op_size, + ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); + sec_out32(®s->irja, 1); return 0; @@ -241,12 +251,6 @@ static int jr_dequeue(void) #endif while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) { - unsigned long start = (unsigned long)jr.output_ring & - ~(ARCH_DMA_MINALIGN - 1); - unsigned long end = ALIGN(start + - sizeof(struct op_ring)*JR_SIZE, - ARCH_DMA_MINALIGN); - invalidate_dcache_range(start, end); found = 0; diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 5899696e8a..545d964ced 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -72,6 +72,8 @@ struct jobring { int write_idx; /* Size of the rings. */ int size; + /* Op ring size aligned to cache line size */ + int op_size; /* The ip and output rings have to be accessed by SEC. So the * pointers will ahve to point to the housekeeping region provided * by SEC -- cgit v1.2.3 From f698e9f39aaf8ed30dab86f0130ea1e21bc721cc Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Fri, 22 Jan 2016 17:05:59 +0530 Subject: powerpc/SECURE_BOOT: Add PAMU driver PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 18 +- arch/powerpc/cpu/mpc8xxx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 433 ++++++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xxx/pamu_table.c | 55 +++++ arch/powerpc/include/asm/fsl_pamu.h | 169 +++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 19 +- drivers/crypto/fsl/jr.c | 23 ++ 7 files changed, 709 insertions(+), 9 deletions(-) create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_pamu.c create mode 100644 arch/powerpc/cpu/mpc8xxx/pamu_table.c create mode 100644 arch/powerpc/include/asm/fsl_pamu.h diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 80bbc1805f..4ae4a6c83d 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,6 +37,10 @@ #ifdef CONFIG_FSL_CAAM #include #endif +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) +#include +#include +#endif #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include #include @@ -432,8 +436,7 @@ void fsl_erratum_a007212_workaround(void) ulong cpu_init_f(void) { extern void m8560_cpm_reset (void); -#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \ - (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)) +#ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_SECURE_BOOT) @@ -465,12 +468,6 @@ ulong cpu_init_f(void) #if defined(CONFIG_SYS_CPC_REINIT_F) disable_cpc_sram(); #endif - -#if defined(CONFIG_FSL_CORENET) - /* Put PAMU in bypass mode */ - out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS); -#endif - #endif #ifdef CONFIG_CPM2 @@ -954,6 +951,11 @@ int cpu_init_r(void) fman_enet_init(); #endif +#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET) + if (pamu_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); +#endif + #ifdef CONFIG_FSL_CAAM sec_init(); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index ac45e0e3df..c5592cdbb3 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -24,5 +24,6 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_FSL_LBC) += fsl_lbc.o obj-$(CONFIG_SYS_SRIO) += srio.o obj-$(CONFIG_FSL_LAW) += law.o +obj-$(CONFIG_FSL_CORENET) += fsl_pamu.o pamu_table.o endif diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c new file mode 100644 index 0000000000..9421f1ebf6 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -0,0 +1,433 @@ +/* + * FSL PAMU driver + * + * Copyright 2012-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +struct paace *ppaact; +struct paace *sec; +unsigned long fspi; + +static inline int __ilog2_roundup_64(uint64_t val) +{ + if ((val & (val - 1)) == 0) + return __ilog2_u64(val); + else + return __ilog2_u64(val) + 1; +} + + +static inline int count_lsb_zeroes(unsigned long val) +{ + return ffs(val) - 1; +} + +static unsigned int map_addrspace_size_to_wse(uint64_t addrspace_size) +{ + /* window size is 2^(WSE+1) bytes */ + return count_lsb_zeroes(addrspace_size >> PAMU_PAGE_SHIFT) + + PAMU_PAGE_SHIFT - 1; +} + +static unsigned int map_subwindow_cnt_to_wce(uint32_t subwindow_cnt) +{ + /* window count is 2^(WCE+1) bytes */ + return count_lsb_zeroes(subwindow_cnt) - 1; +} + +static void pamu_setup_default_xfer_to_host_ppaace(struct paace *ppaace) +{ + set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY); + set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR, + PAACE_M_COHERENCE_REQ); +} + +static void pamu_setup_default_xfer_to_host_spaace(struct paace *spaace) +{ + set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY); + set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR, + PAACE_M_COHERENCE_REQ); +} + +/** Sets up PPAACE entry for specified liodn + * + * @param[in] liodn Logical IO device number + * @param[in] win_addr starting address of DSA window + * @param[in] win-size size of DSA window + * @param[in] omi Operation mapping index -- if ~omi == 0 then omi + not defined + * @param[in] stashid cache stash id for associated cpu -- if ~stashid == 0 + then stashid not defined + * @param[in] snoopid snoop id for hardware coherency -- if ~snoopid == 0 + then snoopid not defined + * @param[in] subwin_cnt number of sub-windows + * + * @return Returns 0 upon success else error code < 0 returned + */ +static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr, + uint64_t win_size, uint32_t omi, + uint32_t snoopid, uint32_t stashid, + uint32_t subwin_cnt) +{ + struct paace *ppaace; + + if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE) + return -1; + + if (win_addr & (win_size - 1)) + return -2; + + if (liodn > NUM_PPAACT_ENTRIES) { + printf("Entries in PPACT not sufficient\n"); + return -3; + } + + ppaace = &ppaact[liodn]; + + /* window size is 2^(WSE+1) bytes */ + set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE, + map_addrspace_size_to_wse(win_size)); + + pamu_setup_default_xfer_to_host_ppaace(ppaace); + + if (sizeof(phys_addr_t) > 4) + ppaace->wbah = (u64)win_addr >> (PAMU_PAGE_SHIFT + 20); + else + ppaace->wbah = 0; + + set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL, + (win_addr >> PAMU_PAGE_SHIFT)); + + /* set up operation mapping if it's configured */ + if (omi < OME_NUMBER_ENTRIES) { + set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED); + ppaace->op_encode.index_ot.omi = omi; + } else if (~omi != 0) { + return -3; + } + + /* configure stash id */ + if (~stashid != 0) + set_bf(ppaace->impl_attr, PAACE_IA_CID, stashid); + + /* configure snoop id */ + if (~snoopid != 0) + ppaace->domain_attr.to_host.snpid = snoopid; + + if (subwin_cnt) { + /* window count is 2^(WCE+1) bytes */ + set_bf(ppaace->impl_attr, PAACE_IA_WCE, + map_subwindow_cnt_to_wce(subwin_cnt)); + set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0x1); + ppaace->fspi = fspi; + fspi = fspi + DEFAULT_NUM_SUBWINDOWS - 1; + } else { + set_bf(ppaace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL); + } + + asm volatile("sync" : : : "memory"); + /* Mark the ppace entry valid */ + ppaace->addr_bitfields |= PAACE_V_VALID; + asm volatile("sync" : : : "memory"); + + return 0; +} + +static int pamu_config_spaace(uint32_t liodn, + uint64_t subwin_size, uint64_t subwin_addr, uint64_t size, + uint32_t omi, uint32_t snoopid, uint32_t stashid) +{ + struct paace *paace; + /* Align start addr of subwin to subwindoe size */ + uint64_t sec_addr = subwin_addr & ~(subwin_size - 1); + uint64_t end_addr = subwin_addr + size; + int size_shift = __ilog2_u64(subwin_size); + uint64_t win_size = 0; + uint32_t index, swse; + unsigned long fspi_idx; + + /* Recalculate the size */ + size = end_addr - sec_addr; + + if (!subwin_size) + return -1; + + if (liodn > NUM_PPAACT_ENTRIES) { + printf("LIODN No programmed %d > no. of PPAACT entries %d\n", + liodn, NUM_PPAACT_ENTRIES); + return -1; + } + + while (sec_addr < end_addr) { + debug("sec_addr < end_addr is %llx < %llx\n", sec_addr, + end_addr); + paace = &ppaact[liodn]; + if (!paace) + return -1; + fspi_idx = paace->fspi; + + /* Calculating the win_size here as if we map in index 0, + paace entry woudl need to be programmed for SWSE */ + win_size = end_addr - sec_addr; + win_size = 1 << __ilog2_roundup_64(win_size); + + if (win_size > subwin_size) + win_size = subwin_size; + else if (win_size < PAMU_PAGE_SIZE) + win_size = PAMU_PAGE_SIZE; + + debug("win_size is %llx\n", win_size); + + swse = map_addrspace_size_to_wse(win_size); + index = sec_addr >> size_shift; + + if (index == 0) { + set_bf(paace->win_bitfields, PAACE_WIN_SWSE, swse); + set_bf(paace->addr_bitfields, PAACE_AF_AP, + PAACE_AP_PERMS_ALL); + sec_addr += subwin_size; + continue; + } + + paace = sec + fspi_idx + index - 1; + + debug("SPAACT:Writing at location %p, index %d\n", paace, + index); + + pamu_setup_default_xfer_to_host_spaace(paace); + set_bf(paace->addr_bitfields, SPAACE_AF_LIODN, liodn); + set_bf(paace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL); + + /* configure snoop id */ + if (~snoopid != 0) + paace->domain_attr.to_host.snpid = snoopid; + + if (paace->addr_bitfields & PAACE_V_VALID) { + debug("Reached overlap condition\n"); + debug("%d < %d\n", get_bf(paace->win_bitfields, + PAACE_WIN_SWSE), swse); + if (get_bf(paace->win_bitfields, PAACE_WIN_SWSE) < swse) + set_bf(paace->win_bitfields, PAACE_WIN_SWSE, + swse); + } else { + set_bf(paace->win_bitfields, PAACE_WIN_SWSE, swse); + } + + paace->addr_bitfields |= PAACE_V_VALID; + sec_addr += subwin_size; + } + + return 0; +} + +int pamu_init(void) +{ + u32 base_addr = CONFIG_SYS_PAMU_ADDR; + struct ccsr_pamu *regs; + u32 i = 0; + u64 ppaact_phys, ppaact_lim, ppaact_size; + u64 spaact_phys, spaact_lim, spaact_size; + + ppaact_size = sizeof(struct paace) * NUM_PPAACT_ENTRIES; + spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES; + + /* Allocate space for Primary PAACT Table */ + ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size); + if (!ppaact) + return -1; + memset(ppaact, 0, ppaact_size); + + /* Allocate space for Secondary PAACT Table */ + sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size); + if (!sec) + return -1; + memset(sec, 0, spaact_size); + + ppaact_phys = virt_to_phys((void *)ppaact); + ppaact_lim = ppaact_phys + ppaact_size; + + spaact_phys = (uint64_t)virt_to_phys((void *)sec); + spaact_lim = spaact_phys + spaact_size; + + /* Configure all PAMU's */ + for (i = 0; i < CONFIG_NUM_PAMU; i++) { + regs = (struct ccsr_pamu *)base_addr; + + out_be32(®s->ppbah, ppaact_phys >> 32); + out_be32(®s->ppbal, (uint32_t)ppaact_phys); + + out_be32(®s->pplah, (ppaact_lim) >> 32); + out_be32(®s->pplal, (uint32_t)ppaact_lim); + + if (sec != NULL) { + out_be32(®s->spbah, spaact_phys >> 32); + out_be32(®s->spbal, (uint32_t)spaact_phys); + out_be32(®s->splah, spaact_lim >> 32); + out_be32(®s->splal, (uint32_t)spaact_lim); + } + asm volatile("sync" : : : "memory"); + + base_addr += PAMU_OFFSET; + } + + return 0; +} + +void pamu_enable(void) +{ + u32 i = 0; + u32 base_addr = CONFIG_SYS_PAMU_ADDR; + for (i = 0; i < CONFIG_NUM_PAMU; i++) { + setbits_be32((void *)base_addr + PAMU_PCR_OFFSET, + PAMU_PCR_PE); + asm volatile("sync" : : : "memory"); + base_addr += PAMU_OFFSET; + } +} + +void pamu_reset(void) +{ + u32 i = 0; + u32 base_addr = CONFIG_SYS_PAMU_ADDR; + struct ccsr_pamu *regs; + + for (i = 0; i < CONFIG_NUM_PAMU; i++) { + regs = (struct ccsr_pamu *)base_addr; + /* Clear PPAACT Base register */ + out_be32(®s->ppbah, 0); + out_be32(®s->ppbal, 0); + out_be32(®s->pplah, 0); + out_be32(®s->pplal, 0); + out_be32(®s->spbah, 0); + out_be32(®s->spbal, 0); + out_be32(®s->splah, 0); + out_be32(®s->splal, 0); + + clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE); + asm volatile("sync" : : : "memory"); + base_addr += PAMU_OFFSET; + } +} + +void pamu_disable(void) +{ + u32 i = 0; + u32 base_addr = CONFIG_SYS_PAMU_ADDR; + + + for (i = 0; i < CONFIG_NUM_PAMU; i++) { + clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); + asm volatile("sync" : : : "memory"); + base_addr += PAMU_OFFSET; + } +} + + +static uint64_t find_max(uint64_t arr[], int num) +{ + int i = 0; + int max = 0; + for (i = 1 ; i < num; i++) + if (arr[max] < arr[i]) + max = i; + + return arr[max]; +} + +static uint64_t find_min(uint64_t arr[], int num) +{ + int i = 0; + int min = 0; + for (i = 1 ; i < num; i++) + if (arr[min] > arr[i]) + min = i; + + return arr[min]; +} + +static uint32_t get_win_cnt(uint64_t size) +{ + uint32_t win_cnt = DEFAULT_NUM_SUBWINDOWS; + + while (win_cnt && (size/win_cnt) < PAMU_PAGE_SIZE) + win_cnt >>= 1; + + return win_cnt; +} + +int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn) +{ + int i = 0; + int ret = 0; + uint32_t num_sec_windows = 0; + uint32_t num_windows = 0; + uint64_t min_addr, max_addr; + uint64_t size; + uint64_t subwin_size; + int sizebit; + + min_addr = find_min(tbl->start_addr, num_entries); + max_addr = find_max(tbl->end_addr, num_entries); + size = max_addr - min_addr + 1; + + if (!size) + return -1; + + sizebit = __ilog2_roundup_64(size); + size = 1 << sizebit; + debug("min start_addr is %llx\n", min_addr); + debug("max end_addr is %llx\n", max_addr); + debug("size found is %llx\n", size); + + if (size < PAMU_PAGE_SIZE) + size = PAMU_PAGE_SIZE; + + while (1) { + min_addr = min_addr & ~(size - 1); + if (min_addr + size > max_addr) + break; + size <<= 1; + if (!size) + return -1; + } + debug("PAACT :Base addr is %llx\n", min_addr); + debug("PAACT : Size is %llx\n", size); + num_windows = get_win_cnt(size); + /* For a single window, no spaact entries are required + * sec_sub_window count = 0 */ + if (num_windows > 1) + num_sec_windows = num_windows; + else + num_sec_windows = 0; + + ret = pamu_config_ppaace(liodn, min_addr, + size , -1, -1, -1, num_sec_windows); + + if (ret < 0) + return ret; + + debug("configured ppace\n"); + + if (num_sec_windows) { + subwin_size = size >> count_lsb_zeroes(num_sec_windows); + debug("subwin_size is %llx\n", subwin_size); + + for (i = 0; i < num_entries; i++) { + ret = pamu_config_spaace(liodn, + subwin_size, tbl->start_addr[i] - min_addr, + tbl->size[i], -1, -1, -1); + + if (ret < 0) + return ret; + } + } + + return ret; +} diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c new file mode 100644 index 0000000000..26c5ea4fd7 --- /dev/null +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -0,0 +1,55 @@ +/* + * Copyright 2012-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) +{ + int i = 0; + int j; + + tbl->start_addr[i] = + (uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE); + tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED)); + tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; + + i++; +#ifdef CONFIG_SYS_FLASH_BASE_PHYS + tbl->start_addr[i] = + (uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS); + tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */ + tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; + + i++; +#endif + debug("PAMU address\t\t\tsize\n"); + for (j = 0; j < i ; j++) + debug("%llx \t\t\t%llx\n", tbl->start_addr[j], tbl->size[j]); + + *num_entries = i; +} + +int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s) +{ + struct pamu_addr_tbl tbl; + int num_entries = 0; + int ret = 0; + + construct_pamu_addr_table(&tbl, &num_entries); + + ret = config_pamu(&tbl, num_entries, liodn_ns); + if (ret) + return ret; + + ret = config_pamu(&tbl, num_entries, liodn_s); + if (ret) + return ret; + + return ret; +} diff --git a/arch/powerpc/include/asm/fsl_pamu.h b/arch/powerpc/include/asm/fsl_pamu.h new file mode 100644 index 0000000000..93a7cae972 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_pamu.h @@ -0,0 +1,169 @@ +/* + * Copyright 2012-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PAMU_H +#define __PAMU_H + +#define CONFIG_NUM_PAMU 16 +#define NUM_PPAACT_ENTRIES 512 +#define NUM_SPAACT_ENTRIES 256 + +/* PAMU_OFFSET to the next pamu space in ccsr */ +#define PAMU_OFFSET 0x1000 + +#define PAMU_TABLE_ALIGNMENT 0x00001000 + +#define PAMU_PAGE_SHIFT 12 +#define PAMU_PAGE_SIZE 4096U + +#define PAACE_M_COHERENCE_REQ 0x01 + +#define PAACE_DA_HOST_CR 0x80 +#define PAACE_DA_HOST_CR_SHIFT 7 + +#define PAACE_AF_PT 0x00000002 +#define PAACE_AF_PT_SHIFT 1 + +#define PAACE_PT_PRIMARY 0x0 +#define PAACE_PT_SECONDARY 0x1 + +#define PPAACE_AF_WBAL 0xfffff000 +#define PPAACE_AF_WBAL_SHIFT 12 + +#define OME_NUMBER_ENTRIES 16 /* based on P4080 2.0 silicon plan */ + +#define PAACE_IA_CID 0x00FF0000 +#define PAACE_IA_CID_SHIFT 16 +#define PAACE_IA_WCE 0x000000F0 +#define PAACE_IA_WCE_SHIFT 4 +#define PAACE_IA_ATM 0x0000000C +#define PAACE_IA_ATM_SHIFT 2 +#define PAACE_IA_OTM 0x00000003 +#define PAACE_IA_OTM_SHIFT 0 + +#define PAACE_OTM_NO_XLATE 0x00 +#define PAACE_OTM_IMMEDIATE 0x01 +#define PAACE_OTM_INDEXED 0x02 +#define PAACE_OTM_RESERVED 0x03 +#define PAACE_ATM_NO_XLATE 0x00 +#define PAACE_ATM_WINDOW_XLATE 0x01 +#define PAACE_ATM_PAGE_XLATE 0x02 +#define PAACE_ATM_WIN_PG_XLATE \ + (PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE) +#define PAACE_WIN_TWBAL 0xfffff000 +#define PAACE_WIN_TWBAL_SHIFT 12 +#define PAACE_WIN_SWSE 0x00000fc0 +#define PAACE_WIN_SWSE_SHIFT 6 + +#define PAACE_AF_AP 0x00000018 +#define PAACE_AF_AP_SHIFT 3 +#define PAACE_AF_DD 0x00000004 +#define PAACE_AF_DD_SHIFT 2 +#define PAACE_AF_PT 0x00000002 +#define PAACE_AF_PT_SHIFT 1 +#define PAACE_AF_V 0x00000001 +#define PAACE_AF_V_SHIFT 0 +#define PPAACE_AF_WSE 0x00000fc0 +#define PPAACE_AF_WSE_SHIFT 6 +#define PPAACE_AF_MW 0x00000020 +#define PPAACE_AF_MW_SHIFT 5 + +#define PAACE_AP_PERMS_DENIED 0x0 +#define PAACE_AP_PERMS_QUERY 0x1 +#define PAACE_AP_PERMS_UPDATE 0x2 +#define PAACE_AP_PERMS_ALL 0x3 + +#define SPAACE_AF_LIODN 0xffff0000 +#define SPAACE_AF_LIODN_SHIFT 16 +#define PAACE_V_VALID 0x1 + +#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << \ + (m##_SHIFT)) & (m))) +#define get_bf(v, m) (((v) & (m)) >> (m##_SHIFT)) + +#define DEFAULT_NUM_SUBWINDOWS 128 +#define PAMU_PCR_OFFSET 0xc10 +#define PAMU_PCR_PE 0x40000000 + +struct pamu_addr_tbl { + phys_addr_t start_addr[10]; + phys_addr_t end_addr[10]; + phys_size_t size[10]; +}; + +struct paace { + /* PAACE Offset 0x00 */ + uint32_t wbah; /* only valid for Primary PAACE */ + uint32_t addr_bitfields; /* See P/S PAACE_AF_* */ + + /* PAACE Offset 0x08 */ + /* Interpretation of first 32 bits dependent on DD above */ + union { + struct { + /* Destination ID, see PAACE_DID_* defines */ + uint8_t did; + /* Partition ID */ + uint8_t pid; + /* Snoop ID */ + uint8_t snpid; + /* coherency_required : 1 reserved : 7 */ + uint8_t coherency_required; /* See PAACE_DA_* */ + } to_host; + struct { + /* Destination ID, see PAACE_DID_* defines */ + uint8_t did; + uint8_t reserved1; + uint16_t reserved2; + } to_io; + } domain_attr; + + /* Implementation attributes + window count + address & operation + * translation modes + */ + uint32_t impl_attr; /* See PAACE_IA_* */ + + /* PAACE Offset 0x10 */ + /* Translated window base address */ + uint32_t twbah; + uint32_t win_bitfields; /* See PAACE_WIN_* */ + + /* PAACE Offset 0x18 */ + /* first secondary paace entry */ + uint32_t fspi; /* only valid for Primary PAACE */ + union { + struct { + uint8_t ioea; + uint8_t moea; + uint8_t ioeb; + uint8_t moeb; + } immed_ot; + struct { + uint16_t reserved; + uint16_t omi; + } index_ot; + } op_encode; + + /* PAACE Offset 0x20 */ + uint32_t reserved1[2]; /* not currently implemented */ + + /* PAACE Offset 0x28 */ + uint32_t reserved2[2]; /* not currently implemented */ + + /* PAACE Offset 0x30 */ + uint32_t reserved3[2]; /* not currently implemented */ + + /* PAACE Offset 0x38 */ + uint32_t reserved4[2]; /* not currently implemented */ + +}; + +int pamu_init(void); +void pamu_enable(void); +void pamu_disable(void); +int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn); +int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s); + +#endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index fd8aba42a5..53ca6d94d6 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1935,7 +1935,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) u8 res24[64]; u32 pblsr; /* Preboot loader status */ u32 pamubypenr; /* PAMU bypass enable */ -#define FSL_CORENET_PAMU_BYPASS 0xffff0000 u32 dmacr1; /* DMA control */ u8 res25[4]; u32 gensr1; /* General status */ @@ -2774,6 +2773,21 @@ typedef struct ccsr_pme { u8 res4[0x400]; } ccsr_pme_t; +struct ccsr_pamu { + u32 ppbah; + u32 ppbal; + u32 pplah; + u32 pplal; + u32 spbah; + u32 spbal; + u32 splah; + u32 splal; + u32 obah; + u32 obal; + u32 olah; + u32 olal; +}; + #ifdef CONFIG_SYS_FSL_RAID_ENGINE struct ccsr_raide { u8 res0[0x543]; @@ -2854,6 +2868,7 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000 +#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 @@ -3067,6 +3082,8 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) #define CONFIG_SYS_FSL_SRIO_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) +#define CONFIG_SYS_PAMU_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET) #define CONFIG_SYS_PCI1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 4566ec3671..b766470ce2 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -12,6 +12,9 @@ #include "jr.h" #include "jobdesc.h" #include "desc_constr.h" +#ifdef CONFIG_FSL_CORENET +#include +#endif #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) @@ -534,18 +537,38 @@ int sec_init(void) uint32_t mcr = sec_in32(&sec->mcfgr); int ret = 0; +#ifdef CONFIG_FSL_CORENET + uint32_t liodnr; + uint32_t liodn_ns; + uint32_t liodn_s; +#endif + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); #ifdef CONFIG_PHYS_64BIT mcr |= (1 << MCFGR_PS_SHIFT); #endif sec_out32(&sec->mcfgr, mcr); +#ifdef CONFIG_FSL_CORENET + liodnr = sec_in32(&sec->jrliodnr[0].ls); + liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT; + liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; +#endif + ret = jr_init(); if (ret < 0) { printf("SEC initialization failed\n"); return -1; } +#ifdef CONFIG_FSL_CORENET + ret = sec_config_pamu_table(liodn_ns, liodn_s); + if (ret < 0) + return -1; + + pamu_enable(); +#endif + if (get_rng_vid() >= 4) { if (rng_init() < 0) { printf("RNG instantiation failed\n"); -- cgit v1.2.3 From 3e0a0fbbac48e47d45e234691fddb55194052bed Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 29 Jan 2016 16:56:01 +0800 Subject: armv8/ls1043a: enable workaround for errarum A009942 DDR erratum A-009942 applies to LS1043A. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index ff3b1bee3e..a4eb096a64 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -177,6 +177,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009929 +#define CONFIG_SYS_FSL_ERRATUM_A009942 #else #error SoC not defined #endif -- cgit v1.2.3 From bbc8e053bad16366fc74943ce4c69a910c31b8b8 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 2 Feb 2016 11:28:03 +0800 Subject: armv8/ls1043a: Implement workaround for erratum A009660 Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance. Signed-off-by: Mingkai Hu Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 19 +++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + 2 files changed, 20 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 7ff01481be..213ce3a824 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -213,6 +213,24 @@ static void erratum_a009929(void) #endif } +/* + * This erratum requires setting a value to eddrtqcr1 to optimal + * the DDR performance. The eddrtqcr1 register is in SCFG space + * of LS1043A and the offset is 0x157_020c. + */ +#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \ + && defined(CONFIG_SYS_FSL_ERRATUM_A008514) +#error A009660 and A008514 can not be both enabled. +#endif + +static void erratum_a009660(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009660 + u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; + out_be32(eddrtqcr1, 0x63b20042); +#endif +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -238,6 +256,7 @@ void fsl_lsch2_early_init_f(void) /* Erratum */ erratum_a009929(); + erratum_a009660(); } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index a4eb096a64..0ef7c9dd95 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -178,6 +178,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A009663 #define CONFIG_SYS_FSL_ERRATUM_A009929 #define CONFIG_SYS_FSL_ERRATUM_A009942 +#define CONFIG_SYS_FSL_ERRATUM_A009660 #else #error SoC not defined #endif -- cgit v1.2.3 From 70097027d299e3486831396d3c02e37dc6dff66d Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 2 Feb 2016 15:16:23 +0800 Subject: arm: ls1021a: Add QSPI or IFC support in SD boot for LS1021AQDS board As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in SD boot now. For the customer's demand, QSPI needs to be supported in SD boot too. This patch adds QSPI or IFC support in SD boot according to the corresponding defconfig. For detail, ls1021aqds_sdcard_ifc_defconfig is used to support IFC in SD boot and ls1021aqds_sdcard_qspi_defconfig is used to support QSPI in SD boot. Signed-off-by: Alison Wang Reviewed-by: York Sun --- board/freescale/ls1021aqds/MAINTAINERS | 3 ++- board/freescale/ls1021aqds/ls1021aqds.c | 4 ++-- board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg | 14 -------------- board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg | 14 ++++++++++++++ board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg | 14 ++++++++++++++ configs/ls1021aqds_sdcard_defconfig | 11 ----------- configs/ls1021aqds_sdcard_ifc_defconfig | 11 +++++++++++ configs/ls1021aqds_sdcard_qspi_defconfig | 16 ++++++++++++++++ include/configs/ls1021aqds.h | 21 +++++++++++++++++---- 9 files changed, 76 insertions(+), 32 deletions(-) delete mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg delete mode 100644 configs/ls1021aqds_sdcard_defconfig create mode 100644 configs/ls1021aqds_sdcard_ifc_defconfig create mode 100644 configs/ls1021aqds_sdcard_qspi_defconfig diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS index 820d3223c2..c37ab993ee 100644 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -8,6 +8,7 @@ F: configs/ls1021aqds_ddr4_nor_defconfig F: configs/ls1021aqds_ddr4_nor_lpuart_defconfig F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig F: configs/ls1021aqds_nor_lpuart_defconfig -F: configs/ls1021aqds_sdcard_defconfig +F: configs/ls1021aqds_sdcard_ifc_defconfig +F: configs/ls1021aqds_sdcard_qspi_defconfig F: configs/ls1021aqds_qspi_defconfig F: configs/ls1021aqds_nand_defconfig diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 5f4ec9d878..b43b379f5b 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -61,7 +61,7 @@ enum { int checkboard(void) { -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) char buf[64]; #endif #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) @@ -90,7 +90,7 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg deleted file mode 100644 index 9d99bd862d..0000000000 --- a/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg +++ /dev/null @@ -1,14 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 01ee0100 - -#enable IFC, disable QSPI and DSPI -0608000a 00000000 00000000 00000000 -60000000 00407900 60040a00 21046000 -00000000 00000000 00000000 00038000 -00000000 001b7200 00000000 00000000 - -#disable IFC, enable QSPI and DSPI -#0608000a 00000000 00000000 00000000 -#60000000 00407900 60040a00 21046000 -#00000000 00000000 00000000 00038000 -#20024800 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg new file mode 100644 index 0000000000..9d99bd862d --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +0608000a 00000000 00000000 00000000 +60000000 00407900 60040a00 21046000 +00000000 00000000 00000000 00038000 +00000000 001b7200 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +#0608000a 00000000 00000000 00000000 +#60000000 00407900 60040a00 21046000 +#00000000 00000000 00000000 00038000 +#20024800 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg new file mode 100644 index 0000000000..2bd398cc53 --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +#0608000a 00000000 00000000 00000000 +#60000000 00407900 60040a00 21046000 +#00000000 00000000 00000000 00038000 +#00000000 001b7200 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +0608000a 00000000 00000000 00000000 +60000000 00407900 60040a00 21046000 +00000000 00000000 00000000 00038000 +20024800 001b7200 00000000 00000000 diff --git a/configs/ls1021aqds_sdcard_defconfig b/configs/ls1021aqds_sdcard_defconfig deleted file mode 100644 index e283f69629..0000000000 --- a/configs/ls1021aqds_sdcard_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_LS1021AQDS=y -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" -# CONFIG_CMD_SETEXPR is not set -CONFIG_OF_CONTROL=y -CONFIG_DM=y -CONFIG_NETDEVICES=y -CONFIG_E1000=y -CONFIG_SYS_NS16550=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig new file mode 100644 index 0000000000..e283f69629 --- /dev/null +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig new file mode 100644 index 0000000000..cd75af6081 --- /dev/null +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1021AQDS=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5bdc124475..39d747f55e 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -42,7 +42,7 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_QIXIS_I2C_ACCESS @@ -56,7 +56,13 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg +#endif #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT @@ -87,6 +93,9 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_QSPI_BOOT #define CONFIG_SYS_TEXT_BASE 0x40010000 +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NO_FLASH #endif @@ -162,7 +171,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -412,7 +421,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DOS_PARTITION /* SPI */ -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) /* QSPI */ #define QSPI0_AMBA_BASE 0x40000000 #define FSL_QSPI_FLASH_SIZE (1 << 24) @@ -557,6 +566,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#undef CONFIG_CMD_IMLS +#endif + #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN -- cgit v1.2.3 From 16ed85601918cff4b99ac01afa4cfa0581eb2588 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Wed, 3 Feb 2016 17:03:51 +0530 Subject: armv8: ls2080: Add mcinitcmd env variable in default env Define mcinitcmd env variable to load Management complex during u-boot boot sequence. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 4 +++- include/configs/ls2080aqds.h | 4 +++- include/configs/ls2080ardb.h | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 31c6e85b6c..51c3a17ed7 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -264,7 +264,9 @@ unsigned long long get_qixis_addr(void); "kernel_start=0x581200000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "console=ttyAMA0,38400n8\0" + "console=ttyAMA0,38400n8\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" \ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index a402c06a3b..dab38208f5 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -346,7 +346,9 @@ unsigned long get_board_ddr_clk(void); "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" + "kernel_size=0x2800000\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" #ifdef CONFIG_FSL_MC_ENET #define CONFIG_FSL_MEMAC diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 356d254159..b2c0181132 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -327,7 +327,9 @@ unsigned long get_board_sys_clk(void); "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x581100000\0" \ "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" + "kernel_size=0x2800000\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" #undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ -- cgit v1.2.3 From 9f3e1b8a55060bcb2c52e2e3a828a70c7e106219 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Wed, 3 Feb 2016 17:04:07 +0530 Subject: armv8: ls2080: Update bootcmd env variable Before Linux boot DPL must be deployed to DPAA2 interface. So update bootcmd env variable to make sure DPL deployment before Linux boot. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 51c3a17ed7..64b82e8388 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -272,8 +272,9 @@ unsigned long long get_qixis_addr(void); "earlycon=uart8250,mmio,0x21c0500" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=256" -#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ - "$kernel_size && bootm $kernel_load" +#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ + " cp.b $kernel_start $kernel_load" \ + " $kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 10 /* Monitor Command Prompt */ -- cgit v1.2.3 From 2459afb1a783e34d37c0f7aeec43c77f4de4d480 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Thu, 18 Feb 2016 13:01:59 +0800 Subject: qe: move drivers/qe/qe.h to include/fsl_qe.h As the QE firmware struct is shared with Fman, move the header file out of drivers/qe/. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/fdt.c | 2 +- board/freescale/common/arm_sleep.c | 2 +- board/freescale/common/mpc85xx_sleep.c | 2 +- board/freescale/ls1021aqds/ls1021aqds.c | 2 +- board/freescale/ls1021atwr/ls1021atwr.c | 2 +- drivers/net/fm/fm.c | 2 +- drivers/qe/fdt.c | 2 +- drivers/qe/qe.c | 2 +- drivers/qe/qe.h | 299 -------------------------------- drivers/qe/uccf.c | 2 +- drivers/qe/uccf.h | 2 +- drivers/qe/uec.c | 2 +- drivers/qe/uec.h | 2 +- drivers/qe/uec_phy.c | 2 +- include/fsl_qe.h | 299 ++++++++++++++++++++++++++++++++ 16 files changed, 313 insertions(+), 313 deletions(-) delete mode 100644 drivers/qe/qe.h create mode 100644 include/fsl_qe.h diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4ae4a6c83d..f168375b45 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -48,7 +48,7 @@ #include "../../../../drivers/block/fsl_sata.h" #ifdef CONFIG_U_QE -#include "../../../../drivers/qe/qe.h" +#include #endif DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 7270be1b28..50eef052a5 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -19,7 +19,7 @@ #ifdef CONFIG_FSL_ESDHC #include #endif -#include "../../../../drivers/qe/qe.h" /* For struct qe_firmware */ +#include /* For struct qe_firmware */ DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index a498c65f04..71ed15e6a6 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -19,7 +19,7 @@ #include "sleep.h" #ifdef CONFIG_U_QE -#include "../../../drivers/qe/qe.h" +#include #endif DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c index e9cbd515a1..498d770991 100644 --- a/board/freescale/common/mpc85xx_sleep.c +++ b/board/freescale/common/mpc85xx_sleep.c @@ -8,7 +8,7 @@ #include #include "sleep.h" #ifdef CONFIG_U_QE -#include "../../../drivers/qe/qe.h" +#include #endif DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index b43b379f5b..27d0cccadb 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -28,7 +28,7 @@ #include "../common/qixis.h" #include "ls1021aqds_qixis.h" #ifdef CONFIG_U_QE -#include "../../../drivers/qe/qe.h" +#include #endif #define PIN_MUX_SEL_CAN 0x03 diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 616e0bfd39..054a324054 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -28,7 +28,7 @@ #include #include "../common/sleep.h" #ifdef CONFIG_U_QE -#include "../../../drivers/qe/qe.h" +#include #endif #include diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 40fbf19c75..e2a8ed3919 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -10,7 +10,7 @@ #include #include "fm.h" -#include "../../qe/qe.h" /* For struct qe_firmware */ +#include /* For struct qe_firmware */ #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND #include diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c index dfae4bf64d..4f48f984ab 100644 --- a/drivers/qe/fdt.c +++ b/drivers/qe/fdt.c @@ -10,7 +10,7 @@ #include #include #include -#include "qe.h" +#include #ifdef CONFIG_QE DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 08620b23a7..8f00817c50 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -12,7 +12,7 @@ #include "asm/errno.h" #include "asm/io.h" #include "linux/immap_qe.h" -#include "qe.h" +#include #ifdef CONFIG_LS102XA #include #endif diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h deleted file mode 100644 index 77b18e928f..0000000000 --- a/drivers/qe/qe.h +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - * - * Dave Liu - * based on source code of Shlomi Gridish - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __QE_H__ -#define __QE_H__ - -#include "common.h" -#ifdef CONFIG_U_QE -#include -#endif - -#define QE_NUM_OF_BRGS 16 -#define UCC_MAX_NUM 8 - -#define QE_DATAONLY_BASE 0 -#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE) - -/* QE threads SNUM -*/ -typedef enum qe_snum_state { - QE_SNUM_STATE_USED, /* used */ - QE_SNUM_STATE_FREE /* free */ -} qe_snum_state_e; - -typedef struct qe_snum { - u8 num; /* snum */ - qe_snum_state_e state; /* state */ -} qe_snum_t; - -/* QE RISC allocation -*/ -#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ -#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ -#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ -#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ -#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ - QE_RISC_ALLOCATION_RISC2) -#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ - QE_RISC_ALLOCATION_RISC2 | \ - QE_RISC_ALLOCATION_RISC3 | \ - QE_RISC_ALLOCATION_RISC4) - -/* QE CECR commands for UCC fast. -*/ -#define QE_CR_FLG 0x00010000 -#define QE_RESET 0x80000000 -#define QE_INIT_TX_RX 0x00000000 -#define QE_INIT_RX 0x00000001 -#define QE_INIT_TX 0x00000002 -#define QE_ENTER_HUNT_MODE 0x00000003 -#define QE_STOP_TX 0x00000004 -#define QE_GRACEFUL_STOP_TX 0x00000005 -#define QE_RESTART_TX 0x00000006 -#define QE_SWITCH_COMMAND 0x00000007 -#define QE_SET_GROUP_ADDRESS 0x00000008 -#define QE_INSERT_CELL 0x00000009 -#define QE_ATM_TRANSMIT 0x0000000a -#define QE_CELL_POOL_GET 0x0000000b -#define QE_CELL_POOL_PUT 0x0000000c -#define QE_IMA_HOST_CMD 0x0000000d -#define QE_ATM_MULTI_THREAD_INIT 0x00000011 -#define QE_ASSIGN_PAGE 0x00000012 -#define QE_START_FLOW_CONTROL 0x00000014 -#define QE_STOP_FLOW_CONTROL 0x00000015 -#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 -#define QE_GRACEFUL_STOP_RX 0x0000001a -#define QE_RESTART_RX 0x0000001b - -/* QE CECR Sub Block Code - sub block code of QE command. -*/ -#define QE_CR_SUBBLOCK_INVALID 0x00000000 -#define QE_CR_SUBBLOCK_USB 0x03200000 -#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 -#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 -#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 -#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 -#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 -#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 -#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 -#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 -#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 -#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 -#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 -#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 -#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 -#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 -#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 -#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 -#define QE_CR_SUBBLOCK_MCC1 0x03800000 -#define QE_CR_SUBBLOCK_MCC2 0x03a00000 -#define QE_CR_SUBBLOCK_MCC3 0x03000000 -#define QE_CR_SUBBLOCK_IDMA1 0x02800000 -#define QE_CR_SUBBLOCK_IDMA2 0x02a00000 -#define QE_CR_SUBBLOCK_IDMA3 0x02c00000 -#define QE_CR_SUBBLOCK_IDMA4 0x02e00000 -#define QE_CR_SUBBLOCK_HPAC 0x01e00000 -#define QE_CR_SUBBLOCK_SPI1 0x01400000 -#define QE_CR_SUBBLOCK_SPI2 0x01600000 -#define QE_CR_SUBBLOCK_RAND 0x01c00000 -#define QE_CR_SUBBLOCK_TIMER 0x01e00000 -#define QE_CR_SUBBLOCK_GENERAL 0x03c00000 - -/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command. -*/ -#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ -#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 -#define QE_CR_PROTOCOL_ATM_POS 0x0A -#define QE_CR_PROTOCOL_ETHERNET 0x0C -#define QE_CR_PROTOCOL_L2_SWITCH 0x0D -#define QE_CR_PROTOCOL_SHIFT 6 - -/* QE ASSIGN PAGE command -*/ -#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17 - -/* Communication Direction. -*/ -typedef enum comm_dir { - COMM_DIR_NONE = 0, - COMM_DIR_RX = 1, - COMM_DIR_TX = 2, - COMM_DIR_RX_AND_TX = 3 -} comm_dir_e; - -/* Clocks and BRG's -*/ -typedef enum qe_clock { - QE_CLK_NONE = 0, - QE_BRG1, /* Baud Rate Generator 1 */ - QE_BRG2, /* Baud Rate Generator 2 */ - QE_BRG3, /* Baud Rate Generator 3 */ - QE_BRG4, /* Baud Rate Generator 4 */ - QE_BRG5, /* Baud Rate Generator 5 */ - QE_BRG6, /* Baud Rate Generator 6 */ - QE_BRG7, /* Baud Rate Generator 7 */ - QE_BRG8, /* Baud Rate Generator 8 */ - QE_BRG9, /* Baud Rate Generator 9 */ - QE_BRG10, /* Baud Rate Generator 10 */ - QE_BRG11, /* Baud Rate Generator 11 */ - QE_BRG12, /* Baud Rate Generator 12 */ - QE_BRG13, /* Baud Rate Generator 13 */ - QE_BRG14, /* Baud Rate Generator 14 */ - QE_BRG15, /* Baud Rate Generator 15 */ - QE_BRG16, /* Baud Rate Generator 16 */ - QE_CLK1, /* Clock 1 */ - QE_CLK2, /* Clock 2 */ - QE_CLK3, /* Clock 3 */ - QE_CLK4, /* Clock 4 */ - QE_CLK5, /* Clock 5 */ - QE_CLK6, /* Clock 6 */ - QE_CLK7, /* Clock 7 */ - QE_CLK8, /* Clock 8 */ - QE_CLK9, /* Clock 9 */ - QE_CLK10, /* Clock 10 */ - QE_CLK11, /* Clock 11 */ - QE_CLK12, /* Clock 12 */ - QE_CLK13, /* Clock 13 */ - QE_CLK14, /* Clock 14 */ - QE_CLK15, /* Clock 15 */ - QE_CLK16, /* Clock 16 */ - QE_CLK17, /* Clock 17 */ - QE_CLK18, /* Clock 18 */ - QE_CLK19, /* Clock 19 */ - QE_CLK20, /* Clock 20 */ - QE_CLK21, /* Clock 21 */ - QE_CLK22, /* Clock 22 */ - QE_CLK23, /* Clock 23 */ - QE_CLK24, /* Clock 24 */ - QE_CLK_DUMMY -} qe_clock_e; - -/* QE CMXGCR register -*/ -#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000 -#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 - -/* QE CMXUCR registers - */ -#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F - -/* QE BRG configuration register -*/ -#define QE_BRGC_ENABLE 0x00010000 -#define QE_BRGC_DIVISOR_SHIFT 1 -#define QE_BRGC_DIVISOR_MAX 0xFFF -#define QE_BRGC_DIV16 1 - -/* QE SDMA registers -*/ -#define QE_SDSR_BER1 0x02000000 -#define QE_SDSR_BER2 0x01000000 - -#define QE_SDMR_GLB_1_MSK 0x80000000 -#define QE_SDMR_ADR_SEL 0x20000000 -#define QE_SDMR_BER1_MSK 0x02000000 -#define QE_SDMR_BER2_MSK 0x01000000 -#define QE_SDMR_EB1_MSK 0x00800000 -#define QE_SDMR_ER1_MSK 0x00080000 -#define QE_SDMR_ER2_MSK 0x00040000 -#define QE_SDMR_CEN_MASK 0x0000E000 -#define QE_SDMR_SBER_1 0x00000200 -#define QE_SDMR_SBER_2 0x00000200 -#define QE_SDMR_EB1_PR_MASK 0x000000C0 -#define QE_SDMR_ER1_PR 0x00000008 - -#define QE_SDMR_CEN_SHIFT 13 -#define QE_SDMR_EB1_PR_SHIFT 6 - -#define QE_SDTM_MSNUM_SHIFT 24 - -#define QE_SDEBCR_BA_MASK 0x01FFFFFF - -/* Communication Processor */ -#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ -#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ -#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ - -/* I-RAM */ -#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ -#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ -#define QE_IRAM_READY 0x80000000 - -/* Structure that defines QE firmware binary files. - * - * See doc/README.qe_firmware for a description of these fields. - */ -struct qe_firmware { - struct qe_header { - u32 length; /* Length of the entire structure, in bytes */ - u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ - u8 version; /* Version of this layout. First ver is '1' */ - } header; - u8 id[62]; /* Null-terminated identifier string */ - u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ - u8 count; /* Number of microcode[] structures */ - struct { - u16 model; /* The SOC model */ - u8 major; /* The SOC revision major */ - u8 minor; /* The SOC revision minor */ - } __attribute__ ((packed)) soc; - u8 padding[4]; /* Reserved, for alignment */ - u64 extended_modes; /* Extended modes */ - u32 vtraps[8]; /* Virtual trap addresses */ - u8 reserved[4]; /* Reserved, for future expansion */ - struct qe_microcode { - u8 id[32]; /* Null-terminated identifier */ - u32 traps[16]; /* Trap addresses, 0 == ignore */ - u32 eccr; /* The value for the ECCR register */ - u32 iram_offset;/* Offset into I-RAM for the code */ - u32 count; /* Number of 32-bit words of the code */ - u32 code_offset;/* Offset of the actual microcode */ - u8 major; /* The microcode version major */ - u8 minor; /* The microcode version minor */ - u8 revision; /* The microcode version revision */ - u8 padding; /* Reserved, for alignment */ - u8 reserved[4]; /* Reserved, for future expansion */ - } __attribute__ ((packed)) microcode[1]; - /* All microcode binaries should be located here */ - /* CRC32 should be located here, after the microcode binaries */ -} __attribute__ ((packed)); - -struct qe_firmware_info { - char id[64]; /* Firmware name */ - u32 vtraps[8]; /* Virtual trap addresses */ - u64 extended_modes; /* Extended modes */ -}; - -void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); -void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data); -uint qe_muram_alloc(uint size, uint align); -void *qe_muram_addr(uint offset); -int qe_get_snum(void); -void qe_put_snum(u8 snum); -void qe_init(uint qe_base); -void qe_reset(void); -void qe_assign_page(uint snum, uint para_ram_base); -int qe_set_brg(uint brg, uint rate); -int qe_set_mii_clk_src(int ucc_num); -int qe_upload_firmware(const struct qe_firmware *firmware); -struct qe_firmware_info *qe_get_firmware_info(void); -void ft_qe_setup(void *blob); -void qe_init(uint qe_base); -void qe_reset(void); - -#ifdef CONFIG_U_QE -void u_qe_init(void); -int u_qe_upload_firmware(const struct qe_firmware *firmware); -void u_qe_resume(void); -int u_qe_firmware_resume(const struct qe_firmware *firmware, - qe_map_t *qe_immrr); -#endif - -#endif /* __QE_H__ */ diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c index 85386bfc70..e011886505 100644 --- a/drivers/qe/uccf.c +++ b/drivers/qe/uccf.c @@ -12,8 +12,8 @@ #include "asm/errno.h" #include "asm/io.h" #include "linux/immap_qe.h" -#include "qe.h" #include "uccf.h" +#include void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf) { diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h index 55941e4601..aa817e73ec 100644 --- a/drivers/qe/uccf.h +++ b/drivers/qe/uccf.h @@ -11,8 +11,8 @@ #define __UCCF_H__ #include "common.h" -#include "qe.h" #include "linux/immap_qe.h" +#include /* Fast or Giga ethernet */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index e0ab04abc2..40cccc2406 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -12,11 +12,11 @@ #include "asm/errno.h" #include "asm/io.h" #include "linux/immap_qe.h" -#include "qe.h" #include "uccf.h" #include "uec.h" #include "uec_phy.h" #include "miiphy.h" +#include #include /* Default UTBIPAR SMI address */ diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 6b559f7974..22e248ff1d 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -10,8 +10,8 @@ #ifndef __UEC_H__ #define __UEC_H__ -#include "qe.h" #include "uccf.h" +#include #include #define MAX_TX_THREADS 8 diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index e701787c41..272874d3b0 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -16,11 +16,11 @@ #include "asm/errno.h" #include "linux/immap_qe.h" #include "asm/io.h" -#include "qe.h" #include "uccf.h" #include "uec.h" #include "uec_phy.h" #include "miiphy.h" +#include #include #define ugphy_printk(format, arg...) \ diff --git a/include/fsl_qe.h b/include/fsl_qe.h new file mode 100644 index 0000000000..77b18e928f --- /dev/null +++ b/include/fsl_qe.h @@ -0,0 +1,299 @@ +/* + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __QE_H__ +#define __QE_H__ + +#include "common.h" +#ifdef CONFIG_U_QE +#include +#endif + +#define QE_NUM_OF_BRGS 16 +#define UCC_MAX_NUM 8 + +#define QE_DATAONLY_BASE 0 +#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE) + +/* QE threads SNUM +*/ +typedef enum qe_snum_state { + QE_SNUM_STATE_USED, /* used */ + QE_SNUM_STATE_FREE /* free */ +} qe_snum_state_e; + +typedef struct qe_snum { + u8 num; /* snum */ + qe_snum_state_e state; /* state */ +} qe_snum_t; + +/* QE RISC allocation +*/ +#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ +#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ +#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ +#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ +#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2) +#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ + QE_RISC_ALLOCATION_RISC2 | \ + QE_RISC_ALLOCATION_RISC3 | \ + QE_RISC_ALLOCATION_RISC4) + +/* QE CECR commands for UCC fast. +*/ +#define QE_CR_FLG 0x00010000 +#define QE_RESET 0x80000000 +#define QE_INIT_TX_RX 0x00000000 +#define QE_INIT_RX 0x00000001 +#define QE_INIT_TX 0x00000002 +#define QE_ENTER_HUNT_MODE 0x00000003 +#define QE_STOP_TX 0x00000004 +#define QE_GRACEFUL_STOP_TX 0x00000005 +#define QE_RESTART_TX 0x00000006 +#define QE_SWITCH_COMMAND 0x00000007 +#define QE_SET_GROUP_ADDRESS 0x00000008 +#define QE_INSERT_CELL 0x00000009 +#define QE_ATM_TRANSMIT 0x0000000a +#define QE_CELL_POOL_GET 0x0000000b +#define QE_CELL_POOL_PUT 0x0000000c +#define QE_IMA_HOST_CMD 0x0000000d +#define QE_ATM_MULTI_THREAD_INIT 0x00000011 +#define QE_ASSIGN_PAGE 0x00000012 +#define QE_START_FLOW_CONTROL 0x00000014 +#define QE_STOP_FLOW_CONTROL 0x00000015 +#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 +#define QE_GRACEFUL_STOP_RX 0x0000001a +#define QE_RESTART_RX 0x0000001b + +/* QE CECR Sub Block Code - sub block code of QE command. +*/ +#define QE_CR_SUBBLOCK_INVALID 0x00000000 +#define QE_CR_SUBBLOCK_USB 0x03200000 +#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 +#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 +#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 +#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 +#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 +#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 +#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 +#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 +#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 +#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 +#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 +#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 +#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 +#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 +#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 +#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 +#define QE_CR_SUBBLOCK_MCC1 0x03800000 +#define QE_CR_SUBBLOCK_MCC2 0x03a00000 +#define QE_CR_SUBBLOCK_MCC3 0x03000000 +#define QE_CR_SUBBLOCK_IDMA1 0x02800000 +#define QE_CR_SUBBLOCK_IDMA2 0x02a00000 +#define QE_CR_SUBBLOCK_IDMA3 0x02c00000 +#define QE_CR_SUBBLOCK_IDMA4 0x02e00000 +#define QE_CR_SUBBLOCK_HPAC 0x01e00000 +#define QE_CR_SUBBLOCK_SPI1 0x01400000 +#define QE_CR_SUBBLOCK_SPI2 0x01600000 +#define QE_CR_SUBBLOCK_RAND 0x01c00000 +#define QE_CR_SUBBLOCK_TIMER 0x01e00000 +#define QE_CR_SUBBLOCK_GENERAL 0x03c00000 + +/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command. +*/ +#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ +#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 +#define QE_CR_PROTOCOL_ATM_POS 0x0A +#define QE_CR_PROTOCOL_ETHERNET 0x0C +#define QE_CR_PROTOCOL_L2_SWITCH 0x0D +#define QE_CR_PROTOCOL_SHIFT 6 + +/* QE ASSIGN PAGE command +*/ +#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17 + +/* Communication Direction. +*/ +typedef enum comm_dir { + COMM_DIR_NONE = 0, + COMM_DIR_RX = 1, + COMM_DIR_TX = 2, + COMM_DIR_RX_AND_TX = 3 +} comm_dir_e; + +/* Clocks and BRG's +*/ +typedef enum qe_clock { + QE_CLK_NONE = 0, + QE_BRG1, /* Baud Rate Generator 1 */ + QE_BRG2, /* Baud Rate Generator 2 */ + QE_BRG3, /* Baud Rate Generator 3 */ + QE_BRG4, /* Baud Rate Generator 4 */ + QE_BRG5, /* Baud Rate Generator 5 */ + QE_BRG6, /* Baud Rate Generator 6 */ + QE_BRG7, /* Baud Rate Generator 7 */ + QE_BRG8, /* Baud Rate Generator 8 */ + QE_BRG9, /* Baud Rate Generator 9 */ + QE_BRG10, /* Baud Rate Generator 10 */ + QE_BRG11, /* Baud Rate Generator 11 */ + QE_BRG12, /* Baud Rate Generator 12 */ + QE_BRG13, /* Baud Rate Generator 13 */ + QE_BRG14, /* Baud Rate Generator 14 */ + QE_BRG15, /* Baud Rate Generator 15 */ + QE_BRG16, /* Baud Rate Generator 16 */ + QE_CLK1, /* Clock 1 */ + QE_CLK2, /* Clock 2 */ + QE_CLK3, /* Clock 3 */ + QE_CLK4, /* Clock 4 */ + QE_CLK5, /* Clock 5 */ + QE_CLK6, /* Clock 6 */ + QE_CLK7, /* Clock 7 */ + QE_CLK8, /* Clock 8 */ + QE_CLK9, /* Clock 9 */ + QE_CLK10, /* Clock 10 */ + QE_CLK11, /* Clock 11 */ + QE_CLK12, /* Clock 12 */ + QE_CLK13, /* Clock 13 */ + QE_CLK14, /* Clock 14 */ + QE_CLK15, /* Clock 15 */ + QE_CLK16, /* Clock 16 */ + QE_CLK17, /* Clock 17 */ + QE_CLK18, /* Clock 18 */ + QE_CLK19, /* Clock 19 */ + QE_CLK20, /* Clock 20 */ + QE_CLK21, /* Clock 21 */ + QE_CLK22, /* Clock 22 */ + QE_CLK23, /* Clock 23 */ + QE_CLK24, /* Clock 24 */ + QE_CLK_DUMMY +} qe_clock_e; + +/* QE CMXGCR register +*/ +#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000 +#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 + +/* QE CMXUCR registers + */ +#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F + +/* QE BRG configuration register +*/ +#define QE_BRGC_ENABLE 0x00010000 +#define QE_BRGC_DIVISOR_SHIFT 1 +#define QE_BRGC_DIVISOR_MAX 0xFFF +#define QE_BRGC_DIV16 1 + +/* QE SDMA registers +*/ +#define QE_SDSR_BER1 0x02000000 +#define QE_SDSR_BER2 0x01000000 + +#define QE_SDMR_GLB_1_MSK 0x80000000 +#define QE_SDMR_ADR_SEL 0x20000000 +#define QE_SDMR_BER1_MSK 0x02000000 +#define QE_SDMR_BER2_MSK 0x01000000 +#define QE_SDMR_EB1_MSK 0x00800000 +#define QE_SDMR_ER1_MSK 0x00080000 +#define QE_SDMR_ER2_MSK 0x00040000 +#define QE_SDMR_CEN_MASK 0x0000E000 +#define QE_SDMR_SBER_1 0x00000200 +#define QE_SDMR_SBER_2 0x00000200 +#define QE_SDMR_EB1_PR_MASK 0x000000C0 +#define QE_SDMR_ER1_PR 0x00000008 + +#define QE_SDMR_CEN_SHIFT 13 +#define QE_SDMR_EB1_PR_SHIFT 6 + +#define QE_SDTM_MSNUM_SHIFT 24 + +#define QE_SDEBCR_BA_MASK 0x01FFFFFF + +/* Communication Processor */ +#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ +#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ +#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ + +/* I-RAM */ +#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ +#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ +#define QE_IRAM_READY 0x80000000 + +/* Structure that defines QE firmware binary files. + * + * See doc/README.qe_firmware for a description of these fields. + */ +struct qe_firmware { + struct qe_header { + u32 length; /* Length of the entire structure, in bytes */ + u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ + u8 version; /* Version of this layout. First ver is '1' */ + } header; + u8 id[62]; /* Null-terminated identifier string */ + u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ + u8 count; /* Number of microcode[] structures */ + struct { + u16 model; /* The SOC model */ + u8 major; /* The SOC revision major */ + u8 minor; /* The SOC revision minor */ + } __attribute__ ((packed)) soc; + u8 padding[4]; /* Reserved, for alignment */ + u64 extended_modes; /* Extended modes */ + u32 vtraps[8]; /* Virtual trap addresses */ + u8 reserved[4]; /* Reserved, for future expansion */ + struct qe_microcode { + u8 id[32]; /* Null-terminated identifier */ + u32 traps[16]; /* Trap addresses, 0 == ignore */ + u32 eccr; /* The value for the ECCR register */ + u32 iram_offset;/* Offset into I-RAM for the code */ + u32 count; /* Number of 32-bit words of the code */ + u32 code_offset;/* Offset of the actual microcode */ + u8 major; /* The microcode version major */ + u8 minor; /* The microcode version minor */ + u8 revision; /* The microcode version revision */ + u8 padding; /* Reserved, for alignment */ + u8 reserved[4]; /* Reserved, for future expansion */ + } __attribute__ ((packed)) microcode[1]; + /* All microcode binaries should be located here */ + /* CRC32 should be located here, after the microcode binaries */ +} __attribute__ ((packed)); + +struct qe_firmware_info { + char id[64]; /* Firmware name */ + u32 vtraps[8]; /* Virtual trap addresses */ + u64 extended_modes; /* Extended modes */ +}; + +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); +void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data); +uint qe_muram_alloc(uint size, uint align); +void *qe_muram_addr(uint offset); +int qe_get_snum(void); +void qe_put_snum(u8 snum); +void qe_init(uint qe_base); +void qe_reset(void); +void qe_assign_page(uint snum, uint para_ram_base); +int qe_set_brg(uint brg, uint rate); +int qe_set_mii_clk_src(int ucc_num); +int qe_upload_firmware(const struct qe_firmware *firmware); +struct qe_firmware_info *qe_get_firmware_info(void); +void ft_qe_setup(void *blob); +void qe_init(uint qe_base); +void qe_reset(void); + +#ifdef CONFIG_U_QE +void u_qe_init(void); +int u_qe_upload_firmware(const struct qe_firmware *firmware); +void u_qe_resume(void); +int u_qe_firmware_resume(const struct qe_firmware *firmware, + qe_map_t *qe_immrr); +#endif + +#endif /* __QE_H__ */ -- cgit v1.2.3 From 075affb1ac0cc72e4d599df5f39bd40389312d6a Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Thu, 18 Feb 2016 13:02:00 +0800 Subject: fm: fdt: Move fman ucode fixup to driver code Not only powerpc/mpc85xx but also Freescale Layerscape platforms will use fdt_fixup_fman_firmware() to insert Fman ucode blob into the device tree. So move the function to Fman driver code. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/fdt.c | 125 ++-------------------------------------- drivers/net/fm/Makefile | 1 + drivers/net/fm/fdt.c | 128 +++++++++++++++++++++++++++++++++++++++++ include/fsl_fman.h | 1 + 4 files changed, 135 insertions(+), 120 deletions(-) create mode 100644 drivers/net/fm/fdt.c diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 50eef052a5..ced216c680 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -19,7 +19,9 @@ #ifdef CONFIG_FSL_ESDHC #include #endif -#include /* For struct qe_firmware */ +#ifdef CONFIG_SYS_DPAA_FMAN +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -488,125 +490,6 @@ static void ft_fixup_qe_snum(void *blob) } #endif -/** - * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree - * - * The binding for an Fman firmware node is documented in - * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains - * the actual Fman firmware binary data. The operating system is expected to - * be able to parse the binary data to determine any attributes it needs. - */ -#ifdef CONFIG_SYS_DPAA_FMAN -void fdt_fixup_fman_firmware(void *blob) -{ - int rc, fmnode, fwnode = -1; - uint32_t phandle; - struct qe_firmware *fmanfw; - const struct qe_header *hdr; - unsigned int length; - uint32_t crc; - const char *p; - - /* The first Fman we find will contain the actual firmware. */ - fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman"); - if (fmnode < 0) - /* Exit silently if there are no Fman devices */ - return; - - /* If we already have a firmware node, then also exit silently. */ - if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0) - return; - - /* If the environment variable is not set, then exit silently */ - p = getenv("fman_ucode"); - if (!p) - return; - - fmanfw = (struct qe_firmware *) simple_strtoul(p, NULL, 16); - if (!fmanfw) - return; - - hdr = &fmanfw->header; - length = be32_to_cpu(hdr->length); - - /* Verify the firmware. */ - if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || - (hdr->magic[2] != 'F')) { - printf("Data at %p is not an Fman firmware\n", fmanfw); - return; - } - - if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) { - printf("Fman firmware at %p is too large (size=%u)\n", - fmanfw, length); - return; - } - - length -= sizeof(u32); /* Subtract the size of the CRC */ - crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length)); - if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { - printf("Fman firmware at %p has invalid CRC\n", fmanfw); - return; - } - - /* Increase the size of the fdt to make room for the node. */ - rc = fdt_increase_size(blob, fmanfw->header.length); - if (rc < 0) { - printf("Unable to make room for Fman firmware: %s\n", - fdt_strerror(rc)); - return; - } - - /* Create the firmware node. */ - fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware"); - if (fwnode < 0) { - char s[64]; - fdt_get_path(blob, fmnode, s, sizeof(s)); - printf("Could not add firmware node to %s: %s\n", s, - fdt_strerror(fwnode)); - return; - } - rc = fdt_setprop_string(blob, fwnode, "compatible", "fsl,fman-firmware"); - if (rc < 0) { - char s[64]; - fdt_get_path(blob, fwnode, s, sizeof(s)); - printf("Could not add compatible property to node %s: %s\n", s, - fdt_strerror(rc)); - return; - } - phandle = fdt_create_phandle(blob, fwnode); - if (!phandle) { - char s[64]; - fdt_get_path(blob, fwnode, s, sizeof(s)); - printf("Could not add phandle property to node %s: %s\n", s, - fdt_strerror(rc)); - return; - } - rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, fmanfw->header.length); - if (rc < 0) { - char s[64]; - fdt_get_path(blob, fwnode, s, sizeof(s)); - printf("Could not add firmware property to node %s: %s\n", s, - fdt_strerror(rc)); - return; - } - - /* Find all other Fman nodes and point them to the firmware node. */ - while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, "fsl,fman")) > 0) { - rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", phandle); - if (rc < 0) { - char s[64]; - fdt_get_path(blob, fmnode, s, sizeof(s)); - printf("Could not add pointer property to node %s: %s\n", - s, fdt_strerror(rc)); - return; - } - } -} -#else -#define fdt_fixup_fman_firmware(x) -#endif - #if defined(CONFIG_PPC_P4080) static void fdt_fixup_usb(void *fdt) { @@ -752,7 +635,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) ft_fixup_qe_snum(blob); #endif +#ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); +#endif #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index a3c9f99627..493cdc6d48 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -6,6 +6,7 @@ obj-y += dtsec.o obj-y += eth.o +obj-y += fdt.o obj-y += fm.o obj-y += init.o obj-y += tgec.o diff --git a/drivers/net/fm/fdt.c b/drivers/net/fm/fdt.c new file mode 100644 index 0000000000..830d228dba --- /dev/null +++ b/drivers/net/fm/fdt.c @@ -0,0 +1,128 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include /* For struct qe_firmware */ + +#ifdef CONFIG_SYS_DPAA_FMAN +/** + * fdt_fixup_fman_firmware -- insert the Fman firmware into the device tree + * + * The binding for an Fman firmware node is documented in + * Documentation/powerpc/dts-bindings/fsl/dpaa/fman.txt. This node contains + * the actual Fman firmware binary data. The operating system is expected to + * be able to parse the binary data to determine any attributes it needs. + */ +void fdt_fixup_fman_firmware(void *blob) +{ + int rc, fmnode, fwnode = -1; + uint32_t phandle; + struct qe_firmware *fmanfw; + const struct qe_header *hdr; + unsigned int length; + uint32_t crc; + const char *p; + + /* The first Fman we find will contain the actual firmware. */ + fmnode = fdt_node_offset_by_compatible(blob, -1, "fsl,fman"); + if (fmnode < 0) + /* Exit silently if there are no Fman devices */ + return; + + /* If we already have a firmware node, then also exit silently. */ + if (fdt_node_offset_by_compatible(blob, -1, "fsl,fman-firmware") > 0) + return; + + /* If the environment variable is not set, then exit silently */ + p = getenv("fman_ucode"); + if (!p) + return; + + fmanfw = (struct qe_firmware *)simple_strtoul(p, NULL, 16); + if (!fmanfw) + return; + + hdr = &fmanfw->header; + length = be32_to_cpu(hdr->length); + + /* Verify the firmware. */ + if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || + (hdr->magic[2] != 'F')) { + printf("Data at %p is not an Fman firmware\n", fmanfw); + return; + } + + if (length > CONFIG_SYS_QE_FMAN_FW_LENGTH) { + printf("Fman firmware at %p is too large (size=%u)\n", + fmanfw, length); + return; + } + + length -= sizeof(u32); /* Subtract the size of the CRC */ + crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length)); + if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { + printf("Fman firmware at %p has invalid CRC\n", fmanfw); + return; + } + + /* Increase the size of the fdt to make room for the node. */ + rc = fdt_increase_size(blob, fmanfw->header.length); + if (rc < 0) { + printf("Unable to make room for Fman firmware: %s\n", + fdt_strerror(rc)); + return; + } + + /* Create the firmware node. */ + fwnode = fdt_add_subnode(blob, fmnode, "fman-firmware"); + if (fwnode < 0) { + char s[64]; + fdt_get_path(blob, fmnode, s, sizeof(s)); + printf("Could not add firmware node to %s: %s\n", s, + fdt_strerror(fwnode)); + return; + } + rc = fdt_setprop_string(blob, fwnode, "compatible", + "fsl,fman-firmware"); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add compatible property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + phandle = fdt_create_phandle(blob, fwnode); + if (!phandle) { + char s[64]; + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add phandle property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, + fmanfw->header.length); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add firmware property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + /* Find all other Fman nodes and point them to the firmware node. */ + while ((fmnode = fdt_node_offset_by_compatible(blob, fmnode, + "fsl,fman")) > 0) { + rc = fdt_setprop_cell(blob, fmnode, "fsl,firmware-phandle", + phandle); + if (rc < 0) { + char s[64]; + fdt_get_path(blob, fmnode, s, sizeof(s)); + printf("Could not add pointer property to node %s: %s\n", + s, fdt_strerror(rc)); + return; + } + } +} +#endif diff --git a/include/fsl_fman.h b/include/fsl_fman.h index 4d04415ba8..f3e35f8c6b 100644 --- a/include/fsl_fman.h +++ b/include/fsl_fman.h @@ -460,4 +460,5 @@ typedef struct ccsr_fman { u8 res5[4*1024]; } ccsr_fman_t; +void fdt_fixup_fman_firmware(void *blob); #endif /*__FSL_FMAN_H__*/ -- cgit v1.2.3 From 6fc9535f397bace13324546f070e40979ac03d13 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Thu, 18 Feb 2016 13:02:01 +0800 Subject: driver/fm: fdt.c: fix fdt_fixup_fman_firmware() to support ARM platforms Use fdt32_to_cpu() to convert the data correctly for both endianness platforms. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- drivers/net/fm/fdt.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/net/fm/fdt.c b/drivers/net/fm/fdt.c index 830d228dba..9918d8089a 100644 --- a/drivers/net/fm/fdt.c +++ b/drivers/net/fm/fdt.c @@ -45,7 +45,7 @@ void fdt_fixup_fman_firmware(void *blob) return; hdr = &fmanfw->header; - length = be32_to_cpu(hdr->length); + length = fdt32_to_cpu(hdr->length); /* Verify the firmware. */ if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || @@ -61,14 +61,16 @@ void fdt_fixup_fman_firmware(void *blob) } length -= sizeof(u32); /* Subtract the size of the CRC */ - crc = be32_to_cpu(*(u32 *)((void *)fmanfw + length)); + crc = fdt32_to_cpu(*(u32 *)((void *)fmanfw + length)); if (crc != crc32_no_comp(0, (void *)fmanfw, length)) { printf("Fman firmware at %p has invalid CRC\n", fmanfw); return; } + length += sizeof(u32); + /* Increase the size of the fdt to make room for the node. */ - rc = fdt_increase_size(blob, fmanfw->header.length); + rc = fdt_increase_size(blob, length); if (rc < 0) { printf("Unable to make room for Fman firmware: %s\n", fdt_strerror(rc)); @@ -101,8 +103,7 @@ void fdt_fixup_fman_firmware(void *blob) fdt_strerror(rc)); return; } - rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, - fmanfw->header.length); + rc = fdt_setprop(blob, fwnode, "fsl,firmware", fmanfw, length); if (rc < 0) { char s[64]; fdt_get_path(blob, fwnode, s, sizeof(s)); -- cgit v1.2.3 From 0e52b6fea15641d01ce130efdde251b072fcd221 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Thu, 18 Feb 2016 13:02:02 +0800 Subject: armv8/fsl-layerscape: fdt: add fixup for Fman ucode Add fdt fixup to insert Fman firmware into the device tree. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 4e4861d107..9c18fd7a16 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -14,6 +14,9 @@ #ifdef CONFIG_FSL_ESDHC #include #endif +#ifdef CONFIG_SYS_DPAA_FMAN +#include +#endif #ifdef CONFIG_MP #include #endif @@ -204,4 +207,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_LSCH3 fdt_fixup_smmu(blob); #endif + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_firmware(blob); +#endif } -- cgit v1.2.3 From 5a7c40bea618dfa50c6ae5f171782b49fd8250a6 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Tue, 16 Feb 2016 13:12:53 +0800 Subject: armv8/ls1043aqds: Add USB support for ls1043aqds Add USB XHCI support for ls1043qds board. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- board/freescale/ls1043aqds/ls1043aqds.c | 15 +++++++++++++++ include/configs/ls1043aqds.h | 13 +++++++++++++ 2 files changed, 28 insertions(+) diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 01db078222..a72fe52ea0 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -223,10 +223,25 @@ void board_retimer_init(void) int board_early_init_f(void) { +#ifdef CONFIG_HAS_FSL_XHCI_USB + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; +#endif #ifdef CONFIG_LPUART u8 uart; #endif fsl_lsch2_early_init_f(); + +#ifdef CONFIG_HAS_FSL_XHCI_USB + out_be32(&scfg->rcwpmuxcr0, 0x3333); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#endif + #ifdef CONFIG_LPUART /* We use lpuart0 as system console */ uart = QIXIS_READ(brdcfg[14]); diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 4ab8e13ba1..158cf02763 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -379,6 +379,19 @@ unsigned long get_board_ddr_clk(void); #endif #endif +/* USB */ +#define CONFIG_HAS_FSL_XHCI_USB +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_EXT2 +#endif + /* * Miscellaneous configurable options */ -- cgit v1.2.3 From 3bf46e6a6de71a31be05545d59819ca73e367ddc Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 5 Feb 2016 10:04:16 +0800 Subject: driver: qe: Mask the codes not used for micro QE there are some code in qe.c not used for micro QE, use "#ifdef CONFIG_QE" to mask them. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- drivers/qe/qe.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 8f00817c50..31e0e3b4d5 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -20,7 +20,9 @@ #define MPC85xx_DEVDISR_QE_DISABLE 0x1 qe_map_t *qe_immr = NULL; +#ifdef CONFIG_QE static qe_snum_t snums[QE_NUM_OF_SNUM]; +#endif DECLARE_GLOBAL_DATA_PTR; @@ -81,6 +83,7 @@ void *qe_muram_addr(uint offset) return (void *)&qe_immr->muram[offset]; } +#ifdef CONFIG_QE static void qe_sdma_init(void) { volatile sdma_t *p; @@ -184,6 +187,7 @@ void qe_init(uint qe_base) qe_sdma_init(); qe_snums_init(); } +#endif #ifdef CONFIG_U_QE void u_qe_init(void) @@ -214,6 +218,7 @@ void qe_reset(void) (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0); } +#ifdef CONFIG_QE void qe_assign_page(uint snum, uint para_ram_base) { u32 cecr; @@ -229,6 +234,7 @@ void qe_assign_page(uint snum, uint para_ram_base) return; } +#endif /* * brg: 0~15 as BRG1~BRG16 -- cgit v1.2.3 From d3e6d30cef41d929dcab2ce8dcb93d92319a49a2 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 5 Feb 2016 10:04:17 +0800 Subject: board: ls1043ardb: Add micro QE support for ls1043ardb Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- board/freescale/ls1043ardb/ls1043ardb.c | 8 ++++++++ drivers/qe/qe.c | 6 ++---- include/configs/ls1043ardb.h | 7 +++++++ 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index c8f723a108..2e61f3a08e 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -21,6 +21,10 @@ #include #include #include "cpld.h" +#ifdef CONFIG_U_QE +#include +#endif + DECLARE_GLOBAL_DATA_PTR; @@ -113,6 +117,10 @@ int board_init(void) enable_layerscape_ns_access(); #endif +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + return 0; } diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 31e0e3b4d5..2b98984ef2 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -192,8 +192,7 @@ void qe_init(uint qe_base) #ifdef CONFIG_U_QE void u_qe_init(void) { - uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */ - qe_immr = (qe_map_t *)qe_base; + qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET); u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); out_be32(&qe_immr->iram.iready, QE_IRAM_READY); @@ -204,9 +203,8 @@ void u_qe_init(void) void u_qe_resume(void) { qe_map_t *qe_immrr; - uint qe_base = CONFIG_SYS_IMMR + QE_IMMR_OFFSET; /* QE immr base */ - qe_immrr = (qe_map_t *)qe_base; + qe_immrr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET); u_qe_firmware_resume((const void *)CONFIG_SYS_QE_FW_ADDR, qe_immrr); out_be32(&qe_immrr->iram.iready, QE_IRAM_READY); } diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 506f50d895..bc40b06a89 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -268,6 +268,13 @@ #define CONFIG_ETHPRIME "FM1@DTSEC3" #endif +/* QE */ +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ + !defined(CONFIG_QSPI_BOOT) +#define CONFIG_U_QE +#endif +#define CONFIG_SYS_QE_FW_ADDR 0x60600000 + /* USB */ #define CONFIG_HAS_FSL_XHCI_USB #ifdef CONFIG_HAS_FSL_XHCI_USB -- cgit v1.2.3 From 110171dcef7bff6f4cbf93c309398f4523056eee Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 5 Feb 2016 10:04:18 +0800 Subject: board: ls1043rdb: Move USB muxing config to config_board_mux Pin-muxing code should be in config_board_mux, move USB muxing config to config_board_mux. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- board/freescale/ls1043ardb/ls1043ardb.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 2e61f3a08e..dafe7c91a4 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -75,23 +75,8 @@ int dram_init(void) int board_early_init_f(void) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - u32 usb_pwrfault; - fsl_lsch2_early_init_f(); -#ifdef CONFIG_HAS_FSL_XHCI_USB - out_be32(&scfg->rcwpmuxcr0, 0x3333); - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); - usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB2_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << - SCFG_USBPWRFAULT_USB1_SHIFT); - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); -#endif - return 0; } @@ -126,6 +111,21 @@ int board_init(void) int config_board_mux(void) { + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 usb_pwrfault; + +#ifdef CONFIG_HAS_FSL_XHCI_USB + out_be32(&scfg->rcwpmuxcr0, 0x3333); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); +#endif + return 0; } -- cgit v1.2.3 From a12a0ef89e2905c6e08c9a22858725cec68d1821 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 5 Feb 2016 10:04:19 +0800 Subject: board: ls1043ardb: Modify pin-muxing code for USB and QE-HDLC QE-HDLC and USB multi-use the pins, modify the pin-muxing code for them, when set "hwconfig=qe-hdlc" in uboot, assign the pins to QE-HDLC, if not, assgin it to USB Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- board/freescale/ls1043ardb/ls1043ardb.c | 53 ++++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 10 deletions(-) diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index dafe7c91a4..66d974a40b 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -114,18 +114,24 @@ int config_board_mux(void) struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault; + if (hwconfig("qe-hdlc")) { + out_be32(&scfg->rcwpmuxcr0, + (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600); + printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n", + in_be32(&scfg->rcwpmuxcr0)); + } else { #ifdef CONFIG_HAS_FSL_XHCI_USB - out_be32(&scfg->rcwpmuxcr0, 0x3333); - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); - usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_DEDICATED << - SCFG_USBPWRFAULT_USB2_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << - SCFG_USBPWRFAULT_USB1_SHIFT); - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); + out_be32(&scfg->rcwpmuxcr0, 0x3333); + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << + SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_SHARED << + SCFG_USBPWRFAULT_USB1_SHIFT); + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif - + } return 0; } @@ -152,6 +158,16 @@ int misc_init_r(void) } #endif +void fdt_del_qe(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,qe")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} + int ft_board_setup(void *blob, bd_t *bd) { u64 base[CONFIG_NR_DRAM_BANKS]; @@ -169,6 +185,23 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); #endif + + /* + * qe-hdlc and usb multi-use the pins, + * when set hwconfig to qe-hdlc, delete usb node. + */ + if (hwconfig("qe-hdlc")) +#ifdef CONFIG_HAS_FSL_XHCI_USB + fdt_del_node_and_alias(blob, "usb1"); +#endif + /* + * qe just support qe-uart and qe-hdlc, + * if qe-uart and qe-hdlc are not set in hwconfig, + * delete qe node. + */ + if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc")) + fdt_del_qe(blob); + return 0; } -- cgit v1.2.3 From a08b1921b4a477abe1ac4482fae9ec4bcb3cd27e Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Fri, 5 Feb 2016 12:48:17 +0800 Subject: armv7: ls102xa: Move smmu and stream id initialization into the common soc code The initialization for smmu and stream id is moved into the common soc code. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/soc.c | 48 +++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 2 ++ board/freescale/ls1021aqds/ls1021aqds.c | 42 +--------------------- board/freescale/ls1021atwr/ls1021atwr.c | 43 +--------------------- 4 files changed, 52 insertions(+), 83 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 79ae883b13..b1b0c710ae 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -9,6 +9,43 @@ #include #include #include +#include + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), + SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), + SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), + SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), + SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), +}; + +struct smmu_stream_id dev_stream_id[] = { + { 0x100, 0x01, "ETSEC MAC1" }, + { 0x104, 0x02, "ETSEC MAC2" }, + { 0x108, 0x03, "ETSEC MAC3" }, + { 0x10c, 0x04, "PEX1" }, + { 0x110, 0x05, "PEX2" }, + { 0x114, 0x06, "qDMA" }, + { 0x118, 0x07, "SATA" }, + { 0x11c, 0x08, "USB3" }, + { 0x120, 0x09, "QE" }, + { 0x124, 0x0a, "eSDHC" }, + { 0x128, 0x0b, "eMA" }, + { 0x14c, 0x0c, "2D-ACE" }, + { 0x150, 0x0d, "USB2" }, + { 0x18c, 0x0e, "DEBUG" }, +}; unsigned int get_soc_major_rev(void) { @@ -88,3 +125,14 @@ int arch_soc_init(void) return 0; } + +int ls102xa_smmu_stream_id_init(void) +{ + ls1021x_config_caam_stream_id(sec_liodn_tbl, + ARRAY_SIZE(sec_liodn_tbl)); + + ls102xa_config_smmu_stream_id(dev_stream_id, + ARRAY_SIZE(dev_stream_id)); + + return 0; +} diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h index f10cb91f4b..a354684bcc 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h @@ -9,4 +9,6 @@ unsigned int get_soc_major_rev(void); int arch_soc_init(void); +int ls102xa_smmu_stream_id_init(void); + #endif /* __FSL_LS102XA_SOC_H */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 27d0cccadb..dbea0bff26 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -426,42 +425,6 @@ int misc_init_r(void) return 0; } -struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), - SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), - SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), - SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), - SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), -}; - -struct smmu_stream_id dev_stream_id[] = { - { 0x100, 0x01, "ETSEC MAC1" }, - { 0x104, 0x02, "ETSEC MAC2" }, - { 0x108, 0x03, "ETSEC MAC3" }, - { 0x10c, 0x04, "PEX1" }, - { 0x110, 0x05, "PEX2" }, - { 0x114, 0x06, "qDMA" }, - { 0x118, 0x07, "SATA" }, - { 0x11c, 0x08, "USB3" }, - { 0x120, 0x09, "QE" }, - { 0x124, 0x0a, "eSDHC" }, - { 0x128, 0x0b, "eMA" }, - { 0x14c, 0x0c, "2D-ACE" }, - { 0x150, 0x0d, "USB2" }, - { 0x18c, 0x0e, "DEBUG" }, -}; - int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -481,10 +444,7 @@ int board_init(void) config_serdes_mux(); #endif - ls1021x_config_caam_stream_id(sec_liodn_tbl, - ARRAY_SIZE(sec_liodn_tbl)); - ls102xa_config_smmu_stream_id(dev_stream_id, - ARRAY_SIZE(dev_stream_id)); + ls102xa_smmu_stream_id_init(); #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 054a324054..c69c9cba42 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -448,43 +447,6 @@ void board_init_f(ulong dummy) } #endif - -struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), - SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), - SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), - SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), - SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), - SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), - SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), -}; - -struct smmu_stream_id dev_stream_id[] = { - { 0x100, 0x01, "ETSEC MAC1" }, - { 0x104, 0x02, "ETSEC MAC2" }, - { 0x108, 0x03, "ETSEC MAC3" }, - { 0x10c, 0x04, "PEX1" }, - { 0x110, 0x05, "PEX2" }, - { 0x114, 0x06, "qDMA" }, - { 0x118, 0x07, "SATA" }, - { 0x11c, 0x08, "USB3" }, - { 0x120, 0x09, "QE" }, - { 0x124, 0x0a, "eSDHC" }, - { 0x128, 0x0b, "eMA" }, - { 0x14c, 0x0c, "2D-ACE" }, - { 0x150, 0x0d, "USB2" }, - { 0x18c, 0x0e, "DEBUG" }, -}; - #ifdef CONFIG_DEEP_SLEEP /* program the regulator (MC34VR500) to support deep sleep */ void ls1twr_program_regulator(void) @@ -525,10 +487,7 @@ int board_init(void) #endif #endif - ls1021x_config_caam_stream_id(sec_liodn_tbl, - ARRAY_SIZE(sec_liodn_tbl)); - ls102xa_config_smmu_stream_id(dev_stream_id, - ARRAY_SIZE(dev_stream_id)); + ls102xa_smmu_stream_id_init(); #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); -- cgit v1.2.3