From 9b9c6516b0119a4abe71b1598b2258c591f955f5 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Mon, 16 Mar 2015 16:43:23 +0900
Subject: ARM: zynq: move SoC headers to mach-zynq/include/mach

Move arch/arm/include/asm/arch-zynq/*
  -> arch/arm/mach-zynq/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 arch/arm/include/asm/arch-zynq/clk.h        |  29 ------
 arch/arm/include/asm/arch-zynq/gpio.h       |  76 --------------
 arch/arm/include/asm/arch-zynq/hardware.h   | 149 ----------------------------
 arch/arm/include/asm/arch-zynq/sys_proto.h  |  28 ------
 arch/arm/mach-zynq/include/mach/clk.h       |  29 ++++++
 arch/arm/mach-zynq/include/mach/gpio.h      |  76 ++++++++++++++
 arch/arm/mach-zynq/include/mach/hardware.h  | 149 ++++++++++++++++++++++++++++
 arch/arm/mach-zynq/include/mach/sys_proto.h |  28 ++++++
 8 files changed, 282 insertions(+), 282 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-zynq/clk.h
 delete mode 100644 arch/arm/include/asm/arch-zynq/gpio.h
 delete mode 100644 arch/arm/include/asm/arch-zynq/hardware.h
 delete mode 100644 arch/arm/include/asm/arch-zynq/sys_proto.h
 create mode 100644 arch/arm/mach-zynq/include/mach/clk.h
 create mode 100644 arch/arm/mach-zynq/include/mach/gpio.h
 create mode 100644 arch/arm/mach-zynq/include/mach/hardware.h
 create mode 100644 arch/arm/mach-zynq/include/mach/sys_proto.h

diff --git a/arch/arm/include/asm/arch-zynq/clk.h b/arch/arm/include/asm/arch-zynq/clk.h
deleted file mode 100644
index 250c5bc07b..0000000000
--- a/arch/arm/include/asm/arch-zynq/clk.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2013 Xilinx Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ZYNQ_CLK_H_
-#define _ZYNQ_CLK_H_
-
-enum zynq_clk {
-	armpll_clk, ddrpll_clk, iopll_clk,
-	cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk,
-	ddr2x_clk, ddr3x_clk, dci_clk,
-	lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk,
-	fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk,
-	sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk,
-	usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk,
-	sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk,
-	can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk,
-	uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
-	smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};
-
-void zynq_clk_early_init(void);
-int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate);
-unsigned long zynq_clk_get_rate(enum zynq_clk clk);
-const char *zynq_clk_get_name(enum zynq_clk clk);
-unsigned long get_uart_clk(int dev_id);
-
-#endif
diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h
deleted file mode 100644
index 9e1e7da203..0000000000
--- a/arch/arm/include/asm/arch-zynq/gpio.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2013 Xilinx, Inc.
- * Copyright (c) 2015 DAVE Embedded Systems
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ZYNQ_GPIO_H
-#define _ZYNQ_GPIO_H
-
-#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000
-
-/* Maximum banks */
-#define ZYNQ_GPIO_MAX_BANK	4
-
-#define ZYNQ_GPIO_BANK0_NGPIO	32
-#define ZYNQ_GPIO_BANK1_NGPIO	22
-#define ZYNQ_GPIO_BANK2_NGPIO	32
-#define ZYNQ_GPIO_BANK3_NGPIO	32
-
-#define ZYNQ_GPIO_NR_GPIOS	(ZYNQ_GPIO_BANK0_NGPIO + \
-				 ZYNQ_GPIO_BANK1_NGPIO + \
-				 ZYNQ_GPIO_BANK2_NGPIO + \
-				 ZYNQ_GPIO_BANK3_NGPIO)
-
-#define ZYNQ_GPIO_BANK0_PIN_MIN	0
-#define ZYNQ_GPIO_BANK0_PIN_MAX	(ZYNQ_GPIO_BANK0_PIN_MIN + \
-					ZYNQ_GPIO_BANK0_NGPIO - 1)
-#define ZYNQ_GPIO_BANK1_PIN_MIN	(ZYNQ_GPIO_BANK0_PIN_MAX + 1)
-#define ZYNQ_GPIO_BANK1_PIN_MAX	(ZYNQ_GPIO_BANK1_PIN_MIN + \
-					ZYNQ_GPIO_BANK1_NGPIO - 1)
-#define ZYNQ_GPIO_BANK2_PIN_MIN	(ZYNQ_GPIO_BANK1_PIN_MAX + 1)
-#define ZYNQ_GPIO_BANK2_PIN_MAX	(ZYNQ_GPIO_BANK2_PIN_MIN + \
-					ZYNQ_GPIO_BANK2_NGPIO - 1)
-#define ZYNQ_GPIO_BANK3_PIN_MIN	(ZYNQ_GPIO_BANK2_PIN_MAX + 1)
-#define ZYNQ_GPIO_BANK3_PIN_MAX	(ZYNQ_GPIO_BANK3_PIN_MIN + \
-					ZYNQ_GPIO_BANK3_NGPIO - 1)
-
-/* Register offsets for the GPIO device */
-/* LSW Mask & Data -WO */
-#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK)	(0x000 + (8 * BANK))
-/* MSW Mask & Data -WO */
-#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK)	(0x004 + (8 * BANK))
-/* Data Register-RW */
-#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)	(0x060 + (4 * BANK))
-/* Direction mode reg-RW */
-#define ZYNQ_GPIO_DIRM_OFFSET(BANK)	(0x204 + (0x40 * BANK))
-/* Output enable reg-RW */
-#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)	(0x208 + (0x40 * BANK))
-/* Interrupt mask reg-RO */
-#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)	(0x20C + (0x40 * BANK))
-/* Interrupt enable reg-WO */
-#define ZYNQ_GPIO_INTEN_OFFSET(BANK)	(0x210 + (0x40 * BANK))
-/* Interrupt disable reg-WO */
-#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)	(0x214 + (0x40 * BANK))
-/* Interrupt status reg-RO */
-#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)	(0x218 + (0x40 * BANK))
-/* Interrupt type reg-RW */
-#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)	(0x21C + (0x40 * BANK))
-/* Interrupt polarity reg-RW */
-#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)	(0x220 + (0x40 * BANK))
-/* Interrupt on any, reg-RW */
-#define ZYNQ_GPIO_INTANY_OFFSET(BANK)	(0x224 + (0x40 * BANK))
-
-/* Disable all interrupts mask */
-#define ZYNQ_GPIO_IXR_DISABLE_ALL	0xFFFFFFFF
-
-/* Mid pin number of a bank */
-#define ZYNQ_GPIO_MID_PIN_NUM 16
-
-/* GPIO upper 16 bit mask */
-#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
-
-#define BIT(x) (1<<x)
-
-#endif /* _ZYNQ_GPIO_H */
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
deleted file mode 100644
index e2e0b7321a..0000000000
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * Copyright (c) 2013 Xilinx Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_HARDWARE_H
-#define _ASM_ARCH_HARDWARE_H
-
-#define ZYNQ_SERIAL_BASEADDR0		0xE0000000
-#define ZYNQ_SERIAL_BASEADDR1		0xE0001000
-#define ZYNQ_SYS_CTRL_BASEADDR		0xF8000000
-#define ZYNQ_DEV_CFG_APB_BASEADDR	0xF8007000
-#define ZYNQ_SCU_BASEADDR		0xF8F00000
-#define ZYNQ_SCUTIMER_BASEADDR		0xF8F00600
-#define ZYNQ_GEM_BASEADDR0		0xE000B000
-#define ZYNQ_GEM_BASEADDR1		0xE000C000
-#define ZYNQ_SDHCI_BASEADDR0		0xE0100000
-#define ZYNQ_SDHCI_BASEADDR1		0xE0101000
-#define ZYNQ_I2C_BASEADDR0		0xE0004000
-#define ZYNQ_I2C_BASEADDR1		0xE0005000
-#define ZYNQ_SPI_BASEADDR0		0xE0006000
-#define ZYNQ_SPI_BASEADDR1		0xE0007000
-#define ZYNQ_QSPI_BASEADDR		0xE000D000
-#define ZYNQ_SMC_BASEADDR		0xE000E000
-#define ZYNQ_NAND_BASEADDR		0xE1000000
-#define ZYNQ_DDRC_BASEADDR		0xF8006000
-#define ZYNQ_EFUSE_BASEADDR		0xF800D000
-#define ZYNQ_USB_BASEADDR0		0xE0002000
-#define ZYNQ_USB_BASEADDR1		0xE0003000
-
-/* Bootmode setting values */
-#define ZYNQ_BM_MASK		0x7
-#define ZYNQ_BM_QSPI		0x1
-#define ZYNQ_BM_NOR		0x2
-#define ZYNQ_BM_NAND		0x4
-#define ZYNQ_BM_SD		0x5
-#define ZYNQ_BM_JTAG		0x0
-
-/* Reflect slcr offsets */
-struct slcr_regs {
-	u32 scl; /* 0x0 */
-	u32 slcr_lock; /* 0x4 */
-	u32 slcr_unlock; /* 0x8 */
-	u32 reserved0_1[61];
-	u32 arm_pll_ctrl; /* 0x100 */
-	u32 ddr_pll_ctrl; /* 0x104 */
-	u32 io_pll_ctrl; /* 0x108 */
-	u32 reserved0_2[5];
-	u32 arm_clk_ctrl; /* 0x120 */
-	u32 ddr_clk_ctrl; /* 0x124 */
-	u32 dci_clk_ctrl; /* 0x128 */
-	u32 aper_clk_ctrl; /* 0x12c */
-	u32 reserved0_3[2];
-	u32 gem0_rclk_ctrl; /* 0x138 */
-	u32 gem1_rclk_ctrl; /* 0x13c */
-	u32 gem0_clk_ctrl; /* 0x140 */
-	u32 gem1_clk_ctrl; /* 0x144 */
-	u32 smc_clk_ctrl; /* 0x148 */
-	u32 lqspi_clk_ctrl; /* 0x14c */
-	u32 sdio_clk_ctrl; /* 0x150 */
-	u32 uart_clk_ctrl; /* 0x154 */
-	u32 spi_clk_ctrl; /* 0x158 */
-	u32 can_clk_ctrl; /* 0x15c */
-	u32 can_mioclk_ctrl; /* 0x160 */
-	u32 dbg_clk_ctrl; /* 0x164 */
-	u32 pcap_clk_ctrl; /* 0x168 */
-	u32 reserved0_4[1];
-	u32 fpga0_clk_ctrl; /* 0x170 */
-	u32 reserved0_5[3];
-	u32 fpga1_clk_ctrl; /* 0x180 */
-	u32 reserved0_6[3];
-	u32 fpga2_clk_ctrl; /* 0x190 */
-	u32 reserved0_7[3];
-	u32 fpga3_clk_ctrl; /* 0x1a0 */
-	u32 reserved0_8[8];
-	u32 clk_621_true; /* 0x1c4 */
-	u32 reserved1[14];
-	u32 pss_rst_ctrl; /* 0x200 */
-	u32 reserved2[15];
-	u32 fpga_rst_ctrl; /* 0x240 */
-	u32 reserved3[5];
-	u32 reboot_status; /* 0x258 */
-	u32 boot_mode; /* 0x25c */
-	u32 reserved4[116];
-	u32 trust_zone; /* 0x430 */ /* FIXME */
-	u32 reserved5_1[63];
-	u32 pss_idcode; /* 0x530 */
-	u32 reserved5_2[51];
-	u32 ddr_urgent; /* 0x600 */
-	u32 reserved6[6];
-	u32 ddr_urgent_sel; /* 0x61c */
-	u32 reserved7[56];
-	u32 mio_pin[54]; /* 0x700 - 0x7D4 */
-	u32 reserved8[74];
-	u32 lvl_shftr_en; /* 0x900 */
-	u32 reserved9[3];
-	u32 ocm_cfg; /* 0x910 */
-};
-
-#define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
-
-struct devcfg_regs {
-	u32 ctrl; /* 0x0 */
-	u32 lock; /* 0x4 */
-	u32 cfg; /* 0x8 */
-	u32 int_sts; /* 0xc */
-	u32 int_mask; /* 0x10 */
-	u32 status; /* 0x14 */
-	u32 dma_src_addr; /* 0x18 */
-	u32 dma_dst_addr; /* 0x1c */
-	u32 dma_src_len; /* 0x20 */
-	u32 dma_dst_len; /* 0x24 */
-	u32 rom_shadow; /* 0x28 */
-	u32 reserved1[2];
-	u32 unlock; /* 0x34 */
-	u32 reserved2[18];
-	u32 mctrl; /* 0x80 */
-	u32 reserved3;
-	u32 write_count; /* 0x88 */
-	u32 read_count; /* 0x8c */
-};
-
-#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
-
-struct scu_regs {
-	u32 reserved1[16];
-	u32 filter_start; /* 0x40 */
-	u32 filter_end; /* 0x44 */
-};
-
-#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
-
-struct ddrc_regs {
-	u32 ddrc_ctrl; /* 0x0 */
-	u32 reserved[60];
-	u32 ecc_scrub; /* 0xF4 */
-};
-#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
-
-struct efuse_reg {
-	u32 reserved1[4];
-	u32 status;
-	u32 reserved2[3];
-};
-
-#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
-
-#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
deleted file mode 100644
index 9d50e2478f..0000000000
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2013 Xilinx Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-extern void zynq_slcr_lock(void);
-extern void zynq_slcr_unlock(void);
-extern void zynq_slcr_cpu_reset(void);
-extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
-extern void zynq_slcr_devcfg_disable(void);
-extern void zynq_slcr_devcfg_enable(void);
-extern u32 zynq_slcr_get_boot_mode(void);
-extern u32 zynq_slcr_get_idcode(void);
-extern int zynq_slcr_get_mio_pin_status(const char *periph);
-extern void zynq_ddrc_init(void);
-extern unsigned int zynq_get_silicon_version(void);
-
-/* Driver extern functions */
-extern int zynq_sdhci_init(phys_addr_t regbase);
-extern int zynq_sdhci_of_init(const void *blob);
-
-extern void ps7_init(void);
-
-#endif /* _SYS_PROTO_H_ */
diff --git a/arch/arm/mach-zynq/include/mach/clk.h b/arch/arm/mach-zynq/include/mach/clk.h
new file mode 100644
index 0000000000..250c5bc07b
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/clk.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ZYNQ_CLK_H_
+#define _ZYNQ_CLK_H_
+
+enum zynq_clk {
+	armpll_clk, ddrpll_clk, iopll_clk,
+	cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk,
+	ddr2x_clk, ddr3x_clk, dci_clk,
+	lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk,
+	fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk,
+	sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk,
+	usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk,
+	sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk,
+	can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk,
+	uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
+	smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};
+
+void zynq_clk_early_init(void);
+int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate);
+unsigned long zynq_clk_get_rate(enum zynq_clk clk);
+const char *zynq_clk_get_name(enum zynq_clk clk);
+unsigned long get_uart_clk(int dev_id);
+
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/gpio.h b/arch/arm/mach-zynq/include/mach/gpio.h
new file mode 100644
index 0000000000..9e1e7da203
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/gpio.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2013 Xilinx, Inc.
+ * Copyright (c) 2015 DAVE Embedded Systems
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ZYNQ_GPIO_H
+#define _ZYNQ_GPIO_H
+
+#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000
+
+/* Maximum banks */
+#define ZYNQ_GPIO_MAX_BANK	4
+
+#define ZYNQ_GPIO_BANK0_NGPIO	32
+#define ZYNQ_GPIO_BANK1_NGPIO	22
+#define ZYNQ_GPIO_BANK2_NGPIO	32
+#define ZYNQ_GPIO_BANK3_NGPIO	32
+
+#define ZYNQ_GPIO_NR_GPIOS	(ZYNQ_GPIO_BANK0_NGPIO + \
+				 ZYNQ_GPIO_BANK1_NGPIO + \
+				 ZYNQ_GPIO_BANK2_NGPIO + \
+				 ZYNQ_GPIO_BANK3_NGPIO)
+
+#define ZYNQ_GPIO_BANK0_PIN_MIN	0
+#define ZYNQ_GPIO_BANK0_PIN_MAX	(ZYNQ_GPIO_BANK0_PIN_MIN + \
+					ZYNQ_GPIO_BANK0_NGPIO - 1)
+#define ZYNQ_GPIO_BANK1_PIN_MIN	(ZYNQ_GPIO_BANK0_PIN_MAX + 1)
+#define ZYNQ_GPIO_BANK1_PIN_MAX	(ZYNQ_GPIO_BANK1_PIN_MIN + \
+					ZYNQ_GPIO_BANK1_NGPIO - 1)
+#define ZYNQ_GPIO_BANK2_PIN_MIN	(ZYNQ_GPIO_BANK1_PIN_MAX + 1)
+#define ZYNQ_GPIO_BANK2_PIN_MAX	(ZYNQ_GPIO_BANK2_PIN_MIN + \
+					ZYNQ_GPIO_BANK2_NGPIO - 1)
+#define ZYNQ_GPIO_BANK3_PIN_MIN	(ZYNQ_GPIO_BANK2_PIN_MAX + 1)
+#define ZYNQ_GPIO_BANK3_PIN_MAX	(ZYNQ_GPIO_BANK3_PIN_MIN + \
+					ZYNQ_GPIO_BANK3_NGPIO - 1)
+
+/* Register offsets for the GPIO device */
+/* LSW Mask & Data -WO */
+#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK)	(0x000 + (8 * BANK))
+/* MSW Mask & Data -WO */
+#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK)	(0x004 + (8 * BANK))
+/* Data Register-RW */
+#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)	(0x060 + (4 * BANK))
+/* Direction mode reg-RW */
+#define ZYNQ_GPIO_DIRM_OFFSET(BANK)	(0x204 + (0x40 * BANK))
+/* Output enable reg-RW */
+#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)	(0x208 + (0x40 * BANK))
+/* Interrupt mask reg-RO */
+#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)	(0x20C + (0x40 * BANK))
+/* Interrupt enable reg-WO */
+#define ZYNQ_GPIO_INTEN_OFFSET(BANK)	(0x210 + (0x40 * BANK))
+/* Interrupt disable reg-WO */
+#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)	(0x214 + (0x40 * BANK))
+/* Interrupt status reg-RO */
+#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)	(0x218 + (0x40 * BANK))
+/* Interrupt type reg-RW */
+#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)	(0x21C + (0x40 * BANK))
+/* Interrupt polarity reg-RW */
+#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)	(0x220 + (0x40 * BANK))
+/* Interrupt on any, reg-RW */
+#define ZYNQ_GPIO_INTANY_OFFSET(BANK)	(0x224 + (0x40 * BANK))
+
+/* Disable all interrupts mask */
+#define ZYNQ_GPIO_IXR_DISABLE_ALL	0xFFFFFFFF
+
+/* Mid pin number of a bank */
+#define ZYNQ_GPIO_MID_PIN_NUM 16
+
+/* GPIO upper 16 bit mask */
+#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
+
+#define BIT(x) (1<<x)
+
+#endif /* _ZYNQ_GPIO_H */
diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h
new file mode 100644
index 0000000000..e2e0b7321a
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/hardware.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define ZYNQ_SERIAL_BASEADDR0		0xE0000000
+#define ZYNQ_SERIAL_BASEADDR1		0xE0001000
+#define ZYNQ_SYS_CTRL_BASEADDR		0xF8000000
+#define ZYNQ_DEV_CFG_APB_BASEADDR	0xF8007000
+#define ZYNQ_SCU_BASEADDR		0xF8F00000
+#define ZYNQ_SCUTIMER_BASEADDR		0xF8F00600
+#define ZYNQ_GEM_BASEADDR0		0xE000B000
+#define ZYNQ_GEM_BASEADDR1		0xE000C000
+#define ZYNQ_SDHCI_BASEADDR0		0xE0100000
+#define ZYNQ_SDHCI_BASEADDR1		0xE0101000
+#define ZYNQ_I2C_BASEADDR0		0xE0004000
+#define ZYNQ_I2C_BASEADDR1		0xE0005000
+#define ZYNQ_SPI_BASEADDR0		0xE0006000
+#define ZYNQ_SPI_BASEADDR1		0xE0007000
+#define ZYNQ_QSPI_BASEADDR		0xE000D000
+#define ZYNQ_SMC_BASEADDR		0xE000E000
+#define ZYNQ_NAND_BASEADDR		0xE1000000
+#define ZYNQ_DDRC_BASEADDR		0xF8006000
+#define ZYNQ_EFUSE_BASEADDR		0xF800D000
+#define ZYNQ_USB_BASEADDR0		0xE0002000
+#define ZYNQ_USB_BASEADDR1		0xE0003000
+
+/* Bootmode setting values */
+#define ZYNQ_BM_MASK		0x7
+#define ZYNQ_BM_QSPI		0x1
+#define ZYNQ_BM_NOR		0x2
+#define ZYNQ_BM_NAND		0x4
+#define ZYNQ_BM_SD		0x5
+#define ZYNQ_BM_JTAG		0x0
+
+/* Reflect slcr offsets */
+struct slcr_regs {
+	u32 scl; /* 0x0 */
+	u32 slcr_lock; /* 0x4 */
+	u32 slcr_unlock; /* 0x8 */
+	u32 reserved0_1[61];
+	u32 arm_pll_ctrl; /* 0x100 */
+	u32 ddr_pll_ctrl; /* 0x104 */
+	u32 io_pll_ctrl; /* 0x108 */
+	u32 reserved0_2[5];
+	u32 arm_clk_ctrl; /* 0x120 */
+	u32 ddr_clk_ctrl; /* 0x124 */
+	u32 dci_clk_ctrl; /* 0x128 */
+	u32 aper_clk_ctrl; /* 0x12c */
+	u32 reserved0_3[2];
+	u32 gem0_rclk_ctrl; /* 0x138 */
+	u32 gem1_rclk_ctrl; /* 0x13c */
+	u32 gem0_clk_ctrl; /* 0x140 */
+	u32 gem1_clk_ctrl; /* 0x144 */
+	u32 smc_clk_ctrl; /* 0x148 */
+	u32 lqspi_clk_ctrl; /* 0x14c */
+	u32 sdio_clk_ctrl; /* 0x150 */
+	u32 uart_clk_ctrl; /* 0x154 */
+	u32 spi_clk_ctrl; /* 0x158 */
+	u32 can_clk_ctrl; /* 0x15c */
+	u32 can_mioclk_ctrl; /* 0x160 */
+	u32 dbg_clk_ctrl; /* 0x164 */
+	u32 pcap_clk_ctrl; /* 0x168 */
+	u32 reserved0_4[1];
+	u32 fpga0_clk_ctrl; /* 0x170 */
+	u32 reserved0_5[3];
+	u32 fpga1_clk_ctrl; /* 0x180 */
+	u32 reserved0_6[3];
+	u32 fpga2_clk_ctrl; /* 0x190 */
+	u32 reserved0_7[3];
+	u32 fpga3_clk_ctrl; /* 0x1a0 */
+	u32 reserved0_8[8];
+	u32 clk_621_true; /* 0x1c4 */
+	u32 reserved1[14];
+	u32 pss_rst_ctrl; /* 0x200 */
+	u32 reserved2[15];
+	u32 fpga_rst_ctrl; /* 0x240 */
+	u32 reserved3[5];
+	u32 reboot_status; /* 0x258 */
+	u32 boot_mode; /* 0x25c */
+	u32 reserved4[116];
+	u32 trust_zone; /* 0x430 */ /* FIXME */
+	u32 reserved5_1[63];
+	u32 pss_idcode; /* 0x530 */
+	u32 reserved5_2[51];
+	u32 ddr_urgent; /* 0x600 */
+	u32 reserved6[6];
+	u32 ddr_urgent_sel; /* 0x61c */
+	u32 reserved7[56];
+	u32 mio_pin[54]; /* 0x700 - 0x7D4 */
+	u32 reserved8[74];
+	u32 lvl_shftr_en; /* 0x900 */
+	u32 reserved9[3];
+	u32 ocm_cfg; /* 0x910 */
+};
+
+#define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
+
+struct devcfg_regs {
+	u32 ctrl; /* 0x0 */
+	u32 lock; /* 0x4 */
+	u32 cfg; /* 0x8 */
+	u32 int_sts; /* 0xc */
+	u32 int_mask; /* 0x10 */
+	u32 status; /* 0x14 */
+	u32 dma_src_addr; /* 0x18 */
+	u32 dma_dst_addr; /* 0x1c */
+	u32 dma_src_len; /* 0x20 */
+	u32 dma_dst_len; /* 0x24 */
+	u32 rom_shadow; /* 0x28 */
+	u32 reserved1[2];
+	u32 unlock; /* 0x34 */
+	u32 reserved2[18];
+	u32 mctrl; /* 0x80 */
+	u32 reserved3;
+	u32 write_count; /* 0x88 */
+	u32 read_count; /* 0x8c */
+};
+
+#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
+
+struct scu_regs {
+	u32 reserved1[16];
+	u32 filter_start; /* 0x40 */
+	u32 filter_end; /* 0x44 */
+};
+
+#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
+
+struct ddrc_regs {
+	u32 ddrc_ctrl; /* 0x0 */
+	u32 reserved[60];
+	u32 ecc_scrub; /* 0xF4 */
+};
+#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
+
+struct efuse_reg {
+	u32 reserved1[4];
+	u32 status;
+	u32 reserved2[3];
+};
+
+#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
+
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h
new file mode 100644
index 0000000000..9d50e2478f
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/sys_proto.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+extern void zynq_slcr_lock(void);
+extern void zynq_slcr_unlock(void);
+extern void zynq_slcr_cpu_reset(void);
+extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
+extern void zynq_slcr_devcfg_disable(void);
+extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_boot_mode(void);
+extern u32 zynq_slcr_get_idcode(void);
+extern int zynq_slcr_get_mio_pin_status(const char *periph);
+extern void zynq_ddrc_init(void);
+extern unsigned int zynq_get_silicon_version(void);
+
+/* Driver extern functions */
+extern int zynq_sdhci_init(phys_addr_t regbase);
+extern int zynq_sdhci_of_init(const void *blob);
+
+extern void ps7_init(void);
+
+#endif /* _SYS_PROTO_H_ */
-- 
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