From 1051a80e9f5f28eeaf3d0cd2e6c76624d702562a Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Fri, 8 Apr 2016 01:12:14 +0200 Subject: sunxi: add initial clock setup for sun9i for SPL --- arch/arm/cpu/armv7/sunxi/clock_sun9i.c | 127 +++++++++++++++++++++++++- arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 81 +++++++++++++++- 2 files changed, 204 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c index 180634c838..78d373e573 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c @@ -1,8 +1,12 @@ + /* * sun9i specific clock code * * (C) Copyright 2015 Hans de Goede * + * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH + * Philipp Tomsich + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,6 +16,46 @@ #include #include + +#ifdef CONFIG_SPL_BUILD + +void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Set up PLL12 (peripheral 1) */ + clock_set_pll12(1200000000); + + /* Set up PLL1 (cluster 0) and PLL2 (cluster 1) */ + clock_set_pll1(408000000); + clock_set_pll2(408000000); + + /* Set up PLL4 (peripheral 0) */ + clock_set_pll4(960000000); + + /* Set up dividers for AXI0 and APB0 on cluster 0: PLL1 / 2 = 204MHz */ + writel(C0_CFG_AXI0_CLK_DIV_RATIO(2) | C0_CFG_APB0_CLK_DIV_RATIO(2), &ccm->c0_cfg); + + writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(8), &ccm->ahb0_cfg); /* AHB0: 120MHz */ + writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(4), &ccm->ahb1_cfg); /* AHB1: 240MHz */ + writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(8), &ccm->ahb2_cfg); /* AHB2: 120MHz */ + writel(APB0_SRC_PLL_PERIPH0 | APB0_CLK_DIV_RATIO(8), &ccm->apb0_cfg); /* APB0: 120MHz */ + + /* GTBUS: 400MHz (PERIPH0 div 3) */ + writel(GTBUS_SRC_PLL_PERIPH1 | GTBUS_CLK_DIV_RATIO(3), &ccm->gtbus_cfg); + /* CCI400: 480MHz (PERIPH1 div 2) */ + writel(CCI400_SRC_PLL_PERIPH0 | CCI400_CLK_DIV_RATIO(2), &ccm->cci400_cfg); + + /* Deassert DMA reset and open clock gating for DMA */ + setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24)); + setbits_le32(&ccm->apb1_gate, (1 << 24)); + + /* set enable-bit in TSTAMP_CTRL_REG */ + writel(1, 0x01720000); +} +#endif + void clock_init_uart(void) { struct sunxi_ccm_reg *const ccm = @@ -25,10 +69,89 @@ void clock_init_uart(void) setbits_le32(&ccm->apb1_reset_cfg, 1 << (APB1_RESET_UART_SHIFT + CONFIG_CONS_INDEX - 1)); +} + +#ifdef CONFIG_SPL_BUILD +void clock_set_pll1(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; + + /* Switch cluster 0 to 24MHz clock while changing PLL1 */ + clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK, C0_CPUX_CLK_SRC_OSC24M); + + writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CCM_PLL1_CLOCK_TIME_2 | + CCM_PLL1_CTRL_N(clk / 24000000), + &ccm->pll1_c0_cfg); + /* Don't bother with the stable-time registers, as it doesn't wait until the PLL is + stable. Note, that even Allwinner just uses a delay loop (or rather the AVS timer) + for this instead of the PLL_STABLE_STATUS register. */ + sdelay(2000); + + /* Switch cluster 0 back to PLL1 */ + clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK, C0_CPUX_CLK_SRC_PLL1); +} + +void clock_set_pll2(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; + + /* Switch cluster 1 to 24MHz clock while changing PLL2 */ + clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, C1_CPUX_CLK_SRC_OSC24M); + + writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) | CCM_PLL2_CLOCK_TIME_2 | + CCM_PLL2_CTRL_N(clk / 24000000), + &ccm->pll2_c1_cfg); + + sdelay(2000); + + /* Switch cluster 1 back to PLL2 */ + clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, C1_CPUX_CLK_SRC_PLL2); +} + +void clock_set_pll6(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + const int p = 0; + + writel(CCM_PLL6_CTRL_EN | CCM_PLL6_CFG_UPDATE | CCM_PLL6_CTRL_P(p) + | CCM_PLL6_CTRL_N(clk / 24000000), + &ccm->pll6_ddr_cfg); + do { } while (!(readl(&ccm->pll_stable_status) & PLL_DDR_STATUS)); + + sdelay(2000); +} + +void clock_set_pll12(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN) + return; + + writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000), + &ccm->pll12_periph1_cfg); + + sdelay(2000); +} + + +void clock_set_pll4(unsigned int clk) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000), + &ccm->pll4_periph0_cfg); - /* Dup with clock_init_safe(), drop once sun9i SPL support lands */ - writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg); + sdelay(2000); } +#endif int clock_twi_onoff(int port, int state) { diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index 1e73d7dd6a..b79eceaba2 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -105,8 +105,6 @@ struct sunxi_sysctl_reg { u32 disp_mux_cfg; /* 0x38 display MUX control */ }; -/* pll4_periph0_cfg */ -#define PLL4_CFG_DEFAULT 0x90002800 /* 960 MHz */ #define CCM_PLL4_CTRL_N_SHIFT 8 #define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT) @@ -115,6 +113,80 @@ struct sunxi_sysctl_reg { #define CCM_PLL4_CTRL_M_SHIFT 18 #define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT) +/* pllx_cfg bits */ +#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8) +#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16) +#define CCM_PLL1_CTRL_EN (1 << 31) +#define CCM_PLL1_CLOCK_TIME_2 (2 << 24) + +#define CCM_PLL2_CTRL_N(n) (((n) & 0xff) << 8) +#define CCM_PLL2_CTRL_P(n) (((n) & 0x1) << 16) +#define CCM_PLL2_CTRL_EN (1 << 31) +#define CCM_PLL2_CLOCK_TIME_2 (2 << 24) + +#define CCM_PLL4_CTRL_N(n) (((n) & 0xff) << 8) +#define CCM_PLL4_CTRL_EN (1 << 31) + +#define CCM_PLL6_CTRL_N(n) (((n) & 0xff) << 8) +#define CCM_PLL6_CTRL_P(p) (((p) & 0x1) << 16) +#define CCM_PLL6_CTRL_EN (1 << 31) +#define CCM_PLL6_CFG_UPDATE (1 << 30) + +#define CCM_PLL12_CTRL_N(n) (((n) & 0xff) << 8) +#define CCM_PLL12_CTRL_EN (1 << 31) + +#define PLL_C0CPUX_STATUS (1 << 0) +#define PLL_C1CPUX_STATUS (1 << 1) +#define PLL_DDR_STATUS (1 << 5) +#define PLL_PERIPH1_STATUS (1 << 11) + +/* cpu_clk_source bits */ +#define C0_CPUX_CLK_SRC_SHIFT 0 +#define C1_CPUX_CLK_SRC_SHIFT 8 +#define C0_CPUX_CLK_SRC_MASK (1 << C0_CPUX_CLK_SRC_SHIFT) +#define C1_CPUX_CLK_SRC_MASK (1 << C1_CPUX_CLK_SRC_SHIFT) +#define C0_CPUX_CLK_SRC_OSC24M (0 << C0_CPUX_CLK_SRC_SHIFT) +#define C0_CPUX_CLK_SRC_PLL1 (1 << C0_CPUX_CLK_SRC_SHIFT) +#define C1_CPUX_CLK_SRC_OSC24M (0 << C1_CPUX_CLK_SRC_SHIFT) +#define C1_CPUX_CLK_SRC_PLL2 (1 << C1_CPUX_CLK_SRC_SHIFT) + +/* c0_cfg */ +#define C0_CFG_AXI0_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) +#define C0_CFG_APB0_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 8) + +/* ahbx_cfg */ +#define AHBx_SRC_CLK_SELECT_SHIFT 24 +#define AHBx_SRC_MASK (0b11 << AHBx_SRC_CLK_SELECT_SHIFT) +#define AHB0_SRC_GTBUS_CLK (0b00 << AHBx_SRC_CLK_SELECT_SHIFT) +#define AHB1_SRC_GTBUS_CLK (0b00 << AHBx_SRC_CLK_SELECT_SHIFT) +#define AHB2_SRC_OSC24M (0b00 << AHBx_SRC_CLK_SELECT_SHIFT) +#define AHBx_SRC_PLL_PERIPH0 (0b01 << AHBx_SRC_CLK_SELECT_SHIFT) +#define AHBx_SRC_PLL_PERIPH1 (0b10 << AHBx_SRC_CLK_SELECT_SHIFT) +#define AHBx_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0) + +/* apb0_cfg */ +#define APB0_SRC_CLK_SELECT_SHIFT 24 +#define APB0_SRC_MASK (0b1 << APB0_SRC_CLK_SELECT_SHIFT) +#define APB0_SRC_OSC24M (0b0 << APB0_SRC_CLK_SELECT_SHIFT) +#define APB0_SRC_PLL_PERIPH0 (0b1 << APB0_SRC_CLK_SELECT_SHIFT) +#define APB0_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0) + +/* gtbus_clk_cfg */ +#define GTBUS_SRC_CLK_SELECT_SHIFT 24 +#define GTBUS_SRC_MASK (0b11 << GTBUS_SRC_CLK_SELECT_SHIFT) +#define GTBUS_SRC_OSC24M (0b00 << GTBUS_SRC_CLK_SELECT_SHIFT) +#define GTBUS_SRC_PLL_PERIPH0 (0b01 << GTBUS_SRC_CLK_SELECT_SHIFT) +#define GTBUS_SRC_PLL_PERIPH1 (0b10 << GTBUS_SRC_CLK_SELECT_SHIFT) +#define GTBUS_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) + +/* cci400_clk_cfg */ +#define CCI400_SRC_CLK_SELECT_SHIFT 24 +#define CCI400_SRC_MASK (0b11 << CCI400_SRC_CLK_SELECT_SHIFT) +#define CCI400_SRC_OSC24M (0b00 << CCI400_SRC_CLK_SELECT_SHIFT) +#define CCI400_SRC_PLL_PERIPH0 (0b01 << CCI400_SRC_CLK_SELECT_SHIFT) +#define CCI400_SRC_PLL_PERIPH1 (0b10 << CCI400_SRC_CLK_SELECT_SHIFT) +#define CCI400_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) + /* sd#_clk_cfg fields */ #define CCM_MMC_CTRL_M(x) ((x) - 1) #define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) @@ -165,6 +237,11 @@ struct sunxi_sysctl_reg { #define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) #ifndef __ASSEMBLY__ +void clock_set_pll1(unsigned int clk); +void clock_set_pll2(unsigned int clk); +void clock_set_pll4(unsigned int clk); +void clock_set_pll6(unsigned int clk); +void clock_set_pll12(unsigned int clk); unsigned int clock_get_pll4_periph0(void); #endif -- cgit v1.2.3