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2016-09-18arm: mvebu: theadorable: Add StratixV FPGA programming supportStefan Roese
This patch adds support for Altera StratixV bitstream programming. 2 FPGAs are connected to the SPI busses. This patch uses board specific write code to program the bitstream via SPI direct write mode. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18arm: mvebu: spi.h: Add registers for direct write accessStefan Roese
The direct write config register is needed for SPI direct write mode configuration. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18arm: mvebu: Add some SPI CS attributesStefan Roese
These attribute defines may be used to map an area of memory for direct access to the specific SPI devices. See SPI Direct Access Mode for further information. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18fpga: altera: Add StratixV supportStefan Roese
This patch adds support for programming of the StratixV FPGAs. Programming is done in this case (board theadorable) via SPI. The board may provide board specific code for bitstream programming. This StratixV support will be used by the theadorable board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18gpio: Add DM GPIO driver for Marvell MVEBUStefan Roese
This patch adds a DM GPIO driver for the Marvell MVEBU SoCs. There are other non-DM drivers that might be used on these platforms. But this patch creates a new DM driver. Which will be used by all Armada XP/38x boards. Other MVEBU SoC (Kirkwood / Orion) may follow once they support DM as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Phil Sutter <phil@nwl.cc> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18arm: mvebu: Fix ddr3_init() cpu configDirk Eibach
Armada 38x has a maximum of two cores. Probably copy/paste bug from Armada XP. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18ARM: sheevaplug: correct nand partition layoutPeter Korsgaard
Commit 1e3d640316 (ARM: sheevaplug: redefine MTDPARTS) changed the partition layout (without any description why), but didn't change the offset/size to load the kernel from or the root=/dev/mtdblockX in the bootargs. The 3MB forseen for a kernel is furthermore too little. A 4.4 build of mvebu_v5_defconfig is 3.6MB: -rw-r--r-- 1 peko peko 3.6M Jan 16 20:24 uImage.kirkwood-sheevaplug When device tree support for sheevaplug was added to the kernel in commit ee514b381e (ARM: Kirkwood: Add dts files for Sheevaplug and eSATA Sheevaplug) a default flash partition layout (used if mtdparts= isn't passed on the command line / CONFIG_MTD_CMDLINE_PARTS isn't enabled) with 1MB for u-boot / environment, 4MB for the kernel and the rest for the rootfs, so use that layout here and adjust the kernel loading to match. Signed-off-by: Peter Korsgaard <peter@korsgaard.com> Signed-off-by: Stefan Roese <sr@denx.de>
2016-09-18sunxi: A83T: fix 32bit overflow warningvishnupatekar
In mctl_channel_init, (0x50<<26) which overflows 32bit. It was supposed to be 0x50<<16,corrected now. Reported-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Select CONFIG_OF_BOARD_SETUP from arch/arm/KconfigHans de Goede
Always select OF_BOARD_SETUP on sunxi, rather then having it in almost all our defconfigs. This also fixes it missing from some recently added defconfigs. This commit also modifies our ft_board_setup() to not cause warnings when CONFIG_VIDEO_DT_SIMPLEFB is not set, since we will now always build it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: sinovoip-bpi-m3: drop LDO settings from defconfigvishnupatekar
Kconfig default settings are same as mentioned Sinovoip Bpi-m3 schematic. As axp818 ALDO support is enabled, it causes bpi-m3 fail to boot if ALDOs are set to 0. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Specify SATAPWR pin for Orangepi PlusHans de Goede
This enables the use of the sata connector in u-boot. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Turn satapwr on from board_initHans de Goede
There are 2 reasons for doing this: 1) The main reason for doing this is to move it outside of board/sunxi/ahci.c, so that it can be used on boards which use a usb<->sata chip too; 2) While doing this I realized that doing it from board_init also meant doing it much earlier. Some printf get_timer(0) calls show that the time between board_init() and scsi_init() is more then 600 ms, so we can drop the mdelay(500) While at it also drop the printf("SUNXI SCSI INIT\n") AHCI init is noisy enough by itself. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Fix gmac not working due to cpu_eth_init no longer being calledHans de Goede
cpu_eth_init is no longer called for dm enabled eth drivers, this was causing the sunxi gmac eth controller to no longer work in u-boot. This commit fixes this by calling the clock, reset and pinmux setup function from s_init() and enabling the phy power pin (if any) from board_init(). The enabling of phy power cannot be done from s_init because it uses dm and dm is not ready yet at this point. Note that the mdelay is dropped as the phy gets enabled much earlier now, so it is no longer needed. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Tested-by: Karsten Merker <merker@debian.org> Tested-by: Michael Haas <haas@computerlinguist.org>
2016-09-18sunxi: Fix 2nd usb controller on sun4i/sun7i no longer workingHans de Goede
The 2nd usb controller on sun4i/sun7i has its base address 0x8000 bytes from the 1st one, rather then 0x1000. Also the ahb clk gates are interleaved with the ohci clk-gates introducing a hole between the clks for usb1 and usb2. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Enable support for the eMMC found on the orangepi plusHans de Goede
This enables support for the eMMC found on the orangepi plus. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18spl: Print from which mmc slot spl is trying to bootHans de Goede
On some sunxi boards (and presumably also non sunxi boards) u-boot can be either loaded from a sdcard in a micro-sd slot, or from eMMC. Print which MMC spl tries to boot from, to help debugging. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-09-18sunxi: Add a bunch of missing compatible strings to sunxi_gpio.cHans de Goede
The kernel has different compatible strings for the pio block because the pin-muxing is different on all the different SoCs, but sunxi_gpio.c only support the basic gpio functionality, which is identical everywhere. Add the missing compatible strings for various SoC models. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Specify USB vbus pins for orangepi boardsHans de Goede
This fixes the USB ports not working on the orangepi_plus and stops us from messing with gpio-s which we should not touch on the orangepi_pc. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Add support for USB vbus pin for USB3Hans de Goede
The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Enable realtek phy supportHans de Goede
Enable building of drivers/net/phy/realtek.c so that realtek phys get properly initialized. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Enable composite video out on the CHIPAlex Kaplan
The CHIP has a composite video output in the mini-Jack connector, alongside with the 2 audio channels. Enable this output in U-Boot. Signed-off-by: Alex Kaplan <kaplan2539@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Fix DCDC2 output in CHIP_defconfigBoris Brezillon
Unlike the datasheet recommendation, the R8 SoC requires a 1.4V supply for its CPU when operating at 1Ghz. Rely on the default value specified in the Kconfig entry. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Configure only LVDS pins instead of all LCD pins when LVDS interface ↵Lawrence Yu
selected The behavior before this patch would attempt to configure the mux setting for pins 0 to 27 on PORTD to all be setting 3 for LVDS. The LVDS interface actually only uses pins 18 to 27 and not pins 0 to 27 as in the parallel LCD interface. This patch restricts the configuration to only the relevant pins 18 to 27 on PORTD. This was tested on a sun8i A33 tablet with an LVDS screen. MMC1 has the capability to use pins 2 to 7 on PORTD and the mux on those pins was being inadvertently set to setting 3 for MMC functionality which this patch corrects. Signed-off-by: Lawrence Yu <lyu@micile.com> [hdegoede@redhat.com: Only apply this change to A23 / A33] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Support SID e-fuses on A83T and H3Chen-Yu Tsai
On the A83T and H3, the SID block is at a different address. Furthurmore, the e-fuses are at an offset of 0x200 within the hardware's address space. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Add defconfig and dts for Orange Pi 2 SBCHans de Goede
The Orange Pi 2 is a SBC based on the Allwinner H3 SoC with a uSD slot, 4 USB ports connected via a USB-2 hub, a 10/100M ethernet port using the SoC's integrated PHY, Wifi via a RTL8189ETV sdio wifi chip, USB OTG, HDMI, a TRRS headphone jack for stereo out and composite out, a microphone, an IR receiver, a CSI connector, 2 LEDs, a 3 pin UART header and a 40-pin GPIO header. The added dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Add defconfig and dts for Dserve DSRV9703C tabletHans de Goede
The Dserve DSRV9703C is a 9.7" A10 tablet with a 1024x768 ips LCD, 1G RAM, 4GB flash, a Focaltech FT5406EE8 touchscreen and rtl8188ctv wifi. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Add defconfig for yones toptech bs1078-v2 tabletPeter Korsgaard
The yones toptech bs1078-v2 is a 10.1" tablet without any clear markings on the outside, but 'YONESTOPTECH-BS1078' written on the PCB silkscreen. It features a 16:9 1024:600 LCD, A31s SoC, 1GB RAM, 8G NAND, silead gsl3675 touchscreen and a RTL8723AS wifi chip: https://linux-sunxi.org/Yones_Toptech_BS1078_V2 Signed-off-by: Peter Korsgaard <peter@korsgaard.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Add defconfig for Sinlinx SinA31sChen-Yu Tsai
The Sinlinx A31s SDK is a A31s based module/baseboard development kit. The core module has the SoC, PMIC, DRAM, eMMC and supporting components. There are also pads for UART0, JTAG and I2S. The baseboard has 100 Mbps Ethernet, 5x USB 2.0 host ports via a USB 2.0 hub chip, MMC, HDMI, SPDIF, CIR, audio jacks, 2 tablet-like volume buttons, RS232 style UART and USB OTG (though VBUS is not connected). Various headers are available for other addon modules, such as SDIO WiFi, LCD display, camera sensor, UARTs, I2C, SPI and GPIOs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Add defconfig for icnova-a20-swacStefan Roese
The ICnova-A20-SWAC is a baseboard, equipped with the ICnova-A20 SoM from In-Circuit: http://wiki.in-circuit.de/index.php5?title=ICnova_A20_SODIMM http://linux-sunxi.org/In-Circuit_ICnova_A20 This patch adds support for this board, including ethernet, LCD and USB support. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sun7i: Add defconfig for the Itead IboxMarcus Cooper
Add defconfig for the multi board device based on the Allwinner A20 SoC. It contains the A20 Itead Core module and a base board for the external interfaces. The core module comes with 4GB NAND and 1GB DDR RAM. The base board to which the core board is connected provides 3 USB 2.0 Host ports, 1 USB 2.0 OTG, 1 uSD slot, 10/100 Ethernet port, HDMI, IR receiver, SPDIF and a 32-pin GPIO header. This header expands the features of core board by exposing the VGA pins, audio In/Out pins, SATA, SPI, I2C, UARTS, USB-OTG and power.. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Add defconfig for Cubietruck PlusChen-Yu Tsai
Cubietruck Plus is a A83T/H8 based development board. The board has standard DDR3 SDRAM, AXP818 PMIC/codec, SD/MMC, eMMC, USB 2.0 host via HSIC USB Hub, USB OTG, SATA via USB bridge, gigabit ethernet, WiFi, headphone out / mic in, and various GPIO headers. The board also has an EEPROM on i2c0 which holds the MAC address. DLDO3 and DLDO4 provide power to the EMAC pins and PHY. Pin PA20 is connected to the reset control of the PHY. EMAC is not actually supported yet. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18sunxi: Add defconfig and dts for the Polaroid MID2809PXE4 tabletHans de Goede
The Polaroid MID2809PXE4 is a 9" tablet which is clearly marked Polaroid MID2809PXE4 on the back. It features a 9" 16:9 800x480 LCD, A23 Soc, 1GB RAM, 8GB NAND, gsl3670 touchscreen and esp8089 wifi. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Add defconfig and dts for Difrence DIT4350 tabletHans de Goede
The Difrnce dit4350 tablet is a tiny tablet with a 4.3" 16:9 480x272 LCD, A13 SoC, 512M RAM, 4G NAND, solomon systech ssd2532qn6 touchscreen at i2c1 address 0x48, Memsic MXC622X accelerometer at i2c1 address 0x15 and rtl8188etv wifi. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Add defconfig and dts for colorfly e708 q1 tabletHans de Goede
The colorfly e708 q1 is a 7" tablet which is clearly marked as colorfly e708 q1 on the back. It features a 9:16 800x1280 IPS LCD, A31s SoC, 1GB RAM, 8G NAND, ilitek 2139qt004 touchscreen on i2c-1 addr 0x41, stk8313 accelerometer on i2c-2 addr 0x22 and a rtl8188etv wifi chip. The added dts is identical to the dts submitted to the upstream kernel, note this commit also syncs axp22x.dtsi and sun6i-a31.dtsi with the upstream kernel as the added dts depends on these. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Fix clock_twi_onoff for sun9iHans de Goede
Fix a copy and paste error which caused us to use the uart rather then the twi reset bits in clock_twi_onoff for sun9i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Fix clock_twi_onoff for sun8i-a83Hans de Goede
clock_sun8i_a83.c did not contain a clock_twi_onoff implementation at all, this is fixed by moving the clock_sun6i.c implementation, which is correct for the a83 too, to a shared location. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Fix clock_twi_onoff for sun6iHans de Goede
The clock_sun6i.c implementation was not deasserting the reset for the regular i2c controllers, this commit fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: Sync dts files with the upstream kernelHans de Goede
Sync dts files with the upstream kernel including changes queued for 4.6: https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/commit/?h=sunxi/dt-for-4.6 Note this adds a number of new unused board dts files. I've asked the authors of the kernel commits adding these to submit a matching defconfig to u-boot. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18include/dt-bindings: Sync some files with the kernelHans de Goede
This commit syncs the dt-bindings/input/* headers with the kernel (v4.5) and adds dt-bindings/clock/sun4i-a10-pll2.h, both are necessary for newer sunxi dts files to build. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-18sunxi: A23: Fix some revisions needing a different magic sram pokeHans de Goede
I've had this one a23 tablet which would not boot and I've finally figured out what the problem is by looking at the released boot0 code, it seems the magic sram controller poke which we need to do in s_init() depends on the revision of the a23. Specifically this change is needed to get the A23 SoC I have with the following serial to boot: "E6071AB 26Y7". Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-24ARM: uniphier: switch to raw U-Boot imageMasahiro Yamada
Now everything is done to load a raw U-Boot proper image instead of an mkimage-processed one (as far as I tested on NAND, eMMC, NOR). The SPL already knows the load address of the U-Boot proper without parsing its uImage header because the load address is defined by CONFIG_SYS_TEXT_BASE, assuming that the two images are generated from the same build. My main motivation of this switch is to use u-boot-with-spl.bin, a concatenation of u-boot-spl.bin and u-boot.bin. (I wish there were a concatenation of u-boot-spl.bin and u-boot.img...) Anyway, this commit would be useful for one-shot image burn. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24ARM: uniphier: add NOR boot supportMasahiro Yamada
This allows to boot from NOR flash (or SRAM) with help of an external loader (NOR-loader). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24ARM: uniphier: fix README instruction for updating U-Boot via TFTPMasahiro Yamada
Commit 3cb9abc9c512 ("ARM: uniphier: update U-Boot file names in workflow") missed to update these two sentences. Fix them now. Replace u-boot-spl-dtb.bin and u-boot-dtb.img with u-boot-spl.bin and u-boot.img, respectively. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24ARM: uniphier: support Debug UARTMasahiro Yamada
For ARM32 architecture, CONFIG_DEBUG_LL is available for early low-level debugging (and actually UniPhier 32bit SoCs use it), but ARM64 architecture does not support it. Instead, CONFIG_DEBUG_UART is available as an architecture-independent debug facility. This commit supports it on all the UniPhier SoCs (including the new ARMv8 SoCs), which is very useful for new SoC bringups. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24ARM: uniphier: add System Control register macros for ARMv8 SoCsMasahiro Yamada
The System Control block moved to a completely different register map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones. Define register macros in a new header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24ARM: uniphier: add sg_set_iectrl() functionMasahiro Yamada
This helper function would be useful for new SoCs with per-pin input enable controlling, such as PH1-LD20, PH1-LD11, etc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24ARM: dts: uniphier: add PH1-LD11 SoC/board device tree sourcesMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24ARM: dts: uniphier: add PH1-LD20 SoC/board device tree sourcesMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24ARM: uniphier: enable DDR PHY parameter dump commands by defaultMasahiro Yamada
These commands are not necessarily needed for usual operations (they are useful in case of DDR memory trouble), but enabling them by default would be nice in terms of the compilation test coverage. They are small enough, so limited impact on the memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24ARM: uniphier: add work-around to support Micro Support Card v3.6.10Masahiro Yamada
Due to some hardware guy's awful work, this version is not compatible with v3.6: the logic of BIT(0) of the reset logic is inverted! (and v3.6.10 is horribly wrong in multiple ways), but this is what we have to solve now. The v3.6 expects 0x0000 set to the register for reset de-assertion, while v3.6 does 0x0001. This commit (ab)uses another bug of v3.6.10 to work around the issue. The UniPhier System Bus is a 16-bit bus, which this support card is connected to. A 32-bit write to the bus (writel() function call) is divided into two 16-bit write transactions, with LSB the first. What is amazing for v3.6.10 is that access to address 4N + 2 goes to 4N (Jesus Christ!). For clarification, things are like this: writel(0x00010000, MICRO_SUPPORT_CARD_RESET); is done with two bus transactions as follows [1] write 0x0000 to address MICRO_SUPPORT_CARD [2] write 0x0001 to address MICRO_SUPPORT_CARD + 2 For v3.6, [1] is written to the register and [2] is correctly ignored because there is nothing at the address MICRO_SUPPORT_CARD + 2. This is what we expect. For v3.6.10, [1] is written to the reset register and then [2] is over-written to the same register due to the bus access bug. For the latter, it produces a glitch signal to the BIT[0], so the device state is lost due to the reset pulse. This solution only works for the start-up code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-23 21:00:26 +0000