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Diffstat (limited to 'arch/arm/include/asm/arch-zynq/hardware.h')
-rw-r--r--arch/arm/include/asm/arch-zynq/hardware.h36
1 files changed, 27 insertions, 9 deletions
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index d0c69da971..8b8a91ae65 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -23,16 +23,28 @@
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
-#define XPSS_SYS_CTRL_BASEADDR 0xF8000000
-#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
-#define XPSS_SCU_BASEADDR 0xF8F00000
+#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
+#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
+#define ZYNQ_SCU_BASEADDR 0xF8F00000
+#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
+#define ZYNQ_GEM_BASEADDR0 0xE000B000
+#define ZYNQ_GEM_BASEADDR1 0xE000C000
+#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
+#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
+#define ZYNQ_I2C_BASEADDR0 0xE0004000
+#define ZYNQ_I2C_BASEADDR1 0xE0005000
/* Reflect slcr offsets */
struct slcr_regs {
u32 scl; /* 0x0 */
u32 slcr_lock; /* 0x4 */
u32 slcr_unlock; /* 0x8 */
- u32 reserved1[125];
+ u32 reserved0[75];
+ u32 gem0_rclk_ctrl; /* 0x138 */
+ u32 gem1_rclk_ctrl; /* 0x13c */
+ u32 gem0_clk_ctrl; /* 0x140 */
+ u32 gem1_clk_ctrl; /* 0x144 */
+ u32 reserved1[46];
u32 pss_rst_ctrl; /* 0x200 */
u32 reserved2[15];
u32 fpga_rst_ctrl; /* 0x240 */
@@ -41,15 +53,21 @@ struct slcr_regs {
u32 boot_mode; /* 0x25c */
u32 reserved4[116];
u32 trust_zone; /* 0x430 */ /* FIXME */
- u32 reserved5[115];
+ u32 reserved5_1[63];
+ u32 pss_idcode; /* 0x530 */
+ u32 reserved5_2[51];
u32 ddr_urgent; /* 0x600 */
u32 reserved6[6];
u32 ddr_urgent_sel; /* 0x61c */
- u32 reserved7[188];
+ u32 reserved7[56];
+ u32 mio_pin[54]; /* 0x700 - 0x7D4 */
+ u32 reserved8[74];
+ u32 lvl_shftr_en; /* 0x900 */
+ u32 reserved9[3];
u32 ocm_cfg; /* 0x910 */
};
-#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
+#define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
struct devcfg_regs {
u32 ctrl; /* 0x0 */
@@ -72,7 +90,7 @@ struct devcfg_regs {
u32 read_count; /* 0x8c */
};
-#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
+#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
struct scu_regs {
u32 reserved1[16];
@@ -80,6 +98,6 @@ struct scu_regs {
u32 filter_end; /* 0x44 */
};
-#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
+#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
#endif /* _ASM_ARCH_HARDWARE_H */