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-rw-r--r--arch/arm/cpu/tegra-common/ap.c2
-rw-r--r--arch/arm/cpu/tegra-common/clock.c10
2 files changed, 7 insertions, 5 deletions
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 9b77b2b82e..e099683890 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -72,6 +72,7 @@ int tegra_get_chip_sku(void)
switch (chip_id) {
case CHIPID_TEGRA20:
switch (sku_id) {
+ case SKU_ID_T20_7:
case SKU_ID_T20:
return TEGRA_SOC_T20;
case SKU_ID_T25SE:
@@ -92,6 +93,7 @@ int tegra_get_chip_sku(void)
case CHIPID_TEGRA114:
switch (sku_id) {
case SKU_ID_T114_ENG:
+ case SKU_ID_T114_1:
return TEGRA_SOC_T114;
}
break;
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 9156d009b2..268fb912b5 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -321,17 +321,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
unsigned effective_rate;
int mux_bits, divider_bits, source;
int divider;
+ int xdiv = 0;
/* work out the source clock and set it */
source = get_periph_clock_source(periph_id, parent, &mux_bits,
&divider_bits);
+ divider = find_best_divider(divider_bits, pll_rate[parent],
+ rate, &xdiv);
if (extra_div)
- divider = find_best_divider(divider_bits, pll_rate[parent],
- rate, extra_div);
- else
- divider = clk_get_divider(divider_bits, pll_rate[parent],
- rate);
+ *extra_div = xdiv;
+
assert(divider >= 0);
if (adjust_periph_pll(periph_id, source, mux_bits, divider))
return -1U;