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-rw-r--r--.gitignore1
-rw-r--r--MAINTAINERS18
-rw-r--r--Makefile26
-rw-r--r--README5
-rw-r--r--arch/arm/config.mk3
-rw-r--r--arch/arm/cpu/arm1136/mx35/Makefile1
-rw-r--r--arch/arm/cpu/arm1136/mx35/iomux.c114
-rw-r--r--arch/arm/cpu/arm720t/start.S4
-rw-r--r--arch/arm/cpu/arm926ejs/at91/Makefile1
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c4
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c177
-rw-r--r--arch/arm/cpu/arm926ejs/at91/clock.c4
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c8
-rw-r--r--arch/arm/cpu/arm926ejs/mx25/generic.c117
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/Makefile10
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/clock.c93
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/mxs.c65
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c46
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_power_init.c50
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd4
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd4
-rw-r--r--arch/arm/cpu/armv7/am33xx/clock_ti814x.c103
-rw-r--r--arch/arm/cpu/armv7/am33xx/sys_info.c6
-rw-r--r--arch/arm/cpu/armv7/at91/Makefile52
-rw-r--r--arch/arm/cpu/armv7/at91/clock.c125
-rw-r--r--arch/arm/cpu/armv7/at91/cpu.c90
-rw-r--r--arch/arm/cpu/armv7/at91/reset.c47
-rw-r--r--arch/arm/cpu/armv7/at91/sama5d3_devices.c196
-rw-r--r--arch/arm/cpu/armv7/at91/timer.c139
-rw-r--r--arch/arm/cpu/armv7/lowlevel_init.S8
-rw-r--r--arch/arm/cpu/armv7/mx5/Makefile2
-rw-r--r--arch/arm/cpu/armv7/mx5/clock.c14
-rw-r--r--arch/arm/cpu/armv7/mx5/iomux.c186
-rw-r--r--arch/arm/cpu/armv7/mx5/soc.c7
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c52
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c11
-rw-r--r--arch/arm/cpu/armv7/omap-common/boot-common.c31
-rw-r--r--arch/arm/cpu/armv7/omap-common/clocks-common.c1
-rw-r--r--arch/arm/cpu/armv7/omap-common/emif-common.c11
-rw-r--r--arch/arm/cpu/armv7/omap-common/hwinit-common.c61
-rw-r--r--arch/arm/cpu/armv7/omap-common/lowlevel_init.S50
-rw-r--r--arch/arm/cpu/armv7/omap-common/reset.c4
-rw-r--r--arch/arm/cpu/armv7/omap4/emif.c4
-rw-r--r--arch/arm/cpu/armv7/omap4/hw_data.c2
-rw-r--r--arch/arm/cpu/armv7/omap4/hwinit.c3
-rw-r--r--arch/arm/cpu/armv7/omap5/emif.c4
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c5
-rw-r--r--arch/arm/cpu/armv7/omap5/hwinit.c22
-rw-r--r--arch/arm/cpu/armv7/omap5/prcm-regs.c2
-rw-r--r--arch/arm/cpu/armv7/zynq/slcr.c61
-rw-r--r--arch/arm/cpu/armv7/zynq/timer.c49
-rw-r--r--arch/arm/cpu/ixp/config.mk4
-rw-r--r--arch/arm/cpu/pxa/pxa2xx.c2
-rw-r--r--arch/arm/cpu/tegra-common/ap.c2
-rw-r--r--arch/arm/cpu/tegra-common/clock.c10
-rw-r--r--arch/arm/imx-common/Makefile22
-rw-r--r--arch/arm/imx-common/iomux-v3.c18
-rw-r--r--arch/arm/imx-common/misc.c84
-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h17
-rw-r--r--arch/arm/include/asm/arch-am33xx/hardware_ti814x.h1
-rw-r--r--arch/arm/include/asm/arch-am33xx/omap.h25
-rw-r--r--arch/arm/include/asm/arch-at91/at91_common.h1
-rw-r--r--arch/arm/include/asm/arch-at91/at91_dbu.h4
-rw-r--r--arch/arm/include/asm/arch-at91/at91_pmc.h23
-rw-r--r--arch/arm/include/asm/arch-at91/at91sam9_matrix.h2
-rw-r--r--arch/arm/include/asm/arch-at91/at91sam9x5.h19
-rw-r--r--arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h17
-rw-r--r--arch/arm/include/asm/arch-at91/clk.h1
-rw-r--r--arch/arm/include/asm/arch-at91/hardware.h4
-rw-r--r--arch/arm/include/asm/arch-at91/sama5d3.h212
-rw-r--r--arch/arm/include/asm/arch-at91/sama5d3_smc.h79
-rw-r--r--arch/arm/include/asm/arch-davinci/hardware.h2
-rw-r--r--arch/arm/include/asm/arch-davinci/nand_defs.h9
-rw-r--r--arch/arm/include/asm/arch-mx25/imx-regs.h21
-rw-r--r--arch/arm/include/asm/arch-mx25/imx25-pinmux.h421
-rw-r--r--arch/arm/include/asm/arch-mx25/iomux-mx25.h545
-rw-r--r--arch/arm/include/asm/arch-mx27/imx-regs.h3
-rw-r--r--arch/arm/include/asm/arch-mx31/imx-regs.h22
-rw-r--r--arch/arm/include/asm/arch-mx35/imx-regs.h19
-rw-r--r--arch/arm/include/asm/arch-mx35/iomux-mx35.h1276
-rw-r--r--arch/arm/include/asm/arch-mx35/iomux.h295
-rw-r--r--arch/arm/include/asm/arch-mx35/mx35_pins.h353
-rw-r--r--arch/arm/include/asm/arch-mx5/clock.h1
-rw-r--r--arch/arm/include/asm/arch-mx5/imx-regs.h24
-rw-r--r--arch/arm/include/asm/arch-mx5/iomux-mx51.h180
-rw-r--r--arch/arm/include/asm/arch-mx5/iomux-mx53.h1232
-rw-r--r--arch/arm/include/asm/arch-mx5/iomux.h91
-rw-r--r--arch/arm/include/asm/arch-mx5/mx5x_pins.h879
-rw-r--r--arch/arm/include/asm/arch-mx5/spl.h19
-rw-r--r--arch/arm/include/asm/arch-mx6/clock.h1
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h183
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h96
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6-pins.h4
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6dl_pins.h35
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6q_pins.h27
-rw-r--r--arch/arm/include/asm/arch-mx6/mx6sl_pins.h25
-rw-r--r--arch/arm/include/asm/arch-mx6/sys_proto.h10
-rw-r--r--arch/arm/include/asm/arch-mxs/clock.h1
-rw-r--r--arch/arm/include/asm/arch-mxs/imx-regs.h6
-rw-r--r--arch/arm/include/asm/arch-mxs/iomux.h4
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-digctl.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-i2c.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-lcdif.h38
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-lradc.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-ocotp.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-pinctrl.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-power-mx23.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-power-mx28.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-rtc.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-ssp.h2
-rw-r--r--arch/arm/include/asm/arch-mxs/regs-timrot.h2
-rw-r--r--arch/arm/include/asm/arch-omap4/omap.h36
-rw-r--r--arch/arm/include/asm/arch-omap4/sys_proto.h12
-rw-r--r--arch/arm/include/asm/arch-omap5/clocks.h10
-rw-r--r--arch/arm/include/asm/arch-omap5/cpu.h2
-rw-r--r--arch/arm/include/asm/arch-omap5/i2c.h2
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h36
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h22
-rw-r--r--arch/arm/include/asm/arch-pxa/hardware.h11
-rw-r--r--arch/arm/include/asm/arch-tegra/tegra.h2
-rw-r--r--arch/arm/include/asm/arch-zynq/hardware.h36
-rw-r--r--arch/arm/include/asm/arch-zynq/sys_proto.h7
-rw-r--r--arch/arm/include/asm/global_data.h8
-rw-r--r--arch/arm/include/asm/imx-common/dma.h (renamed from arch/arm/include/asm/arch-mxs/dma.h)12
-rw-r--r--arch/arm/include/asm/imx-common/imximage.cfg30
-rw-r--r--arch/arm/include/asm/imx-common/iomux-v3.h69
-rw-r--r--arch/arm/include/asm/imx-common/regs-apbh.h (renamed from arch/arm/include/asm/arch-mxs/regs-apbh.h)19
-rw-r--r--arch/arm/include/asm/imx-common/regs-bch.h (renamed from arch/arm/include/asm/arch-mxs/regs-bch.h)12
-rw-r--r--arch/arm/include/asm/imx-common/regs-common.h (renamed from arch/arm/include/asm/arch-mxs/regs-common.h)0
-rw-r--r--arch/arm/include/asm/imx-common/regs-gpmi.h (renamed from arch/arm/include/asm/arch-mxs/regs-gpmi.h)2
-rw-r--r--arch/arm/include/asm/omap_boot.h50
-rw-r--r--arch/arm/include/asm/omap_common.h20
-rw-r--r--arch/powerpc/cpu/mpc512x/Makefile1
-rw-r--r--arch/powerpc/cpu/mpc512x/cpu_init.c2
-rw-r--r--arch/powerpc/cpu/mpc512x/iim.c394
-rw-r--r--arch/powerpc/include/asm/immap_512x.h2
-rw-r--r--board/CarMediaLab/flea3/flea3.c91
-rw-r--r--board/Seagate/goflexhome/Makefile51
-rw-r--r--board/Seagate/goflexhome/goflexhome.c189
-rw-r--r--board/Seagate/goflexhome/kwbimage.cfg168
-rw-r--r--board/armltd/vexpress/Makefile2
-rw-r--r--board/armltd/vexpress/vexpress_common.c (renamed from board/armltd/vexpress/ca9x4_ct_vxp.c)35
-rw-r--r--board/atmel/at91sam9260ek/at91sam9260ek.c22
-rw-r--r--board/atmel/at91sam9n12ek/Makefile52
-rw-r--r--board/atmel/at91sam9n12ek/at91sam9n12ek.c228
-rw-r--r--board/atmel/sama5d3xek/Makefile51
-rw-r--r--board/atmel/sama5d3xek/sama5d3xek.c275
-rw-r--r--board/boundary/nitrogen6x/clocks.cfg11
-rw-r--r--board/boundary/nitrogen6x/nitrogen6x.c42
-rw-r--r--board/compulab/cm_t35/Makefile (renamed from board/cm_t35/Makefile)12
-rw-r--r--board/compulab/cm_t35/cm_t35.c (renamed from board/cm_t35/cm_t35.c)26
-rw-r--r--board/compulab/cm_t35/display.c (renamed from board/cm_t35/display.c)2
-rw-r--r--board/compulab/cm_t35/eeprom.c (renamed from board/cm_t35/eeprom.c)0
-rw-r--r--board/compulab/cm_t35/eeprom.h (renamed from board/cm_t35/eeprom.h)0
-rw-r--r--board/compulab/cm_t35/leds.c (renamed from board/cm_t35/leds.c)3
-rw-r--r--board/denx/m53evk/Makefile40
-rw-r--r--board/denx/m53evk/imximage.cfg108
-rw-r--r--board/denx/m53evk/m53evk.c328
-rw-r--r--board/esg/ima3-mx53/ima3-mx53.c228
-rw-r--r--board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg11
-rw-r--r--board/freescale/mx23evk/spl_boot.c4
-rw-r--r--board/freescale/mx25pdk/mx25pdk.c132
-rw-r--r--board/freescale/mx35pdk/mx35pdk.c175
-rw-r--r--board/freescale/mx51evk/mx51evk.c348
-rw-r--r--board/freescale/mx51evk/mx51evk_video.c22
-rw-r--r--board/freescale/mx53ard/mx53ard.c329
-rw-r--r--board/freescale/mx53evk/mx53evk.c289
-rw-r--r--board/freescale/mx53loco/mx53loco.c268
-rw-r--r--board/freescale/mx53loco/mx53loco_video.c68
-rw-r--r--board/freescale/mx53smd/mx53smd.c152
-rw-r--r--board/freescale/mx6qarm2/mx6qarm2.c17
-rw-r--r--board/freescale/mx6qsabreauto/mx6qsabreauto.c22
-rw-r--r--board/freescale/mx6qsabrelite/mx6qsabrelite.c30
-rw-r--r--board/freescale/mx6qsabresd/mx6qsabresd.c30
-rw-r--r--board/freescale/mx6slevk/Makefile28
-rw-r--r--board/freescale/mx6slevk/imximage.cfg118
-rw-r--r--board/freescale/mx6slevk/mx6slevk.c102
-rw-r--r--board/freescale/titanium/Makefile36
-rw-r--r--board/freescale/titanium/imximage.cfg178
-rw-r--r--board/freescale/titanium/titanium.c334
-rw-r--r--board/genesi/mx51_efikamx/efikamx-usb.c122
-rw-r--r--board/genesi/mx51_efikamx/efikamx.c2
-rw-r--r--board/h2200/h2200.c9
-rw-r--r--board/isee/igep0033/Makefile46
-rw-r--r--board/isee/igep0033/board.c232
-rw-r--r--board/isee/igep0033/board.h27
-rw-r--r--board/isee/igep0033/mux.c89
-rw-r--r--board/karo/tx25/tx25.c107
-rw-r--r--board/nokia/rx51/rx51.c52
-rw-r--r--board/nvidia/beaver/Makefile38
-rw-r--r--board/olimex/mx23_olinuxino/spl_boot.c4
-rw-r--r--board/pandora/pandora.c3
-rw-r--r--board/syteco/zmx25/zmx25.c143
-rw-r--r--board/ti/beagle/beagle.c5
-rw-r--r--board/ti/dra7xx/evm.c2
-rw-r--r--board/ti/omap5_uevm/evm.c6
-rw-r--r--board/ti/panda/panda.c6
-rw-r--r--board/ti/ti814x/evm.c75
-rw-r--r--board/ti/ti814x/evm.h1
-rw-r--r--board/ti/ti814x/mux.c35
-rw-r--r--board/ttcontrol/vision2/vision2.c585
-rw-r--r--board/wandboard/wandboard.c113
-rw-r--r--board/woodburn/woodburn.c69
-rw-r--r--board/xilinx/zynq/board.c66
-rw-r--r--boards.cfg20
-rw-r--r--common/Makefile1
-rw-r--r--common/cmd_fpga.c250
-rw-r--r--common/cmd_fuse.c168
-rw-r--r--common/spl/spl.c10
-rw-r--r--doc/README.at9184
-rw-r--r--doc/README.fsl_iim48
-rw-r--r--doc/README.fuse67
-rw-r--r--doc/README.imx2510
-rw-r--r--doc/README.imx2710
-rw-r--r--doc/README.imx56
-rw-r--r--doc/README.imx610
-rw-r--r--doc/README.imximage18
-rw-r--r--doc/README.mxc_ocotp50
-rw-r--r--doc/README.omap-reset-time20
-rw-r--r--drivers/dma/apbh_dma.c5
-rw-r--r--drivers/fpga/Makefile1
-rw-r--r--drivers/fpga/fpga.c225
-rw-r--r--drivers/fpga/xilinx.c146
-rw-r--r--drivers/fpga/zynqpl.c355
-rw-r--r--drivers/i2c/Makefile1
-rw-r--r--drivers/i2c/zynq_i2c.c306
-rw-r--r--drivers/misc/Makefile2
-rw-r--r--drivers/misc/fsl_iim.c286
-rw-r--r--drivers/misc/mxc_ocotp.c216
-rw-r--r--drivers/misc/twl4030_led.c4
-rw-r--r--drivers/mmc/Makefile1
-rw-r--r--drivers/mmc/gen_atmel_mci.c47
-rw-r--r--drivers/mmc/mxsmmc.c2
-rw-r--r--drivers/mmc/omap_hsmmc.c8
-rw-r--r--drivers/mmc/zynq_sdhci.c40
-rw-r--r--drivers/mtd/nand/Makefile2
-rw-r--r--drivers/mtd/nand/docg4.c1028
-rw-r--r--drivers/mtd/nand/docg4_spl.c222
-rw-r--r--drivers/mtd/nand/mxc_nand_spl.c13
-rw-r--r--drivers/mtd/nand/mxs_nand.c15
-rw-r--r--drivers/net/cpsw.c6
-rw-r--r--drivers/net/phy/Makefile1
-rw-r--r--drivers/net/phy/et1011c.c110
-rw-r--r--drivers/net/phy/marvell.c11
-rw-r--r--drivers/net/phy/phy.c3
-rw-r--r--drivers/net/zynq_gem.c199
-rw-r--r--drivers/power/Makefile2
-rw-r--r--drivers/power/palmas.c (renamed from drivers/power/twl6035.c)34
-rw-r--r--drivers/power/twl4030.c16
-rw-r--r--drivers/power/twl6030.c75
-rw-r--r--drivers/spi/atmel_spi.c15
-rw-r--r--drivers/spi/atmel_spi.h2
-rw-r--r--drivers/spi/mxs_spi.c2
-rw-r--r--drivers/usb/gadget/pxa27x_udc.c4
-rw-r--r--drivers/usb/host/ehci-mx5.c73
-rw-r--r--drivers/usb/host/ohci-at91.c14
-rw-r--r--drivers/usb/phy/twl4030.c48
-rw-r--r--drivers/video/Makefile1
-rw-r--r--drivers/video/cfb_console.c4
-rw-r--r--drivers/video/mxsfb.c189
-rw-r--r--drivers/video/pxa_lcd.c34
-rw-r--r--include/altera.h17
-rw-r--r--include/atmel_mci.h2
-rw-r--r--include/config_cmd_all.h1
-rw-r--r--include/configs/M54455EVB.h2
-rw-r--r--include/configs/MERGERBOX.h2
-rw-r--r--include/configs/MVBC_P.h2
-rw-r--r--include/configs/MVBLM7.h2
-rw-r--r--include/configs/MVSMR.h2
-rw-r--r--include/configs/ac14xx.h5
-rw-r--r--include/configs/am335x_evm.h14
-rw-r--r--include/configs/aria.h2
-rw-r--r--include/configs/at91sam9260ek.h52
-rw-r--r--include/configs/at91sam9n12ek.h232
-rw-r--r--include/configs/cm_t35.h18
-rw-r--r--include/configs/da830evm.h4
-rw-r--r--include/configs/da850evm.h4
-rw-r--r--include/configs/enbw_cmc.h4
-rw-r--r--include/configs/goflexhome.h151
-rw-r--r--include/configs/igep0033.h288
-rw-r--r--include/configs/ima3-mx53.h3
-rw-r--r--include/configs/m28evk.h19
-rw-r--r--include/configs/m53evk.h256
-rw-r--r--include/configs/mecp5123.h2
-rw-r--r--include/configs/mpc5121ads.h2
-rw-r--r--include/configs/mx28evk.h1
-rw-r--r--include/configs/mx51evk.h51
-rw-r--r--include/configs/mx53ard.h102
-rw-r--r--include/configs/mx53evk.h1
-rw-r--r--include/configs/mx53smd.h1
-rw-r--r--include/configs/mx6_common.h1
-rw-r--r--include/configs/mx6qsabre_common.h14
-rw-r--r--include/configs/mx6qsabrelite.h5
-rw-r--r--include/configs/mx6slevk.h189
-rw-r--r--include/configs/nitrogen6x.h5
-rw-r--r--include/configs/omap3_mvblx.h2
-rw-r--r--include/configs/omap4_common.h8
-rw-r--r--include/configs/omap4_panda.h2
-rw-r--r--include/configs/omap5_common.h5
-rw-r--r--include/configs/omap5_uevm.h3
-rw-r--r--include/configs/pcm051.h8
-rw-r--r--include/configs/pdm360ng.h7
-rw-r--r--include/configs/sama5d3xek.h245
-rw-r--r--include/configs/tegra-common-post.h2
-rw-r--r--include/configs/tegra114-common.h2
-rw-r--r--include/configs/tegra20-common.h2
-rw-r--r--include/configs/tegra30-common.h2
-rw-r--r--include/configs/ti814x_evm.h25
-rw-r--r--include/configs/titanium.h277
-rw-r--r--include/configs/tnetv107x_evm.h4
-rw-r--r--include/configs/vexpress_ca15_tc2.h36
-rw-r--r--include/configs/vexpress_ca5x2.h34
-rw-r--r--include/configs/vexpress_ca9x4.h (renamed from arch/arm/include/asm/arch-mx25/sys_proto.h)22
-rw-r--r--include/configs/vexpress_common.h (renamed from include/configs/ca9x4_ct_vxp.h)157
-rw-r--r--include/configs/wandboard.h24
-rw-r--r--include/configs/zynq.h39
-rw-r--r--include/fpga.h13
-rw-r--r--include/fuse.h44
-rw-r--r--include/lattice.h3
-rw-r--r--include/linux/bitrev.h23
-rw-r--r--include/linux/mtd/docg4.h134
-rw-r--r--include/netdev.h2
-rw-r--r--include/palmas.h (renamed from include/twl6035.h)28
-rw-r--r--include/phy.h1
-rw-r--r--include/spl.h1
-rw-r--r--include/twl4030.h4
-rw-r--r--include/twl6030.h16
-rw-r--r--include/usb/ehci-fsl.h6
-rw-r--r--include/xilinx.h25
-rw-r--r--include/zynqpl.h59
-rw-r--r--lib/Makefile1
-rw-r--r--lib/bitrev.c59
-rw-r--r--spl/Makefile8
-rw-r--r--tools/imximage.c17
-rw-r--r--tools/imximage.h9
-rw-r--r--tools/mxsboot.c8
338 files changed, 16826 insertions, 6324 deletions
diff --git a/.gitignore b/.gitignore
index 41164483ef..771b860ee8 100644
--- a/.gitignore
+++ b/.gitignore
@@ -46,6 +46,7 @@
/u-boot.ais
/u-boot.dtb
/u-boot.sb
+/u-boot.bd
/u-boot.geany
#
diff --git a/MAINTAINERS b/MAINTAINERS
index 2f066300ec..14075afae4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -607,6 +607,7 @@ Enric Balletbo i Serra <eballetbo@iseebcn.com>
igep0020 ARM ARMV7 (OMAP3xx SoC)
igep0030 ARM ARMV7 (OMAP3xx SoC)
igep0032 ARM ARMV7 (OMAP3xx SoC)
+ igep0033 ARM ARMV7 (AM33xx Soc)
Eric Benard <eric@eukrea.com>
@@ -664,6 +665,7 @@ Fabio Estevam <fabio.estevam@freescale.com>
mx6qsabresd i.MX6Q
mx6qsabreauto i.MX6Q
wandboard i.MX6DL/S
+ mx6slevk i.MX6SL
Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
@@ -683,7 +685,7 @@ Simon Guinot <simon.guinot@sequanux.org>
Igor Grinberg <grinberg@compulab.co.il>
- cm-t35 ARM ARMV7 (OMAP3xx Soc)
+ cm_t35 ARM ARMV7 (OMAP3xx Soc)
Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
@@ -848,6 +850,10 @@ Sricharan R <r.sricharan@ti.com>
omap4_sdp4430 ARM ARMV7 (OMAP4xx SoC)
omap5_evm ARM ARMV7 (OMAP5xx Soc)
+Suriyan Ramasami <suriyan.r@gmail.com>
+
+ goflexhome ARM926EJS (Kirkwood SoC)
+
Thierry Reding <thierry.reding@avionic-design.de>
plutux Tegra20 (ARM7 & A9 Dual Core)
@@ -877,6 +883,8 @@ Stefan Roese <sr@denx.de>
x600 ARM926EJS (spear600 Soc)
+ titanium i.MX6Q
+
pdnb3 xscale/ixp
scpu xscale/ixp
@@ -914,6 +922,7 @@ Matt Sealey <matt@genesi-usa.com>
Bo Shen <voice.shen@atmel.com>
at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
+ sama5d3xek ARMV7 (SAMA5D31, D33, D34, D35 SoC)
Rajeshwari Shinde <rajeshwari.s@samsung.com>
@@ -954,6 +963,7 @@ Marek Vasut <marek.vasut@gmail.com>
mx23_olinuxino i.MX23
m28evk i.MX28
sc_sps_1 i.MX28
+ m53evk i.MX53
Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
@@ -961,7 +971,8 @@ Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
Matt Waddel <matt.waddel@linaro.org>
- ca9x4_ct_vxp ARM ARMV7 (Quad Core)
+ vexpress_ca9x4 ARM ARMV7 (Quad Core)
+ vexpress_ca5x2 ARM ARMV7 (Dual Core)
Otavio Salvador <otavio@ossystems.com.br>
@@ -1018,6 +1029,9 @@ Richard Woodruff <r-woodruff2@ti.com>
omap2420h4 ARM1136EJS
+Josh Wu <josh.wu@atmel.com>
+ at91sam9n12ek ARM926EJS (AT91SAM9N12 SoC)
+
Ilya Yanok <yanok@emcraft.com>
mcx ARM ARMV7 (AM35x SoC)
diff --git a/Makefile b/Makefile
index dbc4b709b6..ef154aa57c 100644
--- a/Makefile
+++ b/Makefile
@@ -341,7 +341,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(C
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs))
LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
endif
@@ -522,13 +522,9 @@ $(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \
$(obj)u-boot.ais
-# Specify the target for use in elftosb call
-ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
-ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
- elftosb -zf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
- -o $(obj)u-boot.sb
+ $(MAKE) -C $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb
# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
# Both images are created using mkimage (crc etc), so that the ROM
@@ -547,18 +543,15 @@ $(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
ifneq ($(CONFIG_TEGRA),)
-ifeq ($(CONFIG_OF_SEPARATE),y)
-nodtb=dtb
-dtbfile=$(obj)u-boot.dtb
-else
-nodtb=nodtb
-dtbfile=
-endif
-
-$(obj)u-boot-$(nodtb)-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(dtbfile)
+$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
- cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(dtbfile) > $@
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
rm $(obj)spl/u-boot-spl-pad.bin
+
+ifeq ($(CONFIG_OF_SEPARATE),y)
+$(obj)u-boot-dtb-tegra.bin: $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb
+ cat $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb > $@
+endif
endif
$(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
@@ -871,6 +864,7 @@ clobber: tidy
@rm -f $(obj)u-boot.ais
@rm -f $(obj)u-boot.dtb
@rm -f $(obj)u-boot.sb
+ @rm -f $(obj)u-boot.bd
@rm -f $(obj)u-boot.spr
@rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
diff --git a/README b/README
index 3012dcdc16..b1b3e1788e 100644
--- a/README
+++ b/README
@@ -843,6 +843,7 @@ The following options need to be configured:
CONFIG_CMD_FDOS * Dos diskette Support
CONFIG_CMD_FLASH flinfo, erase, protect
CONFIG_CMD_FPGA FPGA device initialization support
+ CONFIG_CMD_FUSE Device fuse support
CONFIG_CMD_GETTIME * Get time since boot
CONFIG_CMD_GO * the 'go' command (exec code)
CONFIG_CMD_GREPENV * search environment
@@ -3345,6 +3346,10 @@ Configuration Settings:
offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
directly. You should not need to touch this setting.
+- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
+ This is set by OMAP boards for the max time that reset should
+ be asserted. See doc/README.omap-reset-time for details on how
+ the value can be calulated on a given board.
The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 461899eabc..dc64160789 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -31,6 +31,9 @@ CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
endif
endif
+LDFLAGS_FINAL += --gc-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+
# Support generic board on ARM
__HAVE_ARCH_GENERIC_BOARD := y
diff --git a/arch/arm/cpu/arm1136/mx35/Makefile b/arch/arm/cpu/arm1136/mx35/Makefile
index f4ababbe5b..23adac088d 100644
--- a/arch/arm/cpu/arm1136/mx35/Makefile
+++ b/arch/arm/cpu/arm1136/mx35/Makefile
@@ -29,7 +29,6 @@ LIB = $(obj)lib$(SOC).o
COBJS += generic.o
COBJS += timer.o
-COBJS += iomux.o
COBJS += mx35_sdram.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/arm1136/mx35/iomux.c b/arch/arm/cpu/arm1136/mx35/iomux.c
deleted file mode 100644
index a302575eda..0000000000
--- a/arch/arm/cpu/arm1136/mx35/iomux.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
-
-/*
- * IOMUX register (base) addresses
- */
-enum iomux_reg_addr {
- IOMUXGPR = IOMUXC_BASE_ADDR, /* General purpose */
- IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR + 4, /* MUX control */
- IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + 0x324, /* last MUX control */
- IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + 0x328, /* Pad control */
- IOMUXSW_PAD_END = IOMUXC_BASE_ADDR + 0x794, /* last Pad control */
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + 0x7AC, /* input select */
- IOMUXSW_INPUT_END = IOMUXC_BASE_ADDR + 0x9F4, /* last input select */
-};
-
-#define MUX_PIN_NUM_MAX \
- (((IOMUXSW_PAD_END - IOMUXSW_PAD_CTL) >> 2) + 1)
-#define MUX_INPUT_NUM_MUX \
- (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used.
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
- if (mux_reg != NON_MUX_I) {
- mux_reg += IOMUXGPR;
- writel(cfg, mux_reg);
- }
-}
-
-/*
- * Release ownership for an IO pin
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in iomux_pin_name_t
- * @param config the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
- u32 pad_reg = IOMUXGPR + PIN_TO_IOMUX_PAD(pin);
-
- writel(config, pad_reg);
-}
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param gp one signal as defined in iomux_gp_func_t
- * @param en enable/disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en)
-{
- u32 l;
-
- l = readl(IOMUXGPR);
- if (en)
- l |= gp;
- else
- l &= ~gp;
-
- writel(l, IOMUXGPR);
-}
-
-/*
- * This function configures input path.
- *
- * @param input index of input select register as defined in
- * iomux_input_select_t
- * @param config the binary value of elements defined in
- * iomux_input_config_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
- u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
- writel(config, reg);
-}
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 9facc7e694..f425a55a3b 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -244,9 +244,9 @@ c_runtime_cpu_setup:
*************************************************************************
*/
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
-#if !defined(CONFIG_TEGRA)
mov ip, lr
/*
* before relocating, we have to setup RAM timing
@@ -255,9 +255,9 @@ cpu_init_crit:
*/
bl lowlevel_init
mov lr, ip
-#endif
mov pc, lr
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile
index 346e58faee..c4408f6c9d 100644
--- a/arch/arm/cpu/arm926ejs/at91/Makefile
+++ b/arch/arm/cpu/arm926ejs/at91/Makefile
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o
COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o
COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
+COBJS-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o
COBJS-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
COBJS-$(CONFIG_AT91_EFLASH) += eflash.o
COBJS-$(CONFIG_AT91_LED) += led.o
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
index 19ec615c72..5e995e1d07 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
@@ -203,6 +203,10 @@ void at91_macb_hw_init(void)
#if defined(CONFIG_GENERIC_ATMEL_MCI)
void at91_mci_hw_init(void)
{
+ /* Enable mci clock */
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ writel(1 << ATMEL_ID_MCI, &pmc->pcer);
+
at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */
#if defined(CONFIG_ATMEL_MCI_PORTB)
at91_set_b_periph(AT91_PIO_PORTA, 1, 1); /* MCCDB */
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
new file mode 100644
index 0000000000..6eaeac0fc2
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2013 Atmel Corporation
+ * Josh Wu <josh.wu@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+
+unsigned int has_lcdc()
+{
+ return 1;
+}
+
+void at91_serial0_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
+ writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
+ writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
+ writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+void at91_serial3_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
+ at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
+ writel(1 << ATMEL_ID_USART3, &pmc->pcer);
+}
+
+void at91_seriald_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
+ at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
+ writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+#ifdef CONFIG_ATMEL_SPI
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+
+ if (cs_mask & (1 << 0))
+ at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
+ if (cs_mask & (1 << 1))
+ at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
+ if (cs_mask & (1 << 2))
+ at91_set_pio_output(AT91_PIO_PORTA, 1, 1);
+ if (cs_mask & (1 << 3))
+ at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
+ at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
+ at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
+
+ /* Enable clock */
+ writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+
+ if (cs_mask & (1 << 0))
+ at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
+ if (cs_mask & (1 << 1))
+ at91_set_pio_output(AT91_PIO_PORTA, 0, 1);
+ if (cs_mask & (1 << 2))
+ at91_set_pio_output(AT91_PIO_PORTA, 31, 1);
+ if (cs_mask & (1 << 3))
+ at91_set_pio_output(AT91_PIO_PORTA, 30, 1);
+}
+#endif
+
+void at91_mci_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
+ at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
+ at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
+
+ writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
+}
+
+#ifdef CONFIG_LCD
+void at91_lcd_hw_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
+ at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
+ at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */
+
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
+ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
+ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
+ at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
+ at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
+
+ writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
index f825388ae9..5b4923f3bf 100644
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -156,7 +156,7 @@ int at91_clock_init(unsigned long main_clock)
*/
mckr = readl(&pmc->mckr);
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
- || defined(CONFIG_AT91SAM9X5)
+ || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
/* plla divisor by 2 */
gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
@@ -171,7 +171,7 @@ int at91_clock_init(unsigned long main_clock)
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
- || defined(CONFIG_AT91SAM9X5)
+ || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
/* mdiv <==> divisor
* 0 <==> 1
* 1 <==> 2
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index ff2e2e33df..127beb86bc 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -32,6 +32,14 @@
#include <asm/arch/emif_defs.h>
#include <asm/arch/pll_defs.h>
+void davinci_enable_uart0(void)
+{
+ lpsc_on(DAVINCI_LPSC_UART0);
+
+ /* Bringup UART0 out of reset */
+ REG(UART0_PWREMU_MGMT) = 0x00006001;
+}
+
#if defined(CONFIG_SYS_DA850_PLL_INIT)
void da850_waitloop(unsigned long loopcnt)
{
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
index 679273b2b4..7cbbe65784 100644
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -27,7 +27,6 @@
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/imx25-pinmux.h>
#include <asm/arch/clock.h>
#ifdef CONFIG_FSL_ESDHC
@@ -248,123 +247,7 @@ int cpu_mmc_init(bd_t *bis)
}
#endif
-#ifdef CONFIG_MXC_UART
-void mx25_uart1_init_pins(void)
-{
- struct iomuxc_mux_ctl *muxctl;
- struct iomuxc_pad_ctl *padctl;
- u32 inpadctl;
- u32 outpadctl;
- u32 muxmode0;
-
- muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
- padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
- muxmode0 = MX25_PIN_MUX_MODE(0);
- /*
- * set up input pins with hysteresis and 100K pull-ups
- */
- inpadctl = MX25_PIN_PAD_CTL_HYS
- | MX25_PIN_PAD_CTL_PKE
- | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
-
- /*
- * set up output pins with 100K pull-downs
- * FIXME: need to revisit this
- * PUE is ignored if PKE is not set
- * so the right value here is likely
- * 0x0 for no pull up/down
- * or
- * 0xc0 for 100k pull down
- */
- outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
- /* UART1 */
- /* rxd */
- writel(muxmode0, &muxctl->pad_uart1_rxd);
- writel(inpadctl, &padctl->pad_uart1_rxd);
-
- /* txd */
- writel(muxmode0, &muxctl->pad_uart1_txd);
- writel(outpadctl, &padctl->pad_uart1_txd);
-
- /* rts */
- writel(muxmode0, &muxctl->pad_uart1_rts);
- writel(outpadctl, &padctl->pad_uart1_rts);
-
- /* cts */
- writel(muxmode0, &muxctl->pad_uart1_cts);
- writel(inpadctl, &padctl->pad_uart1_cts);
-}
-#endif /* CONFIG_MXC_UART */
-
#ifdef CONFIG_FEC_MXC
-void mx25_fec_init_pins(void)
-{
- struct iomuxc_mux_ctl *muxctl;
- struct iomuxc_pad_ctl *padctl;
- u32 inpadctl_100kpd;
- u32 inpadctl_22kpu;
- u32 outpadctl;
- u32 muxmode0;
-
- muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
- padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
- muxmode0 = MX25_PIN_MUX_MODE(0);
- inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
- | MX25_PIN_PAD_CTL_PKE
- | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
- inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
- | MX25_PIN_PAD_CTL_PKE
- | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
- /*
- * set up output pins with 100K pull-downs
- * FIXME: need to revisit this
- * PUE is ignored if PKE is not set
- * so the right value here is likely
- * 0x0 for no pull
- * or
- * 0xc0 for 100k pull down
- */
- outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
-
- /* FEC_TX_CLK */
- writel(muxmode0, &muxctl->pad_fec_tx_clk);
- writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk);
-
- /* FEC_RX_DV */
- writel(muxmode0, &muxctl->pad_fec_rx_dv);
- writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv);
-
- /* FEC_RDATA0 */
- writel(muxmode0, &muxctl->pad_fec_rdata0);
- writel(inpadctl_100kpd, &padctl->pad_fec_rdata0);
-
- /* FEC_TDATA0 */
- writel(muxmode0, &muxctl->pad_fec_tdata0);
- writel(outpadctl, &padctl->pad_fec_tdata0);
-
- /* FEC_TX_EN */
- writel(muxmode0, &muxctl->pad_fec_tx_en);
- writel(outpadctl, &padctl->pad_fec_tx_en);
-
- /* FEC_MDC */
- writel(muxmode0, &muxctl->pad_fec_mdc);
- writel(outpadctl, &padctl->pad_fec_mdc);
-
- /* FEC_MDIO */
- writel(muxmode0, &muxctl->pad_fec_mdio);
- writel(inpadctl_22kpu, &padctl->pad_fec_mdio);
-
- /* FEC_RDATA1 */
- writel(muxmode0, &muxctl->pad_fec_rdata1);
- writel(inpadctl_100kpd, &padctl->pad_fec_rdata1);
-
- /* FEC_TDATA1 */
- writel(muxmode0, &muxctl->pad_fec_tdata1);
- writel(outpadctl, &padctl->pad_fec_tdata1);
-
-}
-
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
int i;
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile
index eeecf89f8b..038c1c1d82 100644
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -40,6 +40,16 @@ all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+# Specify the target for use in elftosb call
+ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
+ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
+
+$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd
+ sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@
+
+$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd
+ elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb
+
#########################################################################
# defines $(obj).depend target
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 43e766334c..f94107fc15 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -325,6 +325,99 @@ void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
bus, tgtclk, freq);
}
+void mxs_set_lcdclk(uint32_t freq)
+{
+ struct mxs_clkctrl_regs *clkctrl_regs =
+ (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ uint32_t fp, x, k_rest, k_best, x_best, tk;
+ int32_t k_best_l = 999, k_best_t = 0, x_best_l = 0xff, x_best_t = 0xff;
+
+ if (freq == 0)
+ return;
+
+#if defined(CONFIG_MX23)
+ writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);
+#elif defined(CONFIG_MX28)
+ writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);
+#endif
+
+ /*
+ * / 18 \ 1 1
+ * freq kHz = | 480000000 Hz * -- | * --- * ------
+ * \ x / k 1000
+ *
+ * 480000000 Hz 18
+ * ------------ * --
+ * freq kHz x
+ * k = -------------------
+ * 1000
+ */
+
+ fp = ((PLL_FREQ_KHZ * 1000) / freq) * 18;
+
+ for (x = 18; x <= 35; x++) {
+ tk = fp / x;
+ if ((tk / 1000 == 0) || (tk / 1000 > 255))
+ continue;
+
+ k_rest = tk % 1000;
+
+ if (k_rest < (k_best_l % 1000)) {
+ k_best_l = tk;
+ x_best_l = x;
+ }
+
+ if (k_rest > (k_best_t % 1000)) {
+ k_best_t = tk;
+ x_best_t = x;
+ }
+ }
+
+ if (1000 - (k_best_t % 1000) > (k_best_l % 1000)) {
+ k_best = k_best_l;
+ x_best = x_best_l;
+ } else {
+ k_best = k_best_t;
+ x_best = x_best_t;
+ }
+
+ k_best /= 1000;
+
+#if defined(CONFIG_MX23)
+ writeb(CLKCTRL_FRAC_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);
+ writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
+ &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]);
+ writeb(CLKCTRL_FRAC_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]);
+
+ writel(CLKCTRL_PIX_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_pix_set);
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix,
+ CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE,
+ k_best << CLKCTRL_PIX_DIV_OFFSET);
+
+ while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
+ ;
+#elif defined(CONFIG_MX28)
+ writeb(CLKCTRL_FRAC_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);
+ writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
+ &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_PIX]);
+ writeb(CLKCTRL_FRAC_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]);
+
+ writel(CLKCTRL_DIS_LCDIF_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_lcdif_set);
+ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif,
+ CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE,
+ k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET);
+
+ while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY)
+ ;
+#endif
+}
+
uint32_t mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index e2b41965db..a5e388b5ad 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -30,7 +30,7 @@
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
#include <asm/arch/gpio.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
@@ -39,12 +39,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/* 1 second delay should be plenty of time for block reset. */
-#define RESET_MAX_TIMEOUT 1000000
-
-#define MXS_BLOCK_SFTRST (1 << 31)
-#define MXS_BLOCK_CLKGATE (1 << 30)
-
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
inline void lowlevel_init(void) {}
@@ -82,63 +76,6 @@ void enable_caches(void)
#endif
}
-int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
- int timeout)
-{
- while (--timeout) {
- if ((readl(&reg->reg) & mask) == mask)
- break;
- udelay(1);
- }
-
- return !timeout;
-}
-
-int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
- int timeout)
-{
- while (--timeout) {
- if ((readl(&reg->reg) & mask) == 0)
- break;
- udelay(1);
- }
-
- return !timeout;
-}
-
-int mxs_reset_block(struct mxs_register_32 *reg)
-{
- /* Clear SFTRST */
- writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
-
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
- return 1;
-
- /* Clear CLKGATE */
- writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
-
- /* Set SFTRST */
- writel(MXS_BLOCK_SFTRST, &reg->reg_set);
-
- /* Wait for CLKGATE being set */
- if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
- return 1;
-
- /* Clear SFTRST */
- writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
-
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
- return 1;
-
- /* Clear CLKGATE */
- writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
-
- if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
- return 1;
-
- return 0;
-}
-
void mx28_fixup_vt(uint32_t start_addr)
{
uint32_t *vt = (uint32_t *)0x20;
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index bc2d69c857..07db27927f 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -110,6 +110,7 @@ __weak void mxs_adjust_memory_params(uint32_t *dram_vals)
{
}
+#ifdef CONFIG_MX28
static void initialize_dram_values(void)
{
int i;
@@ -118,15 +119,36 @@ static void initialize_dram_values(void)
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+}
+#else
+static void initialize_dram_values(void)
+{
+ int i;
+
+ mxs_adjust_memory_params(dram_vals);
+
+ /*
+ * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
+ * per FSL bootlets code.
+ *
+ * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
+ * "reserved".
+ * HW_DRAM_CTL8 is setup as the last element.
+ * So skip the initialization of these HW_DRAM_CTL registers.
+ */
+ for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
+ if (i == 8 || i == 27 || i == 28 || i == 35)
+ continue;
+ writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ }
-#ifdef CONFIG_MX23
/*
* Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
* element to be set
*/
writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
-#endif
}
+#endif
static void mxs_mem_init_clock(void)
{
@@ -234,17 +256,9 @@ static void mx23_mem_setup_vddmem(void)
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
- writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
- POWER_VDDMEMCTRL_ENABLE_ILIMIT |
- POWER_VDDMEMCTRL_ENABLE_LINREG |
- POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
- &power_regs->hw_power_vddmemctrl);
+ clrbits_le32(&power_regs->hw_power_vddmemctrl,
+ POWER_VDDMEMCTRL_ENABLE_ILIMIT);
- early_delay(10000);
-
- writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
- POWER_VDDMEMCTRL_ENABLE_LINREG,
- &power_regs->hw_power_vddmemctrl);
}
static void mx23_mem_init(void)
@@ -267,22 +281,18 @@ static void mx23_mem_init(void)
initialize_dram_values();
- /* Set START bit in DRAM_CTL16 */
+ /* Set START bit in DRAM_CTL8 */
setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
early_delay(20000);
/* Adjust EMI port priority. */
- clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
+ clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
early_delay(20000);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
-
- /* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
- while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
- ;
}
#endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index 287c698ff7..21cac7b332 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -687,6 +687,12 @@ static void mxs_power_configure_power_source(void)
mxs_init_batt_bo();
mxs_switch_vddd_to_dcdc_source();
+
+#ifdef CONFIG_MX23
+ /* Fire up the VDDMEM LinReg now that we're all set. */
+ writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
+ &power_regs->hw_power_vddmemctrl);
+#endif
}
static void mxs_enable_output_rail_protection(void)
@@ -781,7 +787,11 @@ struct mxs_vddx_cfg {
static const struct mxs_vddx_cfg mxs_vddio_cfg = {
.reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
hw_power_vddioctrl),
+#if defined(CONFIG_MX23)
+ .step_mV = 25,
+#else
.step_mV = 50,
+#endif
.lowest_mV = 2800,
.powered_by_linreg = mxs_get_vddio_power_source_off,
.trg_mask = POWER_VDDIOCTRL_TRG_MASK,
@@ -804,6 +814,21 @@ static const struct mxs_vddx_cfg mxs_vddd_cfg = {
.bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
};
+#ifdef CONFIG_MX23
+static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
+ .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+ hw_power_vddmemctrl),
+ .step_mV = 50,
+ .lowest_mV = 1700,
+ .powered_by_linreg = NULL,
+ .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
+ .bo_irq = 0,
+ .bo_enirq = 0,
+ .bo_offset_mask = 0,
+ .bo_offset_offset = 0,
+};
+#endif
+
static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
uint32_t new_target, uint32_t new_brownout)
{
@@ -821,9 +846,10 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
cur_target += cfg->lowest_mV;
adjust_up = new_target > cur_target;
- powered_by_linreg = cfg->powered_by_linreg();
+ if (cfg->powered_by_linreg)
+ powered_by_linreg = cfg->powered_by_linreg();
- if (adjust_up) {
+ if (adjust_up && cfg->bo_irq) {
if (powered_by_linreg) {
bo_int = readl(cfg->reg);
clrbits_le32(cfg->reg, cfg->bo_enirq);
@@ -864,14 +890,16 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
cur_target += cfg->lowest_mV;
} while (new_target > cur_target);
- if (adjust_up && powered_by_linreg) {
- writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
- if (bo_int & cfg->bo_enirq)
- setbits_le32(cfg->reg, cfg->bo_enirq);
- }
+ if (cfg->bo_irq) {
+ if (adjust_up && powered_by_linreg) {
+ writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
+ if (bo_int & cfg->bo_enirq)
+ setbits_le32(cfg->reg, cfg->bo_enirq);
+ }
- clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
- new_brownout << cfg->bo_offset_offset);
+ clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
+ new_brownout << cfg->bo_offset_offset);
+ }
}
static void mxs_setup_batt_detect(void)
@@ -910,7 +938,9 @@ void mxs_power_init(void)
mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
-
+#ifdef CONFIG_MX23
+ mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
+#endif
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
index 3a51879d5e..8b6c30e8e9 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd
@@ -4,8 +4,8 @@ options {
}
sources {
- u_boot_spl="spl/u-boot-spl.bin";
- u_boot="u-boot.bin";
+ u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
+ u_boot="OBJTREE/u-boot.bin";
}
section (0) {
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
index c60615a456..a5fa6483a9 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd
@@ -1,6 +1,6 @@
sources {
- u_boot_spl="spl/u-boot-spl.bin";
- u_boot="u-boot.bin";
+ u_boot_spl="OBJTREE/spl/u-boot-spl.bin";
+ u_boot="OBJTREE/u-boot.bin";
}
section (0) {
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index cb4210f6e6..8b2878d4ff 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -109,6 +109,8 @@ struct ad_pll {
#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
/* PRCM */
+#define ENET_CLKCTRL_CMPL 0x30000
+
#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500)
struct cm_def {
@@ -183,7 +185,7 @@ struct cm_alwon {
unsigned int resv5[2];
unsigned int gpmcclkctrl;
unsigned int ethernet0clkctrl;
- unsigned int resv6[1];
+ unsigned int ethernet1clkctrl;
unsigned int mpuclkctrl;
unsigned int debugssclkctrl;
unsigned int l3clkctrl;
@@ -203,9 +205,67 @@ struct cm_alwon {
unsigned int custefuseclkctrl;
};
+#define SATA_PLL_BASE (CTRL_BASE + 0x0720)
+
+struct sata_pll {
+ unsigned int pllcfg0;
+ unsigned int pllcfg1;
+ unsigned int pllcfg2;
+ unsigned int pllcfg3;
+ unsigned int pllcfg4;
+ unsigned int pllstatus;
+ unsigned int rxstatus;
+ unsigned int txstatus;
+ unsigned int testcfg;
+};
+
+#define SEL_IN_FREQ (0x1 << 31)
+#define DIGCLRZ (0x1 << 30)
+#define ENDIGLDO (0x1 << 4)
+#define APLL_CP_CURR (0x1 << 3)
+#define ENBGSC_REF (0x1 << 2)
+#define ENPLLLDO (0x1 << 1)
+#define ENPLL (0x1 << 0)
+
+#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
+#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
+#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
+#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
+ ENPLLLDO | ENPLL)
+
+#define PLL_LOCK (0x1 << 0)
+
+#define ENSATAMODE (0x1 << 31)
+#define PLLREFSEL (0x1 << 30)
+#define MDIVINT (0x4b << 18)
+#define EN_CLKAUX (0x1 << 5)
+#define EN_CLK125M (0x1 << 4)
+#define EN_CLK100M (0x1 << 3)
+#define EN_CLK50M (0x1 << 2)
+
+#define SATA_PLLCFG1 (ENSATAMODE | \
+ PLLREFSEL | \
+ MDIVINT | \
+ EN_CLKAUX | \
+ EN_CLK125M | \
+ EN_CLK100M | \
+ EN_CLK50M)
+
+#define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
+#define PLLDO_EN_LDO_STABLE (0x1 << 11)
+#define PLLDO_EN_BUF_CUR (0x1 << 7)
+#define PLLDO_EN_LP (0x1 << 6)
+#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
+
+#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
+ PLLDO_EN_LDO_STABLE | \
+ PLLDO_EN_BUF_CUR | \
+ PLLDO_EN_LP | \
+ PLLDO_CTRL_TRIM_1_4V)
const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
+const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
/*
* Enable the peripheral clock for required peripherals
@@ -221,6 +281,15 @@ static void enable_per_clocks(void)
writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
;
+
+ /* Ethernet */
+ writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
+ writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
+ while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
+ ;
+ writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
+ while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
+ ;
}
/*
@@ -365,6 +434,35 @@ void ddr_pll_config(unsigned int ddrpll_m)
pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
}
+void sata_pll_config(void)
+{
+ /*
+ * This sequence for configuring the SATA PLL
+ * resident in the control module is documented
+ * in TI8148 TRM section 21.3.1
+ */
+ writel(SATA_PLLCFG1, &spll->pllcfg1);
+ udelay(50);
+
+ writel(SATA_PLLCFG3, &spll->pllcfg3);
+ udelay(50);
+
+ writel(SATA_PLLCFG0_1, &spll->pllcfg0);
+ udelay(50);
+
+ writel(SATA_PLLCFG0_2, &spll->pllcfg0);
+ udelay(50);
+
+ writel(SATA_PLLCFG0_3, &spll->pllcfg0);
+ udelay(50);
+
+ writel(SATA_PLLCFG0_4, &spll->pllcfg0);
+ udelay(50);
+
+ while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
+ ;
+}
+
void enable_emif_clocks(void) {};
void enable_dmm_clocks(void)
@@ -397,9 +495,10 @@ void pll_init()
/* Enable the control module */
writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
+ /* Configure PLLs */
mpu_pll_config();
-
l3_pll_config();
+ sata_pll_config();
/* Enable the required peripherals */
enable_per_clocks();
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c
index 5fd8b47b2d..ac049ac4f2 100644
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -92,7 +92,6 @@ u32 get_sysboot_value(void)
int print_cpuinfo(void)
{
char *cpu_s, *sec_s;
- int arm_freq, ddr_freq;
switch (get_cpu_type()) {
case AM335X:
@@ -123,10 +122,7 @@ int print_cpuinfo(void)
sec_s = "?";
}
- printf("%s-%s rev %d\n",
- cpu_s, sec_s, get_cpu_rev());
-
- /* TODO: Print ARM and DDR frequencies */
+ printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev());
return 0;
}
diff --git a/arch/arm/cpu/armv7/at91/Makefile b/arch/arm/cpu/armv7/at91/Makefile
new file mode 100644
index 0000000000..040c67d511
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2013
+# Bo Shen <voice.shen@atmel.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-$(CONFIG_SAMA5D3) += sama5d3_devices.o
+COBJS-y += clock.o
+COBJS-y += cpu.o
+COBJS-y += reset.o
+COBJS-y += timer.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/cpu/armv7/at91/clock.c
new file mode 100644
index 0000000000..624b52cc31
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/clock.c
@@ -0,0 +1,125 @@
+/*
+ * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
+ *
+ * Copyright (C) 2005 David Brownell
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static unsigned long at91_css_to_rate(unsigned long css)
+{
+ switch (css) {
+ case AT91_PMC_MCKR_CSS_SLOW:
+ return CONFIG_SYS_AT91_SLOW_CLOCK;
+ case AT91_PMC_MCKR_CSS_MAIN:
+ return gd->arch.main_clk_rate_hz;
+ case AT91_PMC_MCKR_CSS_PLLA:
+ return gd->arch.plla_rate_hz;
+ }
+
+ return 0;
+}
+
+static u32 at91_pll_rate(u32 freq, u32 reg)
+{
+ unsigned mul, div;
+
+ div = reg & 0xff;
+ mul = (reg >> 18) & 0x7f;
+ if (div && mul) {
+ freq /= div;
+ freq *= mul + 1;
+ } else {
+ freq = 0;
+ }
+
+ return freq;
+}
+
+int at91_clock_init(unsigned long main_clock)
+{
+ unsigned freq, mckr;
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+ unsigned tmp;
+ /*
+ * When the bootloader initialized the main oscillator correctly,
+ * there's no problem using the cycle counter. But if it didn't,
+ * or when using oscillator bypass mode, we must be told the speed
+ * of the main clock.
+ */
+ if (!main_clock) {
+ do {
+ tmp = readl(&pmc->mcfr);
+ } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
+ tmp &= AT91_PMC_MCFR_MAINF_MASK;
+ main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
+ }
+#endif
+ gd->arch.main_clk_rate_hz = main_clock;
+
+ /* report if PLLA is more than mildly overclocked */
+ gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+
+ /*
+ * MCK and CPU derive from one of those primary clocks.
+ * For now, assume this parentage won't change.
+ */
+ mckr = readl(&pmc->mckr);
+
+ /* plla divisor by 2 */
+ if (mckr & (1 << 12))
+ gd->arch.plla_rate_hz >>= 1;
+
+ gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+ freq = gd->arch.mck_rate_hz;
+
+ /* prescale */
+ freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
+
+ switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
+ case AT91_PMC_MCKR_MDIV_2:
+ gd->arch.mck_rate_hz = freq / 2;
+ break;
+ case AT91_PMC_MCKR_MDIV_3:
+ gd->arch.mck_rate_hz = freq / 3;
+ break;
+ case AT91_PMC_MCKR_MDIV_4:
+ gd->arch.mck_rate_hz = freq / 4;
+ break;
+ default:
+ break;
+ }
+
+ gd->arch.cpu_clk_rate_hz = freq;
+
+ return 0;
+}
+
+void at91_periph_clk_enable(int id)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ if (id > 31)
+ writel(1 << (id - 32), &pmc->pcer1);
+ else
+ writel(1 << id, &pmc->pcer);
+}
diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c
new file mode 100644
index 0000000000..3df6143d74
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/cpu.c
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
+ * (C) Copyright 2009
+ * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_dbu.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_gpbr.h>
+#include <asm/arch/clk.h>
+
+#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
+#define CONFIG_SYS_AT91_MAIN_CLOCK 0
+#endif
+
+int arch_cpu_init(void)
+{
+ return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+}
+
+void arch_preboot_os(void)
+{
+ ulong cpiv;
+ at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+ cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
+
+ /*
+ * Disable PITC
+ * Add 0x1000 to current counter to stop it faster
+ * without waiting for wrapping back to 0
+ */
+ writel(cpiv + 0x1000, &pit->mr);
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ char buf[32];
+
+ printf("CPU: %s\n", get_cpu_name());
+ printf("Crystal frequency: %8s MHz\n",
+ strmhz(buf, get_main_clk_rate()));
+ printf("CPU clock : %8s MHz\n",
+ strmhz(buf, get_cpu_clk_rate()));
+ printf("Master clock : %8s MHz\n",
+ strmhz(buf, get_mck_clk_rate()));
+
+ return 0;
+}
+#endif
+
+void enable_caches(void)
+{
+}
+
+unsigned int get_chip_id(void)
+{
+ return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+ return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
+}
diff --git a/arch/arm/cpu/armv7/at91/reset.c b/arch/arm/cpu/armv7/at91/reset.c
new file mode 100644
index 0000000000..b9f83d91b9
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/reset.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_rstc.h>
+
+/* Reset the cpu by telling the reset controller to do so */
+void reset_cpu(ulong ignored)
+{
+ at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
+
+ writel(AT91_RSTC_KEY
+ | AT91_RSTC_CR_PROCRST /* Processor Reset */
+ | AT91_RSTC_CR_PERRST /* Peripheral Reset */
+#ifdef CONFIG_AT91RESET_EXTRST
+ | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */
+#endif
+ , &rstc->cr);
+ /* never reached */
+ do { } while (1);
+}
diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
new file mode 100644
index 0000000000..acf8b43ee6
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2012-2013 Atmel Corporation
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/sama5d3.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+unsigned int has_emac()
+{
+ return cpu_is_sama5d31() || cpu_is_sama5d35();
+}
+
+unsigned int has_gmac()
+{
+ return !cpu_is_sama5d31();
+}
+
+unsigned int has_lcdc()
+{
+ return !cpu_is_sama5d35();
+}
+
+char *get_cpu_name()
+{
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_sama5d3())
+ switch (extension_id) {
+ case ARCH_EXID_SAMA5D31:
+ return "SAMA5D31";
+ case ARCH_EXID_SAMA5D33:
+ return "SAMA5D33";
+ case ARCH_EXID_SAMA5D34:
+ return "SAMA5D34";
+ case ARCH_EXID_SAMA5D35:
+ return "SAMA5D35";
+ default:
+ return "Unknown CPU type";
+ }
+ else
+ return "Unknown CPU type";
+}
+
+void at91_serial0_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */
+ at91_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_USART0);
+}
+
+void at91_serial1_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */
+ at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_USART1);
+}
+
+void at91_serial2_hw_init(void)
+{
+ at91_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */
+ at91_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_USART2);
+}
+
+void at91_seriald_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */
+ at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_SYS);
+}
+
+#if defined(CONFIG_ATMEL_SPI)
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+ at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */
+
+ if (cs_mask & (1 << 0))
+ at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
+ if (cs_mask & (1 << 1))
+ at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
+ if (cs_mask & (1 << 2))
+ at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
+ if (cs_mask & (1 << 3))
+ at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void at91_mci_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */
+ at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */
+ at91_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */
+ at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */
+ at91_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */
+#ifdef CONFIG_ATMEL_MCI_8BIT
+ at91_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */
+ at91_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */
+ at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */
+ at91_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */
+#endif
+ at91_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_MCI0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */
+ at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */
+ at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_EMAC);
+}
+#endif
+
+#ifdef CONFIG_LCD
+void at91_lcd_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
+ at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
+ at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
+
+ /* The lower 16-bit of LCD only available on Port A */
+ at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
+ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
+ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */
+ at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */
+ at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
+ at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_LCDC);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c
new file mode 100644
index 0000000000..b3a450fb31
--- /dev/null
+++ b/arch/arm/cpu/armv7/at91/timer.c
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2013
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pit.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/clk.h>
+#include <div64.h>
+
+#if !defined(CONFIG_AT91FAMILY)
+# error You need to define CONFIG_AT91FAMILY in your board config!
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * We're using the SAMA5D3x PITC in 32 bit mode, by
+ * setting the 20 bit counter period to its maximum (0xfffff).
+ * (See the relevant data sheets to understand that this really works)
+ *
+ * We do also mimic the typical powerpc way of incrementing
+ * two 32 bit registers called tbl and tbu.
+ *
+ * Those registers increment at 1/16 the main clock rate.
+ */
+
+#define TIMER_LOAD_VAL 0xfffff
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, gd->arch.timer_rate_hz);
+
+ return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+ usec *= gd->arch.timer_rate_hz;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
+/*
+ * Use the PITC in full 32 bit incrementing mode
+ */
+int timer_init(void)
+{
+ at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+ /* Enable PITC Clock */
+ at91_periph_clk_enable(ATMEL_ID_SYS);
+
+ /* Enable PITC */
+ writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
+
+ gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
+ gd->arch.tbu = 0;
+ gd->arch.tbl = 0;
+
+ return 0;
+}
+
+/*
+ * Get the current 64 bit timer tick count
+ */
+unsigned long long get_ticks(void)
+{
+ at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
+
+ ulong now = readl(&pit->piir);
+
+ /* increment tbu if tbl has rolled over */
+ if (now < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl = now;
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long long start;
+ ulong tmo;
+
+ start = get_ticks(); /* get current timestamp */
+ tmo = usec_to_tick(usec); /* convert usecs to ticks */
+ while ((get_ticks() - start) < tmo)
+ ; /* loop till time has passed */
+}
+
+/*
+ * get_timer(base) can be used to check for timeouts or
+ * to measure elasped time relative to an event:
+ *
+ * ulong start_time = get_timer(0) sets start_time to the current
+ * time value.
+ * get_timer(start_time) returns the time elapsed since then.
+ *
+ * The time is used in CONFIG_SYS_HZ units!
+ */
+ulong get_timer(ulong base)
+{
+ return tick_to_time(get_ticks()) - base;
+}
+
+/*
+ * Return the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return gd->arch.timer_rate_hz;
+}
diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S
index 0d45528e99..0a15aa4671 100644
--- a/arch/arm/cpu/armv7/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/lowlevel_init.S
@@ -37,7 +37,13 @@ ENTRY(lowlevel_init)
*/
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
-
+#ifdef CONFIG_SPL_BUILD
+ ldr r8, =gdata
+#else
+ sub sp, #GD_SIZE
+ bic sp, sp, #7
+ mov r8, sp
+#endif
/*
* Save the old lr(passed in ip) and the current lr to stack
*/
diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile
index ecd1184213..e05fae91a1 100644
--- a/arch/arm/cpu/armv7/mx5/Makefile
+++ b/arch/arm/cpu/armv7/mx5/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
-COBJS = soc.o clock.o iomux.o
+COBJS = soc.o clock.o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 76c2c529a8..431756ed69 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -739,10 +739,11 @@ static int config_core_clk(u32 ref, u32 freq)
static int config_nfc_clk(u32 nfc_clk)
{
u32 parent_rate = get_emi_slow_clk();
- u32 div = parent_rate / nfc_clk;
+ u32 div;
- if (nfc_clk <= 0)
+ if (nfc_clk == 0)
return -EINVAL;
+ div = parent_rate / nfc_clk;
if (div == 0)
div++;
if (parent_rate / div > NFC_CLK_MAX)
@@ -755,6 +756,15 @@ static int config_nfc_clk(u32 nfc_clk)
return 0;
}
+void enable_nfc_clk(unsigned char enable)
+{
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+ clrsetbits_le32(&mxc_ccm->CCGR5,
+ MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR5_EMI_ENFC(cg));
+}
+
/* Config main_bus_clock for periphs */
static int config_periph_clk(u32 ref, u32 freq)
{
diff --git a/arch/arm/cpu/armv7/mx5/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c
deleted file mode 100644
index d4e3bbb437..0000000000
--- a/arch/arm/cpu/armv7/mx5/iomux.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
-#include <asm/arch/sys_proto.h>
-
-/* IOMUX register (base) addresses */
-enum iomux_reg_addr {
- IOMUXGPR0 = IOMUXC_BASE_ADDR,
- IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
- IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
- IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
- IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
- IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
-};
-
-#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
-
-/* Get the iomux register address of this pin */
-static inline u32 get_mux_reg(iomux_pin_name_t pin)
-{
- u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
-
-#if defined(CONFIG_MX51)
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- /*
- * Fixup register address:
- * i.MX51 TO1 has offset with the register
- * which is define as TO2.
- */
- if ((pin == MX51_PIN_NANDF_RB5) ||
- (pin == MX51_PIN_NANDF_RB6) ||
- (pin == MX51_PIN_NANDF_RB7))
- ; /* Do nothing */
- else if (mux_reg >= 0x2FC)
- mux_reg += 8;
- else if (mux_reg >= 0x130)
- mux_reg += 0xC;
- }
-#endif
- mux_reg += IOMUXSW_MUX_CTL;
- return mux_reg;
-}
-
-/* Get the pad register address of this pin */
-static inline u32 get_pad_reg(iomux_pin_name_t pin)
-{
- u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
-
-#if defined(CONFIG_MX51)
- if (is_soc_rev(CHIP_REV_2_0) < 0) {
- /*
- * Fixup register address:
- * i.MX51 TO1 has offset with the register
- * which is define as TO2.
- */
- if ((pin == MX51_PIN_NANDF_RB5) ||
- (pin == MX51_PIN_NANDF_RB6) ||
- (pin == MX51_PIN_NANDF_RB7))
- ; /* Do nothing */
- else if (pad_reg == 0x4D0 - PAD_I_START)
- pad_reg += 0x4C;
- else if (pad_reg == 0x860 - PAD_I_START)
- pad_reg += 0x9C;
- else if (pad_reg >= 0x804 - PAD_I_START)
- pad_reg += 0xB0;
- else if (pad_reg >= 0x7FC - PAD_I_START)
- pad_reg += 0xB4;
- else if (pad_reg >= 0x4E4 - PAD_I_START)
- pad_reg += 0xCC;
- else
- pad_reg += 8;
- }
-#endif
- pad_reg += IOMUXSW_PAD_CTL;
- return pad_reg;
-}
-
-/* Get the last iomux register address */
-static inline u32 get_mux_end(void)
-{
-#if defined(CONFIG_MX51)
- if (is_soc_rev(CHIP_REV_2_0) < 0)
- return IOMUXC_BASE_ADDR + (0x3F8 - 4);
- else
- return IOMUXC_BASE_ADDR + (0x3F0 - 4);
-#endif
- return IOMUXSW_MUX_END;
-}
-
-/*
- * This function is used to configure a pin through the IOMUX module.
- * @param pin a pin number as defined in iomux_pin_name_t
- * @param cfg an output function as defined in iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- u32 mux_reg = get_mux_reg(pin);
-
- if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
- return ;
- if (cfg == IOMUX_CONFIG_GPIO)
- writel(PIN_TO_ALT_GPIO(pin), mux_reg);
- else
- writel(cfg, mux_reg);
-}
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by iomux_pin_name_t
- * @param cfg an input function as defined in iomux_pin_cfg_t
- *
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
- iomux_config_mux(pin, cfg);
-}
-
-/*
- * Release ownership for an IO pin
- *
- * @param pin a name defined by iomux_pin_name_t
- * @param cfg an input function as defined in iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
-{
-}
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in iomux_pin_name_t
- * @param config the ORed value of elements defined in iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
-{
- u32 pad_reg = get_pad_reg(pin);
- writel(config, pad_reg);
-}
-
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
-{
- u32 pad_reg = get_pad_reg(pin);
- return readl(pad_reg);
-}
-
-/*
- * This function configures daisy-chain
- *
- * @param input index of input select register
- * @param config the binary value of elements
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
-{
- u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
-
- writel(config, reg);
-}
diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 263658aa4b..3d50a5d8ee 100644
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -72,6 +72,13 @@ u32 get_cpu_rev(void)
return system_rev;
}
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+#endif
+
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index a50db70b19..3c0d908d17 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -37,6 +37,20 @@ enum pll_clocks {
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+ u32 reg;
+
+ reg = __raw_readl(&imx_ccm->CCGR2);
+ if (enable)
+ reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+ else
+ reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
+ __raw_writel(reg, &imx_ccm->CCGR2);
+}
+#endif
+
void enable_usboh3_clk(unsigned char enable)
{
u32 reg;
@@ -186,12 +200,16 @@ static u32 get_ipg_per_clk(void)
static u32 get_uart_clk(void)
{
u32 reg, uart_podf;
-
+ u32 freq = PLL3_80M;
reg = __raw_readl(&imx_ccm->cscdr1);
+#ifdef CONFIG_MX6SL
+ if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+ freq = MXC_HCLK;
+#endif
reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
- return PLL3_80M / (uart_podf + 1);
+ return freq / (uart_podf + 1);
}
static u32 get_cspi_clk(void)
@@ -252,6 +270,35 @@ static u32 get_emi_slow_clk(void)
return root_freq / (emi_slow_pof + 1);
}
+#ifdef CONFIG_MX6SL
+static u32 get_mmdc_ch0_clk(void)
+{
+ u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
+ u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+ u32 freq, podf;
+
+ podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
+ >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+
+ switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+ MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+ case 0:
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
+ break;
+ case 1:
+ freq = PLL2_PFD2_FREQ;
+ break;
+ case 2:
+ freq = PLL2_PFD0_FREQ;
+ break;
+ case 3:
+ freq = PLL2_PFD2_DIV_FREQ;
+ }
+
+ return freq / (podf + 1);
+
+}
+#else
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
@@ -260,6 +307,7 @@ static u32 get_mmdc_ch0_clk(void)
return get_periph_clk() / (mmdc_ch0_podf + 1);
}
+#endif
static u32 get_usdhc_clk(u32 port)
{
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 2ea8ca3bd3..fc436fbee7 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -30,6 +30,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/dma.h>
#include <stdbool.h>
struct scu_regs {
@@ -151,6 +152,12 @@ int arch_cpu_init(void)
set_vddsoc(1200); /* Set VDDSOC to 1.2V */
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
+
+#ifdef CONFIG_APBH_DMA
+ /* Start APBH DMA */
+ mxs_dma_init();
+#endif
+
return 0;
}
@@ -165,8 +172,8 @@ void enable_caches(void)
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
- struct fuse_bank *bank = &iim->bank[4];
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[4];
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 24cbe2da05..bff7e9c82a 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -23,31 +23,17 @@
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
-/*
- * This is used to verify if the configuration header
- * was executed by rom code prior to control of transfer
- * to the bootloader. SPL is responsible for saving and
- * passing the boot_params pointer to the u-boot.
- */
-struct omap_boot_parameters boot_params __attribute__ ((section(".data")));
+DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
-/*
- * We use static variables because global data is not ready yet.
- * Initialized data is available in SPL right from the beginning.
- * We would not typically need to save these parameters in regular
- * U-Boot. This is needed only in SPL at the moment.
- */
-u32 omap_bootmode = MMCSD_MODE_FAT;
-
u32 spl_boot_device(void)
{
- return (u32) (boot_params.omap_bootdevice);
+ return (u32) (gd->arch.omap_boot_params.omap_bootdevice);
}
u32 spl_boot_mode(void)
{
- return omap_bootmode;
+ return gd->arch.omap_boot_params.omap_bootmode;
}
void spl_board_init(void)
@@ -73,4 +59,15 @@ int board_mmc_init(bd_t *bis)
}
return 0;
}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+ typedef void __noreturn (*image_entry_noargs_t)(u32 *);
+ image_entry_noargs_t image_entry =
+ (image_entry_noargs_t) spl_image->entry_point;
+
+ debug("image entry point: 0x%X\n", spl_image->entry_point);
+ /* Pass the saved boot_params from rom code */
+ image_entry((u32 *)&gd->arch.omap_boot_params);
+}
#endif
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 2b955c7c00..99910cdcb0 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -716,6 +716,7 @@ void prcm_init(void)
setup_non_essential_dplls();
enable_non_essential_clocks();
#endif
+ setup_warmreset_time();
break;
default:
break;
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index cdb4439721..11e830a533 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1075,6 +1075,11 @@ static void do_sdram_init(u32 base)
else
ddr3_init(base, regs);
}
+ if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
+ set_lpmode_selfrefresh(base);
+ emif_reset_phy(base);
+ ddr3_leveling(base, regs);
+ }
/* Write to the shadow registers */
emif_update_timings(base, regs);
@@ -1262,10 +1267,10 @@ void sdram_init(void)
in_sdram = running_from_sdram();
debug("in_sdram = %d\n", in_sdram);
- if (!(in_sdram || warm_reset())) {
- if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
+ if (!in_sdram) {
+ if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
bypass_dpll((*prcm)->cm_clkmode_dpll_core);
- else
+ else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
}
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 70d16a8160..1645120de7 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -101,11 +101,6 @@ void omap_rev_string(void)
}
#ifdef CONFIG_SPL_BUILD
-static void init_boot_params(void)
-{
- boot_params_ptr = (u32 *) &boot_params;
-}
-
void spl_display_print(void)
{
omap_rev_string();
@@ -116,6 +111,53 @@ void __weak srcomp_enable(void)
{
}
+static void save_omap_boot_params(void)
+{
+ u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
+ u8 boot_device;
+ u32 dev_desc, dev_data;
+
+ if ((rom_params < NON_SECURE_SRAM_START) ||
+ (rom_params > NON_SECURE_SRAM_END))
+ return;
+
+ /*
+ * rom_params can be type casted to omap_boot_parameters and
+ * used. But it not correct to assume that romcode structure
+ * encoding would be same as u-boot. So use the defined offsets.
+ */
+ gd->arch.omap_boot_params.omap_bootdevice = boot_device =
+ *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
+
+ gd->arch.omap_boot_params.ch_flags =
+ *((u8 *)(rom_params + CH_FLAGS_OFFSET));
+
+ if ((boot_device >= MMC_BOOT_DEVICES_START) &&
+ (boot_device <= MMC_BOOT_DEVICES_END)) {
+ if ((omap_hw_init_context() ==
+ OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
+ gd->arch.omap_boot_params.omap_bootmode =
+ *((u8 *)(rom_params + BOOT_MODE_OFFSET));
+ } else {
+ dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
+ dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
+ gd->arch.omap_boot_params.omap_bootmode =
+ *((u32 *)(dev_data + BOOT_MODE_OFFSET));
+ }
+ }
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+/*
+ * SOC specific cpu init
+ */
+int arch_cpu_init(void)
+{
+ save_omap_boot_params();
+ return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
/*
* Routine: s_init
* Description: Does early system init of watchdog, muxing, andclocks
@@ -132,6 +174,14 @@ void __weak srcomp_enable(void)
*/
void s_init(void)
{
+ /*
+ * Save the boot parameters passed from romcode.
+ * We cannot delay the saving further than this,
+ * to prevent overwrites.
+ */
+#ifdef CONFIG_SPL_BUILD
+ save_omap_boot_params();
+#endif
init_omap_revision();
hw_data_init();
@@ -156,7 +206,6 @@ void s_init(void)
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
- init_boot_params();
#endif
}
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 90b3c8aea4..c4895369bf 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -28,59 +28,13 @@
#include <config.h>
#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
#include <asm/arch/spl.h>
#include <linux/linkage.h>
ENTRY(save_boot_params)
- /*
- * See if the rom code passed pointer is valid:
- * It is not valid if it is not in non-secure SRAM
- * This may happen if you are booting with the help of
- * debugger
- */
- ldr r2, =NON_SECURE_SRAM_START
- cmp r2, r0
- bgt 1f
- ldr r2, =NON_SECURE_SRAM_END
- cmp r2, r0
- blt 1f
-
- /*
- * store the boot params passed from rom code or saved
- * and passed by SPL
- */
- cmp r0, #0
- beq 1f
- ldr r1, =boot_params
+ ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
str r0, [r1]
-#ifdef CONFIG_SPL_BUILD
- /* Store the boot device in spl_boot_device */
- ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device
- and r2, #BOOT_DEVICE_MASK
- ldr r3, =boot_params
- strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1
-
- /*
- * boot mode is only valid for device that can be raw or FAT booted.
- * in other cases it may be fatal to look. While platforms differ
- * in the values used for each MMC slot, they are contiguous.
- */
- cmp r2, #MMC_BOOT_DEVICES_START
- blt 2f
- cmp r2, #MMC_BOOT_DEVICES_END
- bgt 2f
- /* Store the boot mode (raw/FAT) in omap_bootmode */
- ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr
- ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr
- ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode
- ldr r3, =omap_bootmode
- str r2, [r3]
-#endif
-2:
- ldrb r2, [r0, #CH_FLAGS_OFFSET]
- ldr r3, =boot_params
- strb r2, [r3, #CH_FLAGS_OFFSET]
-1:
bx lr
ENDPROC(save_boot_params)
diff --git a/arch/arm/cpu/armv7/omap-common/reset.c b/arch/arm/cpu/armv7/omap-common/reset.c
index 587bb47745..57ea9d9999 100644
--- a/arch/arm/cpu/armv7/omap-common/reset.c
+++ b/arch/arm/cpu/armv7/omap-common/reset.c
@@ -39,3 +39,7 @@ u32 __weak warm_reset(void)
{
return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK);
}
+
+void __weak setup_warmreset_time(void)
+{
+}
diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c
index 53f60635b1..0ddf35f79b 100644
--- a/arch/arm/cpu/armv7/omap4/emif.c
+++ b/arch/arm/cpu/armv7/omap4/emif.c
@@ -31,8 +31,8 @@
#include <asm/utils.h>
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM;
-u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN;
+u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
+u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 04977b4f2b..06a2fc8c2f 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -40,7 +40,7 @@ struct dplls const **dplls_data =
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
- (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
+ (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
/*
* The M & N values in the following tables are created using the
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index 2db517b1bf..81f5a48e50 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -34,10 +34,11 @@
#include <asm/sizes.h>
#include <asm/emif.h>
#include <asm/arch/gpio.h>
+#include <asm/omap_common.h>
DECLARE_GLOBAL_DATA_PTR;
-u32 *const omap_si_rev = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
+u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
static const struct gpio_bank gpio_bank_44xx[6] = {
{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
diff --git a/arch/arm/cpu/armv7/omap5/emif.c b/arch/arm/cpu/armv7/omap5/emif.c
index 3f37abdf83..b4c1319adc 100644
--- a/arch/arm/cpu/armv7/omap5/emif.c
+++ b/arch/arm/cpu/armv7/omap5/emif.c
@@ -32,8 +32,8 @@
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
-static u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM;
-static u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN;
+static u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM;
+static u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN;
#endif
#ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index ced274e4db..604fa42b1b 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -41,7 +41,7 @@ struct dplls const **dplls_data =
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
- (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
+ (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
/* OPP HIGH FREQUENCY for ES2.0 */
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
@@ -403,6 +403,7 @@ void enable_basic_uboot_clocks(void)
};
u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_l3init_hsusbtll_clkctrl,
0
};
@@ -411,7 +412,7 @@ void enable_basic_uboot_clocks(void)
(*prcm)->cm_l4per_i2c2_clkctrl,
(*prcm)->cm_l4per_i2c3_clkctrl,
(*prcm)->cm_l4per_i2c4_clkctrl,
- (*prcm)->cm_l3init_hsusbtll_clkctrl,
+ (*prcm)->cm_l4per_i2c5_clkctrl,
(*prcm)->cm_l3init_hsusbhost_clkctrl,
(*prcm)->cm_l3init_fsusb_clkctrl,
0
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 2f4b24752b..e192fea0eb 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -37,10 +37,11 @@
#include <asm/utils.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
+#include <asm/omap_common.h>
DECLARE_GLOBAL_DATA_PTR;
-u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
+u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
static struct gpio_bank gpio_bank_54xx[6] = {
{ (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -363,3 +364,22 @@ u32 warm_reset(void)
{
return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
}
+
+void setup_warmreset_time(void)
+{
+ u32 rst_time, rst_val;
+
+#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
+ rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
+#else
+ rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
+#endif
+ rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
+
+ if (rst_time > RSTTIME1_MASK)
+ rst_time = RSTTIME1_MASK;
+
+ rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
+ rst_val |= rst_time;
+ writel(rst_val, (*prcm)->prm_rsttime);
+}
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index b8a61fe881..e9f6a32653 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -729,6 +729,7 @@ struct prcm_regs const omap5_es2_prcm = {
.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
.prm_rstctrl = 0x4ae07c00,
.prm_rstst = 0x4ae07c04,
+ .prm_rsttime = 0x4ae07c08,
.prm_vc_val_bypass = 0x4ae07ca0,
.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
@@ -952,6 +953,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_wkupaon_scrm_clkctrl = 0x4ae07890,
.prm_rstctrl = 0x4ae07d00,
.prm_rstst = 0x4ae07d04,
+ .prm_rsttime = 0x4ae07d08,
.prm_vc_val_bypass = 0x4ae07da0,
.prm_vc_cfg_i2c_mode = 0x4ae07db4,
.prm_vc_cfg_i2c_clk = 0x4ae07db8,
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 788a8fd14f..52048c6766 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -28,6 +28,9 @@
#define SLCR_LOCK_MAGIC 0x767B
#define SLCR_UNLOCK_MAGIC 0xDF0D
+#define SLCR_IDCODE_MASK 0x1F000
+#define SLCR_IDCODE_SHIFT 12
+
static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
void zynq_slcr_lock(void)
@@ -61,3 +64,61 @@ void zynq_slcr_cpu_reset(void)
writel(1, &slcr_base->pss_rst_ctrl);
}
+
+/* Setup clk for network */
+void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
+{
+ zynq_slcr_unlock();
+
+ if (gem_id > 1) {
+ printf("Non existing GEM id %d\n", gem_id);
+ goto out;
+ }
+
+ if (gem_id) {
+ /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
+ writel(clk, &slcr_base->gem1_clk_ctrl);
+ /* Configure GEM_RCLK_CTRL */
+ writel(rclk, &slcr_base->gem1_rclk_ctrl);
+ } else {
+ /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
+ writel(clk, &slcr_base->gem0_clk_ctrl);
+ /* Configure GEM_RCLK_CTRL */
+ writel(rclk, &slcr_base->gem0_rclk_ctrl);
+ }
+
+out:
+ zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_disable(void)
+{
+ zynq_slcr_unlock();
+
+ /* Disable AXI interface */
+ writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
+
+ /* Set Level Shifters DT618760 */
+ writel(0xA, &slcr_base->lvl_shftr_en);
+
+ zynq_slcr_lock();
+}
+
+void zynq_slcr_devcfg_enable(void)
+{
+ zynq_slcr_unlock();
+
+ /* Set Level Shifters DT618760 */
+ writel(0xF, &slcr_base->lvl_shftr_en);
+
+ /* Disable AXI interface */
+ writel(0x0, &slcr_base->fpga_rst_ctrl);
+
+ zynq_slcr_lock();
+}
+
+u32 zynq_slcr_get_idcode(void)
+{
+ return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
+ SLCR_IDCODE_SHIFT;
+}
diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c
index 45b405a4ba..8c4357de42 100644
--- a/arch/arm/cpu/armv7/zynq/timer.c
+++ b/arch/arm/cpu/armv7/zynq/timer.c
@@ -44,6 +44,7 @@
#include <common.h>
#include <div64.h>
#include <asm/io.h>
+#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -54,7 +55,7 @@ struct scu_timer {
};
static struct scu_timer *timer_base =
- (struct scu_timer *) CONFIG_SCUTIMER_BASEADDR;
+ (struct scu_timer *)ZYNQ_SCUTIMER_BASEADDR;
#define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */
#define SCUTIMER_CONTROL_PRESCALER_SHIFT 8
@@ -114,15 +115,43 @@ ulong get_timer_masked(void)
void __udelay(unsigned long usec)
{
- unsigned long long tmp;
- ulong tmo;
-
- tmo = usec / (1000000 / CONFIG_SYS_HZ);
- tmp = get_ticks() + tmo; /* Get current timestamp */
-
- while (get_ticks() < tmp) { /* Loop till event */
- /* NOP */;
- }
+ u32 countticks;
+ u32 timeend;
+ u32 timediff;
+ u32 timenow;
+
+ if (usec == 0)
+ return;
+
+ countticks = (u32) (((unsigned long long) TIMER_TICK_HZ * usec) /
+ 1000000);
+
+ /* decrementing timer */
+ timeend = readl(&timer_base->counter) - countticks;
+
+#if TIMER_LOAD_VAL != 0xFFFFFFFF
+ /* do not manage multiple overflow */
+ if (countticks >= TIMER_LOAD_VAL)
+ countticks = TIMER_LOAD_VAL - 1;
+#endif
+
+ do {
+ timenow = readl(&timer_base->counter);
+
+ if (timenow >= timeend) {
+ /* normal case */
+ timediff = timenow - timeend;
+ } else {
+ if ((TIMER_LOAD_VAL - timeend + timenow) <=
+ countticks) {
+ /* overflow */
+ timediff = TIMER_LOAD_VAL - timeend + timenow;
+ } else {
+ /* missed the exact match */
+ break;
+ }
+ }
+ } while (timediff > 0);
}
/* Timer without interrupts */
diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk
index b02e8af6ec..fd3c29f624 100644
--- a/arch/arm/cpu/ixp/config.mk
+++ b/arch/arm/cpu/ixp/config.mk
@@ -31,10 +31,6 @@ PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
PLATFORM_LDFLAGS += -EB
USE_PRIVATE_LIBGCC = yes
-# -fdata-sections triggers "section .bss overlaps section .rel.dyn" linker error
-PLATFORM_RELFLAGS += -ffunction-sections
-LDFLAGS_u-boot += --gc-sections
-
# =========================================================================
#
# Supply options according to compiler version
diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c
index 09e8177f7b..0c186101ec 100644
--- a/arch/arm/cpu/pxa/pxa2xx.c
+++ b/arch/arm/cpu/pxa/pxa2xx.c
@@ -284,7 +284,7 @@ void i2c_clk_enable(void)
writel(readl(CKEN) | CKEN14_I2C, CKEN);
}
-void reset_cpu(ulong ignored) __attribute__((noreturn));
+void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
void reset_cpu(ulong ignored)
{
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 9b77b2b82e..e099683890 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -72,6 +72,7 @@ int tegra_get_chip_sku(void)
switch (chip_id) {
case CHIPID_TEGRA20:
switch (sku_id) {
+ case SKU_ID_T20_7:
case SKU_ID_T20:
return TEGRA_SOC_T20;
case SKU_ID_T25SE:
@@ -92,6 +93,7 @@ int tegra_get_chip_sku(void)
case CHIPID_TEGRA114:
switch (sku_id) {
case SKU_ID_T114_ENG:
+ case SKU_ID_T114_1:
return TEGRA_SOC_T114;
}
break;
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 9156d009b2..268fb912b5 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -321,17 +321,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
unsigned effective_rate;
int mux_bits, divider_bits, source;
int divider;
+ int xdiv = 0;
/* work out the source clock and set it */
source = get_periph_clock_source(periph_id, parent, &mux_bits,
&divider_bits);
+ divider = find_best_divider(divider_bits, pll_rate[parent],
+ rate, &xdiv);
if (extra_div)
- divider = find_best_divider(divider_bits, pll_rate[parent],
- rate, extra_div);
- else
- divider = clk_get_divider(divider_bits, pll_rate[parent],
- rate);
+ *extra_div = xdiv;
+
assert(divider >= 0);
if (adjust_periph_pll(periph_id, source, mux_bits, divider))
return -1U;
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 44b6822805..8bba8a57bf 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -27,10 +27,16 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libimx-common.o
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6))
+COBJS-y = iomux-v3.o
+endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
-COBJS-y = iomux-v3.o timer.o cpu.o speed.o
+COBJS-y += timer.o cpu.o speed.o
COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
endif
+ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
+COBJS-y += misc.o
+endif
COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
COBJS-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
COBJS := $(sort $(COBJS-y))
@@ -58,8 +64,11 @@ $(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONF
$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
-I binary -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.imx
- cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.bin > $@
- rm $(OBJTREE)/spl/u-boot-spl-pad.imx
+ $(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
+ -e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \
+ $(OBJTREE)/u-boot.uim
+ cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim > $@
+ rm $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.uim
$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
(echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
@@ -69,8 +78,11 @@ $(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
-I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \
$(OBJTREE)/spl/u-boot-nand-spl-pad.imx
rm $(OBJTREE)/spl/u-boot-nand-spl.imx
- cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.bin > $@
- rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx
+ $(OBJTREE)/tools/mkimage -A arm -O U-Boot -a $(CONFIG_SYS_TEXT_BASE) \
+ -e $(CONFIG_SYS_TEXT_BASE) -C none -d $(OBJTREE)/u-boot.bin \
+ $(OBJTREE)/u-boot.uim
+ cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim > $@
+ rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.uim
#########################################################################
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 08fad7851c..7fe5ce7ce5 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -30,7 +30,7 @@ static void *base = (void *)IOMUXC_BASE_ADDR;
/*
* configures a single pad in the iomuxer
*/
-int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
{
u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
@@ -50,22 +50,14 @@ int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
-
- return 0;
}
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
- unsigned count)
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+ unsigned count)
{
iomux_v3_cfg_t const *p = pad_list;
int i;
- int ret;
- for (i = 0; i < count; i++) {
- ret = imx_iomux_v3_setup_pad(*p);
- if (ret)
- return ret;
- p++;
- }
- return 0;
+ for (i = 0; i < count; i++)
+ imx_iomux_v3_setup_pad(*p++);
}
diff --git a/arch/arm/imx-common/misc.c b/arch/arm/imx-common/misc.c
new file mode 100644
index 0000000000..220785ca9e
--- /dev/null
+++ b/arch/arm/imx-common/misc.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2013 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/imx-common/regs-common.h>
+
+/* 1 second delay should be plenty of time for block reset. */
+#define RESET_MAX_TIMEOUT 1000000
+
+#define MXS_BLOCK_SFTRST (1 << 31)
+#define MXS_BLOCK_CLKGATE (1 << 30)
+
+int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
+ int timeout)
+{
+ while (--timeout) {
+ if ((readl(&reg->reg) & mask) == mask)
+ break;
+ udelay(1);
+ }
+
+ return !timeout;
+}
+
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
+ int timeout)
+{
+ while (--timeout) {
+ if ((readl(&reg->reg) & mask) == 0)
+ break;
+ udelay(1);
+ }
+
+ return !timeout;
+}
+
+int mxs_reset_block(struct mxs_register_32 *reg)
+{
+ /* Clear SFTRST */
+ writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
+
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear CLKGATE */
+ writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
+
+ /* Set SFTRST */
+ writel(MXS_BLOCK_SFTRST, &reg->reg_set);
+
+ /* Wait for CLKGATE being set */
+ if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear SFTRST */
+ writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
+
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+ return 1;
+
+ /* Clear CLKGATE */
+ writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
+
+ if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+ return 1;
+
+ return 0;
+}
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index fb4e78edfe..bb53a6a14e 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -117,6 +117,23 @@
#define MT41J512M8RH125_PHY_WR_DATA 0x74
#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
+/* Samsung K4B2G1646E-BIH9 */
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06
+#define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B
+#define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A
+#define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F
+#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2
+#define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B
+#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
+#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
+#define K4B2G1646EBIH9_RATIO 0x40
+#define K4B2G1646EBIH9_INVERT_CLKOUT 0x1
+#define K4B2G1646EBIH9_RD_DQS 0x3B
+#define K4B2G1646EBIH9_WR_DQS 0x85
+#define K4B2G1646EBIH9_PHY_FIFO_WE 0x100
+#define K4B2G1646EBIH9_PHY_WR_DATA 0xC1
+#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
+
/**
* Configure DMM
*/
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
index a950ac3c18..8f9315c020 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h
@@ -29,6 +29,7 @@
/* Control Module Base Address */
#define CTRL_BASE 0x48140000
+#define CTRL_DEVICE_BASE 0x48140600
/* PRCM Base Address */
#define PRCM_BASE 0x48180000
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index d28f9a83ff..7e3bb9c994 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -35,29 +35,4 @@
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000
#endif
-
-/* ROM code defines */
-/* Boot device */
-#define BOOT_DEVICE_MASK 0xFF
-#define BOOT_DEVICE_OFFSET 0x8
-#define DEV_DESC_PTR_OFFSET 0x4
-#define DEV_DATA_PTR_OFFSET 0x18
-#define BOOT_MODE_OFFSET 0x8
-#define RESET_REASON_OFFSET 0x9
-#define CH_FLAGS_OFFSET 0xA
-
-#define CH_FLAGS_CHSETTINGS (0x1 << 0)
-#define CH_FLAGS_CHRAM (0x1 << 1)
-#define CH_FLAGS_CHFLASH (0x1 << 2)
-#define CH_FLAGS_CHMMCSD (0x1 << 3)
-
-#ifndef __ASSEMBLY__
-struct omap_boot_parameters {
- char *boot_message;
- unsigned int mem_boot_descriptor;
- unsigned char omap_bootdevice;
- unsigned char reset_reason;
- unsigned char ch_flags;
-};
-#endif
#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h
index 8282f46199..584393572c 100644
--- a/arch/arm/include/asm/arch-at91/at91_common.h
+++ b/arch/arm/include/asm/arch-at91/at91_common.h
@@ -35,5 +35,6 @@ void at91_seriald_hw_init(void);
void at91_spi0_hw_init(unsigned long cs_mask);
void at91_spi1_hw_init(unsigned long cs_mask);
void at91_uhp_hw_init(void);
+void at91_lcd_hw_init(void);
#endif /* AT91_COMMON_H */
diff --git a/arch/arm/include/asm/arch-at91/at91_dbu.h b/arch/arm/include/asm/arch-at91/at91_dbu.h
index 3429293535..9a640a5b04 100644
--- a/arch/arm/include/asm/arch-at91/at91_dbu.h
+++ b/arch/arm/include/asm/arch-at91/at91_dbu.h
@@ -38,4 +38,8 @@ typedef struct at91_dbu {
#define AT91_DBU_CID_ARCH_9xx 0x01900000
#define AT91_DBU_CID_ARCH_9XExx 0x02900000
+#define AT91_DBU_CIDR_MASK 0x1f
+#define AT91_DBU_CIDR 0x40
+#define AT91_DBU_EXID 0x44
+
#endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h
index 086cb9b34e..66075b4807 100644
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ b/arch/arm/include/asm/arch-at91/at91_pmc.h
@@ -55,7 +55,16 @@ typedef struct at91_pmc {
u32 reserved5[21];
u32 wpmr; /* 0xE4 Write Protect Mode Register (CAP0) */
u32 wpsr; /* 0xE8 Write Protect Status Register (CAP0) */
+#ifdef CONFIG_SAMA5D3
+ u32 reserved6[8];
+ u32 pcer1; /* 0x100 Periperial Clock Enable Register 1 */
+ u32 pcdr1; /* 0x104 Periperial Clock Disable Register 1 */
+ u32 pcsr1; /* 0x108 Periperial Clock Status Register 1 */
+ u32 pcr; /* 0x10c Periperial Control Register */
+ u32 ocr; /* 0x110 Oscillator Calibration Register */
+#else
u32 reserved8[5];
+#endif
} at91_pmc_t;
#endif /* end not assembly */
@@ -82,6 +91,16 @@ typedef struct at91_pmc {
#define AT91_PMC_MCKR_CSS_PLLB 0x00000003
#define AT91_PMC_MCKR_CSS_MASK 0x00000003
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_MCKR_PRES_1 0x00000000
+#define AT91_PMC_MCKR_PRES_2 0x00000010
+#define AT91_PMC_MCKR_PRES_4 0x00000020
+#define AT91_PMC_MCKR_PRES_8 0x00000030
+#define AT91_PMC_MCKR_PRES_16 0x00000040
+#define AT91_PMC_MCKR_PRES_32 0x00000050
+#define AT91_PMC_MCKR_PRES_64 0x00000060
+#define AT91_PMC_MCKR_PRES_MASK 0x00000070
+#else
#define AT91_PMC_MCKR_PRES_1 0x00000000
#define AT91_PMC_MCKR_PRES_2 0x00000004
#define AT91_PMC_MCKR_PRES_4 0x00000008
@@ -90,6 +109,7 @@ typedef struct at91_pmc {
#define AT91_PMC_MCKR_PRES_32 0x00000014
#define AT91_PMC_MCKR_PRES_64 0x00000018
#define AT91_PMC_MCKR_PRES_MASK 0x0000001C
+#endif
#ifdef CONFIG_AT91RM9200
#define AT91_PMC_MCKR_MDIV_1 0x00000000
@@ -100,6 +120,9 @@ typedef struct at91_pmc {
#else
#define AT91_PMC_MCKR_MDIV_1 0x00000000
#define AT91_PMC_MCKR_MDIV_2 0x00000100
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_MCKR_MDIV_3 0x00000300
+#endif
#define AT91_PMC_MCKR_MDIV_4 0x00000200
#define AT91_PMC_MCKR_MDIV_MASK 0x00000300
#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
index b9a93b0c8f..6e0bebd1bb 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
@@ -23,7 +23,7 @@
#include <asm/arch/at91cap9_matrix.h>
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#include <asm/arch/at91sam9g45_matrix.h>
-#elif defined(CONFIG_AT91SAM9X5)
+#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
#include <asm/arch/at91sam9x5_matrix.h>
#else
#error "Unsupported AT91SAM9/CAP9 processor"
diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h
index b7d1932f42..85e42f582b 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9x5.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h
@@ -1,10 +1,10 @@
/*
* Chip-specific header file for the AT91SAM9x5 family
*
- * Copyright (C) 2012 Atmel Corporation.
+ * Copyright (C) 2012-2013 Atmel Corporation.
*
* Definitions for the SoC:
- * AT91SAM9x5
+ * AT91SAM9x5 & AT91SAM9N12
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,10 +22,12 @@
#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
#define ATMEL_ID_PIOAB 2 /* Parallel I/O Controller A and B */
#define ATMEL_ID_PIOCD 3 /* Parallel I/O Controller C and D */
-#define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD) */
+#define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD), only for AT91SAM9X5 */
+#define ATMEL_ID_FUSE 4 /* FUSE Controller, only for AT91SAM9N12 */
#define ATMEL_ID_USART0 5 /* USART 0 */
#define ATMEL_ID_USART1 6 /* USART 1 */
#define ATMEL_ID_USART2 7 /* USART 2 */
+#define ATMEL_ID_USART3 8 /* USART 3 */
#define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
#define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */
#define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */
@@ -46,6 +48,7 @@
#define ATMEL_ID_HSMCI1 26 /* High Speed Multimedia Card Interface 1 */
#define ATMEL_ID_EMAC1 27 /* Ethernet MAC1 */
#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */
+#define ATMEL_ID_TRNG 30 /* True Random Number Generator */
#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */
/*
@@ -85,6 +88,7 @@
/*
* System Peripherals
*/
+#define ATMEL_BASE_FUSE 0xffffdc00
#define ATMEL_BASE_MATRIX 0xffffde00
#define ATMEL_BASE_PMECC 0xffffe000
#define ATMEL_BASE_PMERRLOC 0xffffe600
@@ -111,10 +115,15 @@
*/
#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
+
+#ifdef CONFIG_AT91SAM9N12
+#define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller */
+#else /* AT91SAM9X5 */
#define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */
#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
+#endif
/* 9x5 series chip id definitions */
#define ARCH_ID_AT91SAM9X5 0x819a05a0
@@ -140,7 +149,11 @@
/*
* Cpu Name
*/
+#ifdef CONFIG_AT91SAM9N12
+#define ATMEL_CPU_NAME "AT91SAM9N12"
+#else /* AT91SAM9X5 */
#define ATMEL_CPU_NAME get_cpu_name()
+#endif
/*
* Other misc defines
diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
index d6ce6fad55..0d33069441 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h
@@ -1,10 +1,10 @@
/*
* Matrix-centric header file for the AT91SAM9X5 family
*
- * Copyright (C) 2012 Atmel Corporation.
+ * Copyright (C) 2012-2013 Atmel Corporation.
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91SAM9X5 preliminary datasheet.
+ * Based on AT91SAM9X5 & AT91SAM9N12 preliminary datasheet.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,14 +17,25 @@
#ifndef __ASSEMBLY__
+/* AT91SAM9N12 Matrix definition is a subset of AT91SAM9X5. */
struct at91_matrix {
u32 mcfg[16];
u32 scfg[16];
u32 pras[16][2];
u32 mrcr; /* 0x100 Master Remap Control */
- u32 filler[7];
+ u32 filler[5];
+#ifdef CONFIG_AT91SAM9X5
+ u32 filler1[2];
+#endif
+ /* EBI Chip Select Assignment Register
+ * 0x118: AT91SAM9N12
+ * 0x120: AT91SAM9X5
+ */
u32 ebicsa;
u32 filler4[47];
+#ifdef CONFIG_AT91SAM9N12
+ u32 filler5[2];
+#endif
u32 wpmr;
u32 wpsr;
};
diff --git a/arch/arm/include/asm/arch-at91/clk.h b/arch/arm/include/asm/arch-at91/clk.h
index d4852a38c1..04b0f8322c 100644
--- a/arch/arm/include/asm/arch-at91/clk.h
+++ b/arch/arm/include/asm/arch-at91/clk.h
@@ -95,4 +95,5 @@ static inline unsigned long get_mci_clk_rate(void)
}
int at91_clock_init(unsigned long main_clock);
+void at91_periph_clk_enable(int id);
#endif /* __ASM_ARM_ARCH_CLK_H__ */
diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h
index 4c4ee703a6..b04641e014 100644
--- a/arch/arm/include/asm/arch-at91/hardware.h
+++ b/arch/arm/include/asm/arch-at91/hardware.h
@@ -37,12 +37,14 @@
# include <asm/arch/at91sam9rl.h>
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
# include <asm/arch/at91sam9g45.h>
-#elif defined(CONFIG_AT91SAM9X5)
+#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
# include <asm/arch/at91sam9x5.h>
#elif defined(CONFIG_AT91CAP9)
# include <asm/arch/at91cap9.h>
#elif defined(CONFIG_AT91X40)
# include <asm/arch/at91x40.h>
+#elif defined(CONFIG_SAMA5D3)
+# include <asm/arch/sama5d3.h>
#else
# error "Unsupported AT91 processor"
#endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h
new file mode 100644
index 0000000000..883b932da7
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/sama5d3.h
@@ -0,0 +1,212 @@
+/*
+ * Chip-specific header file for the SAMA5D3 family
+ *
+ * (C) 2012 - 2013 Atmel Corporation.
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * Definitions for the SoC:
+ * SAMA5D3
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef SAMA5D3_H
+#define SAMA5D3_H
+
+/*
+ * defines to be used in other places
+ */
+#define CONFIG_ARMV7 /* ARM A5 Core */
+#define CONFIG_AT91FAMILY /* it's a member of AT91 */
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
+#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
+#define ATMEL_ID_DBGU 2 /* Debug Unit Interrupt */
+#define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */
+#define ATMEL_ID_WDT 4 /* Watchdog timer Interrupt */
+#define ATMEL_ID_SMC 5 /* Multi-bit ECC Interrupt */
+#define ATMEL_ID_PIOA 6 /* Parallel I/O Controller A */
+#define ATMEL_ID_PIOB 7 /* Parallel I/O Controller B */
+#define ATMEL_ID_PIOC 8 /* Parallel I/O Controller C */
+#define ATMEL_ID_PIOD 9 /* Parallel I/O Controller D */
+#define ATMEL_ID_PIOE 10 /* Parallel I/O Controller E */
+#define ATMEL_ID_SMD 11 /* SMD Soft Modem */
+#define ATMEL_ID_USART0 12 /* USART 0 */
+#define ATMEL_ID_USART1 13 /* USART 1 */
+#define ATMEL_ID_USART2 14 /* USART 2 */
+#define ATMEL_ID_USART3 15 /* USART 3 */
+#define ATMEL_ID_UART0 16
+#define ATMEL_ID_UART1 17
+#define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
+#define ATMEL_ID_TWI1 19 /* Two-Wire Interface 1 */
+#define ATMEL_ID_TWI2 20 /* Two-Wire Interface 2 */
+#define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */
+#define ATMEL_ID_MCI1 22 /* */
+#define ATMEL_ID_MCI2 23 /* */
+#define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */
+#define ATMEL_ID_SPI1 25 /* Serial Peripheral Interface 1 */
+#define ATMEL_ID_TC0 26 /* */
+#define ATMEL_ID_TC1 27 /* */
+#define ATMEL_ID_PWMC 28 /* Pulse Width Modulation Controller */
+#define ATMEL_ID_TSC 29 /* Touch Screen ADC Controller */
+#define ATMEL_ID_DMA0 30 /* DMA Controller */
+#define ATMEL_ID_DMA1 31 /* DMA Controller */
+#define ATMEL_ID_UHPHS 32 /* USB Host High Speed */
+#define ATMEL_ID_UDPHS 33 /* USB Device High Speed */
+#define ATMEL_ID_GMAC 34
+#define ATMEL_ID_EMAC 35 /* Ethernet MAC */
+#define ATMEL_ID_LCDC 36 /* LCD Controller */
+#define ATMEL_ID_ISI 37 /* Image Sensor Interface */
+#define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */
+#define ATMEL_ID_SSC1 39 /* Synchronous Serial Controller 1 */
+#define ATMEL_ID_CAN0 40
+#define ATMEL_ID_CAN1 41
+#define ATMEL_ID_SHA 42
+#define ATMEL_ID_AES 43
+#define ATMEL_ID_TDES 44
+#define ATMEL_ID_TRNG 45
+#define ATMEL_ID_ARM 46
+#define ATMEL_ID_IRQ0 47 /* Advanced Interrupt Controller */
+#define ATMEL_ID_FUSE 48
+#define ATMEL_ID_MPDDRC 49
+
+/* sama5d3 series chip id definitions */
+#define ARCH_ID_SAMA5D3 0x8a5c07c0
+#define ARCH_EXID_SAMA5D31 0x00444300
+#define ARCH_EXID_SAMA5D33 0x00414300
+#define ARCH_EXID_SAMA5D34 0x00414301
+#define ARCH_EXID_SAMA5D35 0x00584300
+
+#define cpu_is_sama5d3() (get_chip_id() == ARCH_ID_SAMA5D3)
+#define cpu_is_sama5d31() (cpu_is_sama5d3() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D31))
+#define cpu_is_sama5d33() (cpu_is_sama5d3() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D33))
+#define cpu_is_sama5d34() (cpu_is_sama5d3() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D34))
+#define cpu_is_sama5d35() (cpu_is_sama5d3() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA5D35))
+
+/*
+ * User Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_MCI0 0xf0000000
+#define ATMEL_BASE_SPI0 0xf0004000
+#define ATMEL_BASE_SSC0 0xf000C000
+#define ATMEL_BASE_TC2 0xf0010000
+#define ATMEL_BASE_TWI0 0xf0014000
+#define ATMEL_BASE_TWI1 0xf0018000
+#define ATMEL_BASE_USART0 0xf001c000
+#define ATMEL_BASE_USART1 0xf0020000
+#define ATMEL_BASE_UART0 0xf0024000
+#define ATMEL_BASE_GMAC 0xf0028000
+#define ATMEL_BASE_PWMC 0xf002c000
+#define ATMEL_BASE_LCDC 0xf0030000
+#define ATMEL_BASE_ISI 0xf0034000
+#define ATMEL_BASE_SFR 0xf0038000
+/* Reserved: 0xf003c000 - 0xf8000000 */
+#define ATMEL_BASE_MCI1 0xf8000000
+#define ATMEL_BASE_MCI2 0xf8004000
+#define ATMEL_BASE_SPI1 0xf8008000
+#define ATMEL_BASE_SSC1 0xf800c000
+#define ATMEL_BASE_CAN1 0xf8010000
+#define ATMEL_BASE_TC3 0xf8014000
+#define ATMEL_BASE_TSADC 0xf8018000
+#define ATMEL_BASE_TWI2 0xf801c000
+#define ATMEL_BASE_USART2 0xf8020000
+#define ATMEL_BASE_USART3 0xf8024000
+#define ATMEL_BASE_UART1 0xf8028000
+#define ATMEL_BASE_EMAC 0xf802c000
+#define ATMEL_BASE_UDHPS 0xf8030000
+#define ATMEL_BASE_SHA 0xf8034000
+#define ATMEL_BASE_AES 0xf8038000
+#define ATMEL_BASE_TDES 0xf803c000
+#define ATMEL_BASE_TRNG 0xf8040000
+/* Reserved: 0xf804400 - 0xffffc00 */
+
+/*
+ * System Peripherals physical base addresses.
+ */
+#define ATMEL_BASE_SYS 0xffffc000
+#define ATMEL_BASE_SMC 0xffffc000
+#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
+#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
+#define ATMEL_BASE_FUSE 0xffffe400
+#define ATMEL_BASE_DMAC0 0xffffe600
+#define ATMEL_BASE_DMAC1 0xffffe800
+#define ATMEL_BASE_MPDDRC 0xffffea00
+#define ATMEL_BASE_MATRIX 0xffffec00
+#define ATMEL_BASE_DBGU 0xffffee00
+#define ATMEL_BASE_AIC 0xfffff000
+#define ATMEL_BASE_PIOA 0xfffff200
+#define ATMEL_BASE_PIOB 0xfffff400
+#define ATMEL_BASE_PIOC 0xfffff600
+#define ATMEL_BASE_PIOD 0xfffff800
+#define ATMEL_BASE_PIOE 0xfffffa00
+#define ATMEL_BASE_PMC 0xfffffc00
+#define ATMEL_BASE_RSTC 0xfffffe00
+#define ATMEL_BASE_SHDWN 0xfffffe10
+#define ATMEL_BASE_PIT 0xfffffe30
+#define ATMEL_BASE_WDT 0xfffffe40
+#define ATMEL_BASE_SCKCR 0xfffffe50
+#define ATMEL_BASE_GPBR 0xfffffe60
+#define ATMEL_BASE_RTC 0xfffffeb0
+/* Reserved: 0xfffffee0 - 0xffffffff */
+
+/*
+ * Internal Memory.
+ */
+#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
+#define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */
+#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM base address */
+#define ATMEL_BASE_SRAM1 0x00310000 /* Internal SRAM base address */
+#define ATMEL_BASE_SMD 0x00400000 /* Internal ROM base address */
+#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
+#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
+#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
+#define ATMEL_BASE_AXI 0x00800000 /* Video Decoder Controller */
+#define ATMEL_BASE_DAP 0x00900000 /* Video Decoder Controller */
+
+/*
+ * External memory
+ */
+#define ATMEL_BASE_CS0 0x10000000
+#define ATMEL_BASE_DDRCS 0x20000000
+#define ATMEL_BASE_CS1 0x40000000
+#define ATMEL_BASE_CS2 0x50000000
+#define ATMEL_BASE_CS3 0x60000000
+
+/*
+ * Other misc defines
+ */
+#define ATMEL_PIO_PORTS 5
+#define CPU_HAS_PIO3
+#define PIO_SCDR_DIV 0x3fff
+
+/*
+ * PMECC table in ROM
+ */
+#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000
+#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000
+#define ATMEL_PMECC_ALPHA_OFFSET_512 0x10000
+#define ATMEL_PMECC_ALPHA_OFFSET_1024 0x18000
+
+/*
+ * SAMA5D3 specific prototypes
+ */
+#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
+unsigned int has_emac(void);
+unsigned int has_gmac(void);
+unsigned int has_lcdc(void);
+char *get_cpu_name(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d3_smc.h b/arch/arm/include/asm/arch-at91/sama5d3_smc.h
new file mode 100644
index 0000000000..eb53eba97f
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/sama5d3_smc.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Static Memory Controllers (SMC) - System peripherals registers.
+ * Based on SAMA5D3 datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef SAMA5D3_SMC_H
+#define SAMA5D3_SMC_H
+
+#ifdef __ASSEMBLY__
+#define AT91_ASM_SMC_SETUP0 (ATMEL_BASE_SMC + 0x600)
+#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x604)
+#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x608)
+#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x60C)
+#else
+struct at91_cs {
+ u32 reserved[96];
+ u32 setup; /* 0x600 SMC Setup Register */
+ u32 pulse; /* 0x604 SMC Pulse Register */
+ u32 cycle; /* 0x608 SMC Cycle Register */
+ u32 timings; /* 0x60C SMC Cycle Register */
+ u32 mode; /* 0x610 SMC Mode Register */
+};
+
+struct at91_smc {
+ struct at91_cs cs[4];
+};
+#endif /* __ASSEMBLY__ */
+
+#define AT91_SMC_SETUP_NWE(x) (x & 0x3f)
+#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8)
+#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16)
+#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24)
+
+#define AT91_SMC_PULSE_NWE(x) (x & 0x3f)
+#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x3f) << 8)
+#define AT91_SMC_PULSE_NRD(x) ((x & 0x3f) << 16)
+#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x3f) << 24)
+
+#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff)
+#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16)
+
+#define AT91_SMC_TIMINGS_TCLR(x) (x & 0xf)
+#define AT91_SMC_TIMINGS_TADL(x) ((x & 0xf) << 4)
+#define AT91_SMC_TIMINGS_TAR(x) ((x & 0xf) << 8)
+#define AT91_SMC_TIMINGS_OCMS(x) ((x & 0x1) << 12)
+#define AT91_SMC_TIMINGS_TRR(x) ((x & 0xf) << 16)
+#define AT91_SMC_TIMINGS_TWB(x) ((x & 0xf) << 24)
+#define AT91_SMC_TIMINGS_RBNSEL(x) ((x & 0xf) << 28)
+#define AT91_SMC_TIMINGS_NFSEL(x) ((x & 0x1) << 31)
+
+#define AT91_SMC_MODE_RM_NCS 0x00000000
+#define AT91_SMC_MODE_RM_NRD 0x00000001
+#define AT91_SMC_MODE_WM_NCS 0x00000000
+#define AT91_SMC_MODE_WM_NWE 0x00000002
+
+#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000
+#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020
+#define AT91_SMC_MODE_EXNW_READY 0x00000030
+
+#define AT91_SMC_MODE_BAT 0x00000100
+#define AT91_SMC_MODE_DBW_8 0x00000000
+#define AT91_SMC_MODE_DBW_16 0x00001000
+#define AT91_SMC_MODE_DBW_32 0x00002000
+#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16)
+#define AT91_SMC_MODE_TDF 0x00100000
+#define AT91_SMC_MODE_PMEN 0x01000000
+#define AT91_SMC_MODE_PS_4 0x00000000
+#define AT91_SMC_MODE_PS_8 0x10000000
+#define AT91_SMC_MODE_PS_16 0x20000000
+#define AT91_SMC_MODE_PS_32 0x30000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 6eed6c95a7..a9017e4683 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -346,6 +346,8 @@ void davinci_errata_workarounds(void);
#define PSC_PSC0_MODULE_ID_CNT 16
#define PSC_PSC1_MODULE_ID_CNT 32
+#define UART0_PWREMU_MGMT (0x01c42030)
+
struct davinci_psc_regs {
dv_reg revid;
dv_reg rsvd0[71];
diff --git a/arch/arm/include/asm/arch-davinci/nand_defs.h b/arch/arm/include/asm/arch-davinci/nand_defs.h
index 10f3a392ab..4a30813808 100644
--- a/arch/arm/include/asm/arch-davinci/nand_defs.h
+++ b/arch/arm/include/asm/arch-davinci/nand_defs.h
@@ -36,6 +36,15 @@
#define MASK_ALE 0x08
#endif
+#ifdef CONFIG_SYS_NAND_MASK_CLE
+#undef MASK_CLE
+#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
+#endif
+#ifdef CONFIG_SYS_NAND_MASK_ALE
+#undef MASK_ALE
+#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
+#endif
+
#define NAND_READ_START 0x00
#define NAND_READ_END 0x30
#define NAND_STATUS 0x70
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 5f4b543823..46f59d7652 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -113,8 +113,12 @@ struct iim_regs {
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
- u32 res1[0x1f5];
+ u32 iim_prg_p;
+ u32 iim_scs0;
+ u32 iim_scs1;
+ u32 iim_scs2;
+ u32 iim_scs3;
+ u32 res1[0x1f1];
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
@@ -122,10 +126,19 @@ struct iim_regs {
};
struct fuse_bank0_regs {
- u32 fuse0_25[0x1a];
+ u32 fuse0_7[8];
+ u32 uid[8];
+ u32 fuse16_25[0xa];
u32 mac_addr[6];
};
+struct fuse_bank1_regs {
+ u32 fuse0_21[0x16];
+ u32 usr5;
+ u32 fuse23_29[7];
+ u32 usr6[2];
+};
+
/* Multi-Layer AHB Crossbar Switch (MAX) registers */
struct max_regs {
u32 mpr0;
@@ -187,6 +200,7 @@ struct aips_regs {
#define IMX_CSPI1_BASE (0x43FA4000)
#define IMX_KPP_BASE (0x43FA8000)
#define IMX_IOPADMUX_BASE (0x43FAC000)
+#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE
#define IMX_IOPADCTL_BASE (0x43FAC22C)
#define IMX_IOPADGRPCTL_BASE (0x43FAC418)
#define IMX_IOPADINPUTSEL_BASE (0x43FAC460)
@@ -240,6 +254,7 @@ struct aips_regs {
#define IMX_PWM1_BASE (0x53FE0000)
#define IMX_RTIC_BASE (0x53FEC000)
#define IMX_IIM_BASE (0x53FF0000)
+#define IIM_BASE_ADDR IMX_IIM_BASE
#define IMX_USB_BASE (0x53FF4000)
#define IMX_USB_PORT_OFFSET 0x200
#define IMX_CSI_BASE (0x53FF8000)
diff --git a/arch/arm/include/asm/arch-mx25/imx25-pinmux.h b/arch/arm/include/asm/arch-mx25/imx25-pinmux.h
deleted file mode 100644
index a4c658b41b..0000000000
--- a/arch/arm/include/asm/arch-mx25/imx25-pinmux.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * iopin settings are controlled by four different sets of registers
- * iopad mux control
- * individual iopad setup (voltage select, pull/keep, drive strength ...)
- * group iopad setup (same as above but for groups of signals)
- * input select when multiple inputs are possible
- */
-
-/*
- * software pad mux control
- */
-/* SW Input On (Loopback) */
-#define MX25_PIN_MUX_SION (1 << 4)
-/* MUX Mode (0-7) */
-#define MX25_PIN_MUX_MODE(mode) ((mode & 0x7) << 0)
-struct iomuxc_mux_ctl {
- u32 gpr1;
- u32 observe_int_mux;
- u32 pad_a10;
- u32 pad_a13;
- u32 pad_a14;
- u32 pad_a15;
- u32 pad_a16;
- u32 pad_a17;
- u32 pad_a18;
- u32 pad_a19;
- u32 pad_a20;
- u32 pad_a21;
- u32 pad_a22;
- u32 pad_a23;
- u32 pad_a24;
- u32 pad_a25;
- u32 pad_eb0;
- u32 pad_eb1;
- u32 pad_oe;
- u32 pad_cs0;
- u32 pad_cs1;
- u32 pad_cs4;
- u32 pad_cs5;
- u32 pad_nf_ce0;
- u32 pad_ecb;
- u32 pad_lba;
- u32 pad_bclk;
- u32 pad_rw;
- u32 pad_nfwe_b;
- u32 pad_nfre_b;
- u32 pad_nfale;
- u32 pad_nfcle;
- u32 pad_nfwp_b;
- u32 pad_nfrb;
- u32 pad_d15;
- u32 pad_d14;
- u32 pad_d13;
- u32 pad_d12;
- u32 pad_d11;
- u32 pad_d10;
- u32 pad_d9;
- u32 pad_d8;
- u32 pad_d7;
- u32 pad_d6;
- u32 pad_d5;
- u32 pad_d4;
- u32 pad_d3;
- u32 pad_d2;
- u32 pad_d1;
- u32 pad_d0;
- u32 pad_ld0;
- u32 pad_ld1;
- u32 pad_ld2;
- u32 pad_ld3;
- u32 pad_ld4;
- u32 pad_ld5;
- u32 pad_ld6;
- u32 pad_ld7;
- u32 pad_ld8;
- u32 pad_ld9;
- u32 pad_ld10;
- u32 pad_ld11;
- u32 pad_ld12;
- u32 pad_ld13;
- u32 pad_ld14;
- u32 pad_ld15;
- u32 pad_hsync;
- u32 pad_vsync;
- u32 pad_lsclk;
- u32 pad_oe_acd;
- u32 pad_contrast;
- u32 pad_pwm;
- u32 pad_csi_d2;
- u32 pad_csi_d3;
- u32 pad_csi_d4;
- u32 pad_csi_d5;
- u32 pad_csi_d6;
- u32 pad_csi_d7;
- u32 pad_csi_d8;
- u32 pad_csi_d9;
- u32 pad_csi_mclk;
- u32 pad_csi_vsync;
- u32 pad_csi_hsync;
- u32 pad_csi_pixclk;
- u32 pad_i2c1_clk;
- u32 pad_i2c1_dat;
- u32 pad_cspi1_mosi;
- u32 pad_cspi1_miso;
- u32 pad_cspi1_ss0;
- u32 pad_cspi1_ss1;
- u32 pad_cspi1_sclk;
- u32 pad_cspi1_rdy;
- u32 pad_uart1_rxd;
- u32 pad_uart1_txd;
- u32 pad_uart1_rts;
- u32 pad_uart1_cts;
- u32 pad_uart2_rxd;
- u32 pad_uart2_txd;
- u32 pad_uart2_rts;
- u32 pad_uart2_cts;
- u32 pad_sd1_cmd;
- u32 pad_sd1_clk;
- u32 pad_sd1_data0;
- u32 pad_sd1_data1;
- u32 pad_sd1_data2;
- u32 pad_sd1_data3;
- u32 pad_kpp_row0;
- u32 pad_kpp_row1;
- u32 pad_kpp_row2;
- u32 pad_kpp_row3;
- u32 pad_kpp_col0;
- u32 pad_kpp_col1;
- u32 pad_kpp_col2;
- u32 pad_kpp_col3;
- u32 pad_fec_mdc;
- u32 pad_fec_mdio;
- u32 pad_fec_tdata0;
- u32 pad_fec_tdata1;
- u32 pad_fec_tx_en;
- u32 pad_fec_rdata0;
- u32 pad_fec_rdata1;
- u32 pad_fec_rx_dv;
- u32 pad_fec_tx_clk;
- u32 pad_rtck;
- u32 pad_de_b;
- u32 pad_gpio_a;
- u32 pad_gpio_b;
- u32 pad_gpio_c;
- u32 pad_gpio_d;
- u32 pad_gpio_e;
- u32 pad_gpio_f;
- u32 pad_ext_armclk;
- u32 pad_upll_bypclk;
- u32 pad_vstby_req;
- u32 pad_vstby_ack;
- u32 pad_power_fail;
- u32 pad_clko;
- u32 pad_boot_mode0;
- u32 pad_boot_mode1;
-};
-
-/*
- * software pad control
- */
-/* Select 3.3 or 1.8 volts */
-#define MX25_PIN_PAD_CTL_DVS_33 (0 << 13)
-#define MX25_PIN_PAD_CTL_DVS_18 (1 << 13)
-/* Enable hysteresis */
-#define MX25_PIN_PAD_CTL_HYS (1 << 8)
-/* Enable pull/keeper */
-#define MX25_PIN_PAD_CTL_PKE (1 << 7)
-/* 0 - keeper / 1 - pull */
-#define MX25_PIN_PAD_CTL_PUE (1 << 6)
-/* pull up/down strength */
-#define MX25_PIN_PAD_CTL_100K_PD (0 << 4)
-#define MX25_PIN_PAD_CTL_47K_PU (1 << 4)
-#define MX25_PIN_PAD_CTL_100K_PU (2 << 4)
-#define MX25_PIN_PAD_CTL_22K_PU (3 << 4)
-/* open drain control */
-#define MX25_PIN_PAD_CTL_OD (1 << 3)
-/* drive strength */
-#define MX25_PIN_PAD_CTL_DS_NOM (0 << 1)
-#define MX25_PIN_PAD_CTL_DS_HIGH (1 << 1)
-#define MX25_PIN_PAD_CTL_DS_MAX (2 << 1)
-#define MX25_PIN_PAD_CTL_DS_MAX11 (3 << 1)
-/* slew rate */
-#define MX25_PIN_PAD_CTL_SRE_SLOW (0 << 0)
-#define MX25_PIN_PAD_CTL_SRE_FAST (1 << 0)
-struct iomuxc_pad_ctl {
- u32 pad_a13;
- u32 pad_a14;
- u32 pad_a15;
- u32 pad_a17;
- u32 pad_a18;
- u32 pad_a19;
- u32 pad_a20;
- u32 pad_a21;
- u32 pad_a23;
- u32 pad_a24;
- u32 pad_a25;
- u32 pad_eb0;
- u32 pad_eb1;
- u32 pad_oe;
- u32 pad_cs4;
- u32 pad_cs5;
- u32 pad_nf_ce0;
- u32 pad_ecb;
- u32 pad_lba;
- u32 pad_rw;
- u32 pad_nfrb;
- u32 pad_d15;
- u32 pad_d14;
- u32 pad_d13;
- u32 pad_d12;
- u32 pad_d11;
- u32 pad_d10;
- u32 pad_d9;
- u32 pad_d8;
- u32 pad_d7;
- u32 pad_d6;
- u32 pad_d5;
- u32 pad_d4;
- u32 pad_d3;
- u32 pad_d2;
- u32 pad_d1;
- u32 pad_d0;
- u32 pad_ld0;
- u32 pad_ld1;
- u32 pad_ld2;
- u32 pad_ld3;
- u32 pad_ld4;
- u32 pad_ld5;
- u32 pad_ld6;
- u32 pad_ld7;
- u32 pad_ld8;
- u32 pad_ld9;
- u32 pad_ld10;
- u32 pad_ld11;
- u32 pad_ld12;
- u32 pad_ld13;
- u32 pad_ld14;
- u32 pad_ld15;
- u32 pad_hsync;
- u32 pad_vsync;
- u32 pad_lsclk;
- u32 pad_oe_acd;
- u32 pad_contrast;
- u32 pad_pwm;
- u32 pad_csi_d2;
- u32 pad_csi_d3;
- u32 pad_csi_d4;
- u32 pad_csi_d5;
- u32 pad_csi_d6;
- u32 pad_csi_d7;
- u32 pad_csi_d8;
- u32 pad_csi_d9;
- u32 pad_csi_mclk;
- u32 pad_csi_vsync;
- u32 pad_csi_hsync;
- u32 pad_csi_pixclk;
- u32 pad_i2c1_clk;
- u32 pad_i2c1_dat;
- u32 pad_cspi1_mosi;
- u32 pad_cspi1_miso;
- u32 pad_cspi1_ss0;
- u32 pad_cspi1_ss1;
- u32 pad_cspi1_sclk;
- u32 pad_cspi1_rdy;
- u32 pad_uart1_rxd;
- u32 pad_uart1_txd;
- u32 pad_uart1_rts;
- u32 pad_uart1_cts;
- u32 pad_uart2_rxd;
- u32 pad_uart2_txd;
- u32 pad_uart2_rts;
- u32 pad_uart2_cts;
- u32 pad_sd1_cmd;
- u32 pad_sd1_clk;
- u32 pad_sd1_data0;
- u32 pad_sd1_data1;
- u32 pad_sd1_data2;
- u32 pad_sd1_data3;
- u32 pad_kpp_row0;
- u32 pad_kpp_row1;
- u32 pad_kpp_row2;
- u32 pad_kpp_row3;
- u32 pad_kpp_col0;
- u32 pad_kpp_col1;
- u32 pad_kpp_col2;
- u32 pad_kpp_col3;
- u32 pad_fec_mdc;
- u32 pad_fec_mdio;
- u32 pad_fec_tdata0;
- u32 pad_fec_tdata1;
- u32 pad_fec_tx_en;
- u32 pad_fec_rdata0;
- u32 pad_fec_rdata1;
- u32 pad_fec_rx_dv;
- u32 pad_fec_tx_clk;
- u32 pad_rtck;
- u32 pad_tdo;
- u32 pad_de_b;
- u32 pad_gpio_a;
- u32 pad_gpio_b;
- u32 pad_gpio_c;
- u32 pad_gpio_d;
- u32 pad_gpio_e;
- u32 pad_gpio_f;
- u32 pad_vstby_req;
- u32 pad_vstby_ack;
- u32 pad_power_fail;
- u32 pad_clko;
-};
-
-
-/*
- * Pad group drive strength and voltage select
- * Same fields as iomuxc_pad_ctl plus ddr type
- */
-/* Select DDR type */
-#define MX25_PIN_PAD_CTL_DDR_18 (0 << 11)
-#define MX25_PIN_PAD_CTL_DDR_33 (1 << 11)
-#define MX25_PIN_PAD_CTL_DDR_MAX (2 << 11)
-struct iomuxc_pad_grp_ctl {
- u32 grp_dvs_misc;
- u32 grp_dse_fec;
- u32 grp_dvs_jtag;
- u32 grp_dse_nfc;
- u32 grp_dse_csi;
- u32 grp_dse_weim;
- u32 grp_dse_ddr;
- u32 grp_dvs_crm;
- u32 grp_dse_kpp;
- u32 grp_dse_sdhc1;
- u32 grp_dse_lcd;
- u32 grp_dse_uart;
- u32 grp_dvs_nfc;
- u32 grp_dvs_csi;
- u32 grp_dse_cspi1;
- u32 grp_ddrtype;
- u32 grp_dvs_sdhc1;
- u32 grp_dvs_lcd;
-};
-
-/*
- * Pad input select control
- * Select which pad to connect to an input port
- * where multiple pads can function as given input
- */
-#define MX25_PAD_INPUT_SELECT_DAISY(in) ((in & 0x7) << 0)
-struct iomuxc_pad_input_select {
- u32 audmux_p4_input_da_amx;
- u32 audmux_p4_input_db_amx;
- u32 audmux_p4_input_rxclk_amx;
- u32 audmux_p4_input_rxfs_amx;
- u32 audmux_p4_input_txclk_amx;
- u32 audmux_p4_input_txfs_amx;
- u32 audmux_p7_input_da_amx;
- u32 audmux_p7_input_txfs_amx;
- u32 can1_ipp_ind_canrx;
- u32 can2_ipp_ind_canrx;
- u32 csi_ipp_csi_d_0;
- u32 csi_ipp_csi_d_1;
- u32 cspi1_ipp_ind_ss3_b;
- u32 cspi2_ipp_cspi_clk_in;
- u32 cspi2_ipp_ind_dataready_b;
- u32 cspi2_ipp_ind_miso;
- u32 cspi2_ipp_ind_mosi;
- u32 cspi2_ipp_ind_ss0_b;
- u32 cspi2_ipp_ind_ss1_b;
- u32 cspi3_ipp_cspi_clk_in;
- u32 cspi3_ipp_ind_dataready_b;
- u32 cspi3_ipp_ind_miso;
- u32 cspi3_ipp_ind_mosi;
- u32 cspi3_ipp_ind_ss0_b;
- u32 cspi3_ipp_ind_ss1_b;
- u32 cspi3_ipp_ind_ss2_b;
- u32 cspi3_ipp_ind_ss3_b;
- u32 esdhc1_ipp_dat4_in;
- u32 esdhc1_ipp_dat5_in;
- u32 esdhc1_ipp_dat6_in;
- u32 esdhc1_ipp_dat7_in;
- u32 esdhc2_ipp_card_clk_in;
- u32 esdhc2_ipp_cmd_in;
- u32 esdhc2_ipp_dat0_in;
- u32 esdhc2_ipp_dat1_in;
- u32 esdhc2_ipp_dat2_in;
- u32 esdhc2_ipp_dat3_in;
- u32 esdhc2_ipp_dat4_in;
- u32 esdhc2_ipp_dat5_in;
- u32 esdhc2_ipp_dat6_in;
- u32 esdhc2_ipp_dat7_in;
- u32 fec_fec_col;
- u32 fec_fec_crs;
- u32 fec_fec_rdata_2;
- u32 fec_fec_rdata_3;
- u32 fec_fec_rx_clk;
- u32 fec_fec_rx_er;
- u32 i2c2_ipp_scl_in;
- u32 i2c2_ipp_sda_in;
- u32 i2c3_ipp_scl_in;
- u32 i2c3_ipp_sda_in;
- u32 kpp_ipp_ind_col_4;
- u32 kpp_ipp_ind_col_5;
- u32 kpp_ipp_ind_col_6;
- u32 kpp_ipp_ind_col_7;
- u32 kpp_ipp_ind_row_4;
- u32 kpp_ipp_ind_row_5;
- u32 kpp_ipp_ind_row_6;
- u32 kpp_ipp_ind_row_7;
- u32 sim1_pin_sim_rcvd1_in;
- u32 sim1_pin_sim_simpd1;
- u32 sim1_sim_rcvd1_io;
- u32 sim2_pin_sim_rcvd1_in;
- u32 sim2_pin_sim_simpd1;
- u32 sim2_sim_rcvd1_io;
- u32 uart3_ipp_uart_rts_b;
- u32 uart3_ipp_uart_rxd_mux;
- u32 uart4_ipp_uart_rts_b;
- u32 uart4_ipp_uart_rxd_mux;
- u32 uart5_ipp_uart_rts_b;
- u32 uart5_ipp_uart_rxd_mux;
- u32 usb_top_ipp_ind_otg_usb_oc;
- u32 usb_top_ipp_ind_uh2_usb_oc;
-};
diff --git a/arch/arm/include/asm/arch-mx25/iomux-mx25.h b/arch/arm/include/asm/arch-mx25/iomux-mx25.h
new file mode 100644
index 0000000000..c0f5c613ec
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx25/iomux-mx25.h
@@ -0,0 +1,545 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on mainline Linux i.MX iomux-mx25.h file:
+ * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
+ *
+ * Based on Linux arch/arm/mach-mx25/mx25_pins.h:
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_MX25_H__
+#define __IOMUX_MX25_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP
+#define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+/*
+ * The naming convention for the pad modes is MX25_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/* PAD MUX ALT INPSE PATH PADCTRL */
+enum {
+ MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTRL),
+ MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTRL),
+
+ MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTRL),
+
+ MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL),
+ MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL),
+ MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CS1__CS1 = IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL),
+ MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL),
+ MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL),
+ MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE),
+ MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_D15__GPIO_4_5 = IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D14__D14 = IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D14__LD17 = IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_D14__GPIO_4_6 = IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D13__D13 = IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D13__LD18 = IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_D13__GPIO_4_7 = IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D12__D12 = IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D12__GPIO_4_8 = IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D11__D11 = IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D11__GPIO_4_9 = IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D10__D10 = IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D10__GPIO_4_10 = IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP),
+
+ MX25_PAD_D9__D9 = IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D9__GPIO_4_11 = IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE),
+
+ MX25_PAD_D8__D8 = IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D8__GPIO_4_12 = IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP),
+
+ MX25_PAD_D7__D7 = IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D7__GPIO_4_13 = IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D6__D6 = IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D6__GPIO_4_14 = IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D5__D5 = IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D5__GPIO_4_15 = IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D4__D4 = IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D4__GPIO_4_16 = IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D3__D3 = IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D3__GPIO_4_17 = IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D2__D2 = IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D2__GPIO_4_18 = IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D1__D1 = IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D1__GPIO_4_19 = IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL),
+ MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL),
+ MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTRL),
+
+ MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTRL),
+
+ MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTRL),
+
+ MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTRL),
+
+ MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTRL),
+
+ MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL),
+
+ MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP),
+
+ MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL),
+ MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x17, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x17, 0x4b4, 1, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL),
+ MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x17, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x17, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x11, 0x528, 1, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE),
+ MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN),
+ MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL),
+ MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL),
+ MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTRL),
+ MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTRL),
+ MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+ MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTRL),
+ MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+ MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTRL),
+ MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+ MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+ MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL),
+ MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+ MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTRL),
+ MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
+ MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL),
+ MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+ MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+ MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+ MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL),
+ MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, MX25_KPP_ROW_PAD_CTRL),
+ MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL),
+ MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+ MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL),
+ MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+ MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+ MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, MX25_KPP_COL_PAD_CTRL),
+ MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PUS_100K_UP),
+ MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL),
+ MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
+ MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL),
+ MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL),
+ MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP),
+ MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
+ MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
+ MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE),
+
+ MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP),
+ MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP),
+
+ MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP),
+
+ MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP),
+
+ MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
+ MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x11, 0x524, 2, NO_PAD_CTRL),
+ MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL),
+ MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_BOOT_MODE1__BOOT_MODE1 = IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_BOOT_MODE1__GPIO_4_31 = IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL),
+
+ MX25_PAD_CTL_GRP_DVS_MISC = IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_FEC = IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DVS_JTAG = IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_NFC = IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_CSI = IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_WEIM = IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_DDR = IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DVS_CRM = IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_KPP = IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_SDHC1 = IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_LCD = IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_UART = IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DVS_NFC = IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DVS_CSI = IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DSE_CSPI1 = IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DDRTYPE = IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DVS_SDHC1 = IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL),
+ MX25_PAD_CTL_GRP_DVS_LCD = IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX25_H__ */
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
index 2f6c823722..8867e9f3f5 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -176,7 +176,7 @@ struct iim_regs {
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
+ u32 iim_prg_p;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
@@ -222,6 +222,7 @@ struct fuse_bank0_regs {
#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
+#define IIM_BASE_ADDR IMX_IIM_BASE
#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
#define IMX_ESD_BASE (0xD8001000)
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 3f58318b02..67fddac83a 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -68,7 +68,7 @@ struct cspi_regs {
u32 test;
};
-/* IIM Control Registers */
+/* IIM control registers */
struct iim_regs {
u32 iim_stat;
u32 iim_statm;
@@ -80,11 +80,28 @@ struct iim_regs {
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
+ u32 iim_prg_p;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
+ u32 res[0x1f1];
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ u32 fuse_rsvd[0xe0];
+ } bank[3];
+};
+
+struct fuse_bank0_regs {
+ u32 fuse0_5[6];
+ u32 usr;
+ u32 fuse7_15[9];
+};
+
+struct fuse_bank2_regs {
+ u32 fuse0;
+ u32 uid[8];
+ u32 fuse9_15[7];
};
struct iomuxc_regs {
@@ -557,6 +574,7 @@ struct esdc_regs {
#define CCMR_CKIH (2 << 1)
#define MX31_IIM_BASE_ADDR 0x5001C000
+#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26)
#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23)
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
index 7f337be557..63c6e24b1e 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -262,11 +262,28 @@ struct iim_regs {
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
+ u32 iim_prg_p;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
+ u32 res1[0x1f1];
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ u32 fuse_rsvd[0xe0];
+ } bank[3];
+};
+
+struct fuse_bank0_regs {
+ u32 fuse0_7[8];
+ u32 uid[8];
+ u32 fuse16_31[0x10];
+};
+
+struct fuse_bank1_regs {
+ u32 fuse0_21[0x16];
+ u32 usr;
+ u32 fuse23_31[9];
};
/* General Purpose Timer (GPT) registers */
diff --git a/arch/arm/include/asm/arch-mx35/iomux-mx35.h b/arch/arm/include/asm/arch-mx35/iomux-mx35.h
new file mode 100644
index 0000000000..8016cb356a
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/iomux-mx35.h
@@ -0,0 +1,1276 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on mainline Linux i.MX iomux-mx35.h file:
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_MX35_H__
+#define __IOMUX_MX35_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/*
+ * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/* PAD MUX ALT INPSE PATH PADCTRL */
+enum {
+ MX35_PAD_CAPTURE__GPT_CAPIN1 = IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CAPTURE__GPT_CMPOUT2 = IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CAPTURE__CSPI2_SS1 = IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL),
+ MX35_PAD_CAPTURE__EPIT1_EPITO = IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CAPTURE__CCM_CLK32K = IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL),
+ MX35_PAD_CAPTURE__GPIO1_4 = IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL),
+
+ MX35_PAD_COMPARE__GPT_CMPOUT1 = IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_COMPARE__GPT_CAPIN2 = IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_COMPARE__GPT_CMPOUT3 = IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_COMPARE__EPIT2_EPITO = IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_COMPARE__GPIO1_5 = IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL),
+ MX35_PAD_COMPARE__SDMA_EXTDMA_2 = IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_WDOG_RST__WDOG_WDOG_B = IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_WDOG_RST__IPU_FLASH_STROBE = IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_WDOG_RST__GPIO1_6 = IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL),
+
+ MX35_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_0__CCM_PMIC_RDY = IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_0__OWIRE_LINE = IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 = IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_GPIO1_1__GPIO1_1 = IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_1__PWM_PWMO = IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_1__CSPI1_SS2 = IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT = IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 = IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_GPIO2_0__GPIO2_0 = IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK = IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_GPIO3_0__GPIO3_0 = IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL),
+ MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK = IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RESET_IN_B__CCM_RESET_IN_B = IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_POR_B__CCM_POR_B = IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CLKO__CCM_CLKO = IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CLKO__GPIO1_8 = IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL),
+
+ MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 = IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 = IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 = IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 = IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 = IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_VSTBY__CCM_VSTBY = IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_VSTBY__GPIO1_7 = IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A0__EMI_EIM_DA_L_0 = IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A1__EMI_EIM_DA_L_1 = IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A2__EMI_EIM_DA_L_2 = IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A3__EMI_EIM_DA_L_3 = IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A4__EMI_EIM_DA_L_4 = IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A5__EMI_EIM_DA_L_5 = IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A6__EMI_EIM_DA_L_6 = IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A7__EMI_EIM_DA_L_7 = IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A8__EMI_EIM_DA_H_8 = IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A9__EMI_EIM_DA_H_9 = IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A10__EMI_EIM_DA_H_10 = IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_MA10__EMI_MA10 = IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A11__EMI_EIM_DA_H_11 = IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A12__EMI_EIM_DA_H_12 = IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A13__EMI_EIM_DA_H_13 = IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A14__EMI_EIM_DA_H2_14 = IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A15__EMI_EIM_DA_H2_15 = IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A16__EMI_EIM_A_16 = IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A17__EMI_EIM_A_17 = IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A18__EMI_EIM_A_18 = IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A19__EMI_EIM_A_19 = IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A20__EMI_EIM_A_20 = IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A21__EMI_EIM_A_21 = IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A22__EMI_EIM_A_22 = IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A23__EMI_EIM_A_23 = IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A24__EMI_EIM_A_24 = IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_A25__EMI_EIM_A_25 = IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDBA1__EMI_EIM_SDBA1 = IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDBA0__EMI_EIM_SDBA0 = IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD0__EMI_DRAM_D_0 = IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1__EMI_DRAM_D_1 = IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD2__EMI_DRAM_D_2 = IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD3__EMI_DRAM_D_3 = IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD4__EMI_DRAM_D_4 = IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD5__EMI_DRAM_D_5 = IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD6__EMI_DRAM_D_6 = IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD7__EMI_DRAM_D_7 = IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD8__EMI_DRAM_D_8 = IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD9__EMI_DRAM_D_9 = IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD10__EMI_DRAM_D_10 = IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD11__EMI_DRAM_D_11 = IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD12__EMI_DRAM_D_12 = IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD13__EMI_DRAM_D_13 = IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD14__EMI_DRAM_D_14 = IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD15__EMI_DRAM_D_15 = IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD16__EMI_DRAM_D_16 = IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD17__EMI_DRAM_D_17 = IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD18__EMI_DRAM_D_18 = IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD19__EMI_DRAM_D_19 = IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD20__EMI_DRAM_D_20 = IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD21__EMI_DRAM_D_21 = IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD22__EMI_DRAM_D_22 = IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD23__EMI_DRAM_D_23 = IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD24__EMI_DRAM_D_24 = IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD25__EMI_DRAM_D_25 = IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD26__EMI_DRAM_D_26 = IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD27__EMI_DRAM_D_27 = IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD28__EMI_DRAM_D_28 = IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD29__EMI_DRAM_D_29 = IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD30__EMI_DRAM_D_30 = IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD31__EMI_DRAM_D_31 = IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_DQM0__EMI_DRAM_DQM_0 = IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_DQM1__EMI_DRAM_DQM_1 = IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_DQM2__EMI_DRAM_DQM_2 = IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_DQM3__EMI_DRAM_DQM_3 = IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_EB0__EMI_EIM_EB0_B = IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_EB1__EMI_EIM_EB1_B = IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_OE__EMI_EIM_OE = IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CS0__EMI_EIM_CS0 = IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CS1__EMI_EIM_CS1 = IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CS1__EMI_NANDF_CE3 = IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CS2__EMI_EIM_CS2 = IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CS3__EMI_EIM_CS3 = IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CS4__EMI_EIM_CS4 = IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CS4__EMI_DTACK_B = IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL),
+ MX35_PAD_CS4__EMI_NANDF_CE1 = IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CS4__GPIO1_20 = IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CS5__EMI_EIM_CS5 = IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CS5__CSPI2_SS2 = IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL),
+ MX35_PAD_CS5__CSPI1_SS2 = IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL),
+ MX35_PAD_CS5__EMI_NANDF_CE2 = IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CS5__GPIO1_21 = IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NF_CE0__EMI_NANDF_CE0 = IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NF_CE0__GPIO1_22 = IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ECB__EMI_EIM_ECB = IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LBA__EMI_EIM_LBA = IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_BCLK__EMI_EIM_BCLK = IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RW__EMI_EIM_RW = IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RAS__EMI_DRAM_RAS = IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CAS__EMI_DRAM_CAS = IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDWE__EMI_DRAM_SDWE = IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 = IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 = IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDCLK__EMI_DRAM_SDCLK = IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 = IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 = IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 = IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 = IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NFWE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWE_B__GPIO2_18 = IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 = IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NFRE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR = IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRE_B__IPU_DISPB_BCLK = IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRE_B__GPIO2_19 = IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 = IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NFALE__EMI_NANDF_ALE = IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFALE__USB_TOP_USBH2_STP = IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFALE__IPU_DISPB_CS0 = IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFALE__GPIO2_20 = IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL),
+ MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 = IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NFCLE__EMI_NANDF_CLE = IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFCLE__USB_TOP_USBH2_NXT = IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFCLE__IPU_DISPB_PAR_RS = IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFCLE__GPIO2_21 = IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL),
+ MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 = IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NFWP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWP_B__IPU_DISPB_WR = IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWP_B__GPIO2_22 = IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL = IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_NFRB__EMI_NANDF_RB = IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRB__IPU_DISPB_RD = IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRB__GPIO2_23 = IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL),
+ MX35_PAD_NFRB__ARM11P_TOP_TRCLK = IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D15__EMI_EIM_D_15 = IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D14__EMI_EIM_D_14 = IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D13__EMI_EIM_D_13 = IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D12__EMI_EIM_D_12 = IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D11__EMI_EIM_D_11 = IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D10__EMI_EIM_D_10 = IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D9__EMI_EIM_D_9 = IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D8__EMI_EIM_D_8 = IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D7__EMI_EIM_D_7 = IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D6__EMI_EIM_D_6 = IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D5__EMI_EIM_D_5 = IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D4__EMI_EIM_D_4 = IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3__EMI_EIM_D_3 = IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D2__EMI_EIM_D_2 = IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D1__EMI_EIM_D_1 = IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D0__EMI_EIM_D_0 = IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D8__IPU_CSI_D_8 = IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D8__KPP_COL_0 = IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D8__GPIO1_20 = IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL),
+ MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 = IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D9__IPU_CSI_D_9 = IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D9__KPP_COL_1 = IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D9__GPIO1_21 = IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL),
+ MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 = IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D10__IPU_CSI_D_10 = IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D10__KPP_COL_2 = IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D10__GPIO1_22 = IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL),
+ MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 = IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D11__IPU_CSI_D_11 = IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D11__KPP_COL_3 = IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D11__GPIO1_23 = IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D12__IPU_CSI_D_12 = IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D12__KPP_ROW_0 = IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D12__GPIO1_24 = IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D13__IPU_CSI_D_13 = IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D13__KPP_ROW_1 = IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D13__GPIO1_25 = IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D14__IPU_CSI_D_14 = IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D14__KPP_ROW_2 = IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D14__GPIO1_26 = IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_D15__IPU_CSI_D_15 = IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D15__KPP_ROW_3 = IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_D15__GPIO1_27 = IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_MCLK__IPU_CSI_MCLK = IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_MCLK__GPIO1_28 = IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC = IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_VSYNC__GPIO1_29 = IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC = IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_HSYNC__GPIO1_30 = IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK = IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSI_PIXCLK__GPIO1_31 = IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_I2C1_CLK__I2C1_SCL = IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C1_CLK__GPIO2_24 = IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK = IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_I2C1_DAT__I2C1_SDA = IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C1_DAT__GPIO2_25 = IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL),
+
+ MX35_PAD_I2C2_CLK__I2C2_SCL = IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_CLK__CAN1_TXCAN = IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR = IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_CLK__GPIO2_26 = IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_I2C2_DAT__I2C2_SDA = IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_DAT__CAN1_RXCAN = IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC = IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_DAT__GPIO2_27 = IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL),
+ MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_STXD4__AUDMUX_AUD4_TXD = IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_STXD4__GPIO2_28 = IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL),
+ MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 = IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SRXD4__AUDMUX_AUD4_RXD = IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SRXD4__GPIO2_29 = IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL),
+ MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 = IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SCK4__AUDMUX_AUD4_TXC = IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SCK4__GPIO2_30 = IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL),
+ MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 = IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_STXFS4__GPIO2_31 = IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL),
+ MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 = IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_STXD5__AUDMUX_AUD5_TXD = IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_STXD5__CSPI2_MOSI = IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL),
+ MX35_PAD_STXD5__GPIO1_0 = IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL),
+ MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 = IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SRXD5__AUDMUX_AUD5_RXD = IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL),
+ MX35_PAD_SRXD5__CSPI2_MISO = IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL),
+ MX35_PAD_SRXD5__GPIO1_1 = IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL),
+ MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 = IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SCK5__AUDMUX_AUD5_TXC = IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL),
+ MX35_PAD_SCK5__CSPI2_SCLK = IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL),
+ MX35_PAD_SCK5__GPIO1_2 = IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL),
+ MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 = IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_STXFS5__CSPI2_RDY = IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL),
+ MX35_PAD_STXFS5__GPIO1_3 = IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL),
+ MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 = IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SCKR__ESAI_SCKR = IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SCKR__GPIO1_4 = IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL),
+ MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 = IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FSR__ESAI_FSR = IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FSR__GPIO1_5 = IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL),
+ MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 = IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_HCKR__ESAI_HCKR = IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKR__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKR__CSPI2_SS0 = IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKR__IPU_FLASH_STROBE = IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKR__GPIO1_6 = IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL),
+ MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 = IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SCKT__ESAI_SCKT = IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SCKT__GPIO1_7 = IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL),
+ MX35_PAD_SCKT__IPU_CSI_D_0 = IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL),
+ MX35_PAD_SCKT__KPP_ROW_2 = IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL),
+
+ MX35_PAD_FST__ESAI_FST = IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FST__GPIO1_8 = IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL),
+ MX35_PAD_FST__IPU_CSI_D_1 = IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL),
+ MX35_PAD_FST__KPP_ROW_3 = IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL),
+
+ MX35_PAD_HCKT__ESAI_HCKT = IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKT__AUDMUX_AUD5_RXC = IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKT__GPIO1_9 = IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKT__IPU_CSI_D_2 = IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL),
+ MX35_PAD_HCKT__KPP_COL_3 = IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL),
+
+ MX35_PAD_TX5_RX0__ESAI_TX5_RX0 = IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC = IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX5_RX0__CSPI2_SS2 = IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL),
+ MX35_PAD_TX5_RX0__CAN2_TXCAN = IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX5_RX0__UART2_DTR = IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX5_RX0__GPIO1_10 = IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL),
+ MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 = IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TX4_RX1__ESAI_TX4_RX1 = IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__CSPI2_SS3 = IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__CAN2_RXCAN = IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__UART2_DSR = IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__GPIO1_11 = IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__IPU_CSI_D_3 = IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL),
+ MX35_PAD_TX4_RX1__KPP_ROW_0 = IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL),
+
+ MX35_PAD_TX3_RX2__ESAI_TX3_RX2 = IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX3_RX2__I2C3_SCL = IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL),
+ MX35_PAD_TX3_RX2__EMI_NANDF_CE1 = IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX3_RX2__GPIO1_12 = IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX3_RX2__IPU_CSI_D_4 = IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL),
+ MX35_PAD_TX3_RX2__KPP_ROW_1 = IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL),
+
+ MX35_PAD_TX2_RX3__ESAI_TX2_RX3 = IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX2_RX3__I2C3_SDA = IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL),
+ MX35_PAD_TX2_RX3__EMI_NANDF_CE2 = IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX2_RX3__GPIO1_13 = IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX2_RX3__IPU_CSI_D_5 = IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL),
+ MX35_PAD_TX2_RX3__KPP_COL_0 = IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL),
+
+ MX35_PAD_TX1__ESAI_TX1 = IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX1__CCM_PMIC_RDY = IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL),
+ MX35_PAD_TX1__CSPI1_SS2 = IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL),
+ MX35_PAD_TX1__EMI_NANDF_CE3 = IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX1__UART2_RI = IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX1__GPIO1_14 = IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX1__IPU_CSI_D_6 = IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL),
+ MX35_PAD_TX1__KPP_COL_1 = IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL),
+
+ MX35_PAD_TX0__ESAI_TX0 = IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL),
+ MX35_PAD_TX0__CSPI1_SS3 = IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL),
+ MX35_PAD_TX0__EMI_DTACK_B = IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL),
+ MX35_PAD_TX0__UART2_DCD = IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX0__GPIO1_15 = IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TX0__IPU_CSI_D_7 = IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL),
+ MX35_PAD_TX0__KPP_COL_2 = IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL),
+
+ MX35_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_MOSI__GPIO1_16 = IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 = IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_MISO__GPIO1_17 = IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 = IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS0__OWIRE_LINE = IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS0__CSPI2_SS3 = IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS0__GPIO1_18 = IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 = IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS1__PWM_PWMO = IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS1__CCM_CLK32K = IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS1__GPIO1_19 = IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 = IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 = IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SCLK__GPIO3_4 = IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 = IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 = IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY = IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 = IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 = IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 = IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RXD1__UART1_RXD_MUX = IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_RXD1__CSPI2_MOSI = IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL),
+ MX35_PAD_RXD1__KPP_COL_4 = IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL),
+ MX35_PAD_RXD1__GPIO3_6 = IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL),
+ MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 = IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TXD1__UART1_TXD_MUX = IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TXD1__CSPI2_MISO = IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL),
+ MX35_PAD_TXD1__KPP_COL_5 = IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL),
+ MX35_PAD_TXD1__GPIO3_7 = IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL),
+ MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 = IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RTS1__UART1_RTS = IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS1__CSPI2_SCLK = IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL),
+ MX35_PAD_RTS1__I2C3_SCL = IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL),
+ MX35_PAD_RTS1__IPU_CSI_D_0 = IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL),
+ MX35_PAD_RTS1__KPP_COL_6 = IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS1__GPIO3_8 = IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS1__EMI_NANDF_CE1 = IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 = IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CTS1__UART1_CTS = IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS1__CSPI2_RDY = IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL),
+ MX35_PAD_CTS1__I2C3_SDA = IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL),
+ MX35_PAD_CTS1__IPU_CSI_D_1 = IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL),
+ MX35_PAD_CTS1__KPP_COL_7 = IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS1__GPIO3_9 = IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS1__EMI_NANDF_CE2 = IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 = IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RXD2__UART2_RXD_MUX = IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_RXD2__KPP_ROW_4 = IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL),
+ MX35_PAD_RXD2__GPIO3_10 = IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TXD2__UART2_TXD_MUX = IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL),
+ MX35_PAD_TXD2__KPP_ROW_5 = IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL),
+ MX35_PAD_TXD2__GPIO3_11 = IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RTS2__UART2_RTS = IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS2__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL),
+ MX35_PAD_RTS2__CAN2_RXCAN = IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL),
+ MX35_PAD_RTS2__IPU_CSI_D_2 = IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL),
+ MX35_PAD_RTS2__KPP_ROW_6 = IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS2__GPIO3_12 = IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS2__AUDMUX_AUD5_RXC = IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_RTS2__UART3_RXD_MUX = IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CTS2__UART2_CTS = IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS2__CAN2_TXCAN = IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS2__IPU_CSI_D_3 = IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL),
+ MX35_PAD_CTS2__KPP_ROW_7 = IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS2__GPIO3_13 = IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS2__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CTS2__UART3_TXD_MUX = IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_RTCK__ARM11P_TOP_RTCK = IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TCK__SJC_TCK = IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TMS__SJC_TMS = IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TDI__SJC_TDI = IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TDO__SJC_TDO = IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TRSTB__SJC_TRSTB = IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_DE_B__SJC_DE_B = IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SJC_MOD__SJC_MOD = IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR = IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR = IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_USBOTG_PWR__GPIO3_14 = IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL),
+
+ MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC = IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC = IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL),
+ MX35_PAD_USBOTG_OC__GPIO3_15 = IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD0__IPU_DISPB_DAT_0 = IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD0__GPIO2_0 = IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL),
+ MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 = IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD1__IPU_DISPB_DAT_1 = IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD1__GPIO2_1 = IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL),
+ MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 = IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD2__IPU_DISPB_DAT_2 = IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD2__GPIO2_2 = IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 = IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD3__IPU_DISPB_DAT_3 = IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD3__GPIO2_3 = IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL),
+ MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 = IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD4__IPU_DISPB_DAT_4 = IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD4__GPIO2_4 = IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 = IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD5__IPU_DISPB_DAT_5 = IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD5__GPIO2_5 = IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL),
+ MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 = IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD6__IPU_DISPB_DAT_6 = IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD6__GPIO2_6 = IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL),
+ MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 = IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD7__IPU_DISPB_DAT_7 = IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD7__GPIO2_7 = IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL),
+ MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 = IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD8__IPU_DISPB_DAT_8 = IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD8__GPIO2_8 = IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 = IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD9__IPU_DISPB_DAT_9 = IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD9__GPIO2_9 = IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL),
+ MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 = IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD10__IPU_DISPB_DAT_10 = IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD10__GPIO2_10 = IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL),
+ MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 = IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD11__IPU_DISPB_DAT_11 = IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD11__GPIO2_11 = IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL),
+ MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 = IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD11__ARM11P_TOP_TRACE_4 = IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD12__IPU_DISPB_DAT_12 = IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD12__GPIO2_12 = IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL),
+ MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 = IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD12__ARM11P_TOP_TRACE_5 = IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD13__IPU_DISPB_DAT_13 = IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD13__GPIO2_13 = IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL),
+ MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 = IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD13__ARM11P_TOP_TRACE_6 = IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD14__IPU_DISPB_DAT_14 = IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD14__GPIO2_14 = IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL),
+ MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD14__ARM11P_TOP_TRACE_7 = IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD15__IPU_DISPB_DAT_15 = IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD15__GPIO2_15 = IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL),
+ MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD15__ARM11P_TOP_TRACE_8 = IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD16__IPU_DISPB_DAT_16 = IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD16__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL),
+ MX35_PAD_LD16__GPIO2_16 = IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL),
+ MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD16__ARM11P_TOP_TRACE_9 = IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD17__IPU_DISPB_DAT_17 = IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD17__IPU_DISPB_CS2 = IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD17__GPIO2_17 = IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL),
+ MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD17__ARM11P_TOP_TRACE_10 = IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD18__IPU_DISPB_DAT_18 = IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD18__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL),
+ MX35_PAD_LD18__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL),
+ MX35_PAD_LD18__ESDHC3_CMD = IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL),
+ MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD18__GPIO3_24 = IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD18__ARM11P_TOP_TRACE_11 = IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD19__IPU_DISPB_DAT_19 = IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__IPU_DISPB_BCLK = IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__IPU_DISPB_CS1 = IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__ESDHC3_CLK = IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__GPIO3_25 = IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD19__ARM11P_TOP_TRACE_12 = IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD20__IPU_DISPB_DAT_20 = IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD20__IPU_DISPB_CS0 = IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD20__IPU_DISPB_SD_CLK = IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD20__ESDHC3_DAT0 = IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL),
+ MX35_PAD_LD20__GPIO3_26 = IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 = IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD20__ARM11P_TOP_TRACE_13 = IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD21__IPU_DISPB_DAT_21 = IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__IPU_DISPB_PAR_RS = IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__IPU_DISPB_SER_RS = IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__ESDHC3_DAT1 = IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__USB_TOP_USBOTG_STP = IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__GPIO3_27 = IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD21__ARM11P_TOP_TRACE_14 = IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD22__IPU_DISPB_DAT_22 = IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__IPU_DISPB_WR = IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__IPU_DISPB_SD_D_I = IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__ESDHC3_DAT2 = IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__GPIO3_28 = IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD22__ARM11P_TOP_TRCTL = IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_LD23__IPU_DISPB_DAT_23 = IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD23__IPU_DISPB_RD = IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD23__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL),
+ MX35_PAD_LD23__ESDHC3_DAT3 = IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL),
+ MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD23__GPIO3_29 = IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_LD23__ARM11P_TOP_TRCLK = IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC = IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL),
+ MX35_PAD_D3_HSYNC__GPIO3_30 = IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 = IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK = IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK = IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_FPSHIFT__GPIO3_31 = IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 = IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 = IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY = IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O = IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_DRDY__GPIO1_0 = IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL),
+ MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 = IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 = IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_CONTRAST__IPU_DISPB_CONTR = IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CONTRAST__GPIO1_1 = IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL),
+ MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 = IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 = IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC = IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 = IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_VSYNC__GPIO1_2 = IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL),
+ MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD = IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 = IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_REV__IPU_DISPB_D3_REV = IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_REV__IPU_DISPB_SER_RS = IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_REV__GPIO1_3 = IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL),
+ MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 = IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS = IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_CLS__IPU_DISPB_CS2 = IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_CLS__GPIO1_4 = IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL),
+ MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 = IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL = IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL),
+ MX35_PAD_D3_SPL__GPIO1_5 = IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL),
+ MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 = IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CMD__MSHC_SCLK = IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL),
+ MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CMD__GPIO1_6 = IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL),
+ MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL = IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CLK__MSHC_BS = IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CLK__IPU_DISPB_BCLK = IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_CLK__GPIO1_7 = IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL),
+ MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK = IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA0__MSHC_DATA_0 = IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA0__GPIO1_8 = IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 = IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA1__MSHC_DATA_1 = IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS = IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA1__GPIO1_9 = IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 = IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA2__MSHC_DATA_2 = IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA2__IPU_DISPB_WR = IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA2__GPIO1_10 = IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 = IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA3__MSHC_DATA_3 = IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA3__IPU_DISPB_RD = IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA3__GPIO1_11 = IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL),
+ MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 = IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__I2C3_SCL = IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__ESDHC1_DAT4 = IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__IPU_CSI_D_2 = IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__GPIO2_0 = IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL),
+
+ MX35_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__I2C3_SDA = IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__IPU_CSI_D_3 = IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__GPIO2_1 = IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL),
+ MX35_PAD_SD2_CLK__IPU_DISPB_CS2 = IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA0__UART3_RXD_MUX = IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA0__ESDHC1_DAT6 = IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA0__IPU_CSI_D_4 = IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA0__GPIO2_2 = IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL),
+
+ MX35_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA1__UART3_TXD_MUX = IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA1__ESDHC1_DAT7 = IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA1__IPU_CSI_D_5 = IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA1__GPIO2_3 = IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL),
+
+ MX35_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA2__UART3_RTS = IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA2__CAN1_RXCAN = IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA2__IPU_CSI_D_6 = IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA2__GPIO2_4 = IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL),
+
+ MX35_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA3__UART3_CTS = IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA3__CAN1_TXCAN = IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA3__IPU_CSI_D_7 = IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL),
+ MX35_PAD_SD2_DATA3__GPIO2_5 = IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_CS0__ATA_CS0 = IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS0__CSPI1_SS3 = IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS0__IPU_DISPB_CS1 = IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS0__GPIO2_6 = IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS0__IPU_DIAGB_0 = IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 = IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_CS1__ATA_CS1 = IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS1__IPU_DISPB_CS2 = IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS1__CSPI2_SS0 = IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS1__GPIO2_7 = IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS1__IPU_DIAGB_1 = IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 = IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DIOR__ATA_DIOR = IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__ESDHC3_DAT0 = IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR = IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 = IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__CSPI2_SS1 = IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__GPIO2_8 = IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__IPU_DIAGB_2 = IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 = IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DIOW__ATA_DIOW = IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__ESDHC3_DAT1 = IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP = IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 = IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__CSPI2_MOSI = IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__GPIO2_9 = IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__IPU_DIAGB_3 = IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 = IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DMACK__ATA_DMACK = IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMACK__ESDHC3_DAT2 = IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT = IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMACK__CSPI2_MISO = IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMACK__GPIO2_10 = IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMACK__IPU_DIAGB_4 = IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 = IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_RESET_B__ATA_RESET_B = IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 = IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 = IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O = IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__CSPI2_RDY = IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__GPIO2_11 = IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 = IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 = IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_IORDY__ATA_IORDY = IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__ESDHC3_DAT4 = IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 = IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__ESDHC2_DAT4 = IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__GPIO2_12 = IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__IPU_DIAGB_6 = IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 = IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA0__ATA_DATA_0 = IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__ESDHC3_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 = IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__ESDHC2_DAT5 = IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__GPIO2_13 = IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__IPU_DIAGB_7 = IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 = IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA1__ATA_DATA_1 = IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__ESDHC3_DAT6 = IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 = IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK = IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__ESDHC2_DAT6 = IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__GPIO2_14 = IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__IPU_DIAGB_8 = IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 = IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA2__ATA_DATA_2 = IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__ESDHC3_DAT7 = IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 = IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS = IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__ESDHC2_DAT7 = IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__GPIO2_15 = IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__IPU_DIAGB_9 = IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 = IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA3__ATA_DATA_3 = IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA3__ESDHC3_CLK = IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 = IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA3__CSPI2_SCLK = IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA3__GPIO2_16 = IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA3__IPU_DIAGB_10 = IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 = IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA4__ATA_DATA_4 = IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA4__ESDHC3_CMD = IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 = IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA4__GPIO2_17 = IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA4__IPU_DIAGB_11 = IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 = IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA5__ATA_DATA_5 = IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 = IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA5__GPIO2_18 = IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA5__IPU_DIAGB_12 = IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 = IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA6__ATA_DATA_6 = IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA6__CAN1_TXCAN = IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA6__UART1_DTR = IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD = IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA6__GPIO2_19 = IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA6__IPU_DIAGB_13 = IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA7__ATA_DATA_7 = IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA7__CAN1_RXCAN = IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA7__UART1_DSR = IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD = IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA7__GPIO2_20 = IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA7__IPU_DIAGB_14 = IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA8__ATA_DATA_8 = IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA8__UART3_RTS = IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA8__UART1_RI = IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC = IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA8__GPIO2_21 = IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA8__IPU_DIAGB_15 = IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA9__ATA_DATA_9 = IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA9__UART3_CTS = IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA9__UART1_DCD = IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA9__GPIO2_22 = IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA9__IPU_DIAGB_16 = IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA10__ATA_DATA_10 = IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA10__UART3_RXD_MUX = IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC = IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA10__GPIO2_23 = IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA10__IPU_DIAGB_17 = IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA11__ATA_DATA_11 = IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA11__UART3_TXD_MUX = IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA11__GPIO2_24 = IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA11__IPU_DIAGB_18 = IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA12__ATA_DATA_12 = IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA12__I2C3_SCL = IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA12__GPIO2_25 = IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA12__IPU_DIAGB_19 = IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA13__ATA_DATA_13 = IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA13__I2C3_SDA = IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA13__GPIO2_26 = IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA13__IPU_DIAGB_20 = IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA14__ATA_DATA_14 = IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA14__IPU_CSI_D_0 = IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA14__KPP_ROW_0 = IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA14__GPIO2_27 = IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA14__IPU_DIAGB_21 = IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DATA15__ATA_DATA_15 = IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA15__IPU_CSI_D_1 = IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA15__KPP_ROW_1 = IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA15__GPIO2_28 = IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DATA15__IPU_DIAGB_22 = IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_INTRQ__ATA_INTRQ = IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 = IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL),
+ MX35_PAD_ATA_INTRQ__KPP_ROW_2 = IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_INTRQ__GPIO2_29 = IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 = IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN = IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 = IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL),
+ MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 = IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_BUFF_EN__GPIO2_30 = IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 = IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DMARQ__ATA_DMARQ = IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 = IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMARQ__KPP_COL_0 = IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMARQ__GPIO2_31 = IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 = IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 = IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DA0__ATA_DA_0 = IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA0__IPU_CSI_D_5 = IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA0__KPP_COL_1 = IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA0__GPIO3_0 = IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA0__IPU_DIAGB_26 = IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 = IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DA1__ATA_DA_1 = IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA1__IPU_CSI_D_6 = IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA1__KPP_COL_2 = IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA1__GPIO3_1 = IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA1__IPU_DIAGB_27 = IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 = IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_ATA_DA2__ATA_DA_2 = IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA2__IPU_CSI_D_7 = IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA2__KPP_COL_3 = IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA2__GPIO3_2 = IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA2__IPU_DIAGB_28 = IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 = IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_MLB_CLK__MLB_MLBCLK = IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_MLB_CLK__GPIO3_3 = IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_MLB_DAT__MLB_MLBDAT = IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_MLB_DAT__GPIO3_4 = IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL),
+
+ MX35_PAD_MLB_SIG__MLB_MLBSIG = IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_MLB_SIG__GPIO3_5 = IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 = IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX = IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR = IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__CSPI2_MOSI = IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__GPIO3_6 = IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC = IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 = IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK = IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 = IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX = IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP = IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__CSPI2_MISO = IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__GPIO3_7 = IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I = IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 = IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 = IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__UART3_RTS = IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT = IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__CSPI2_SCLK = IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__GPIO3_8 = IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK = IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 = IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_COL__FEC_COL = IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__ESDHC1_DAT7 = IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__UART3_CTS = IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 = IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__CSPI2_RDY = IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__GPIO3_9 = IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__IPU_DISPB_SER_RS = IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 = IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0 = IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__PWM_PWMO = IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__UART3_DTR = IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 = IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__CSPI2_SS0 = IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__GPIO3_10 = IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 = IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 = IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0 = IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 = IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__UART3_DSR = IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 = IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__CSPI2_SS1 = IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__GPIO3_11 = IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 = IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 = IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 = IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_EN__UART3_RI = IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 = IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_EN__GPIO3_12 = IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS = IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 = IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDC__CAN2_TXCAN = IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDC__UART3_DCD = IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 = IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDC__GPIO3_13 = IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDC__IPU_DISPB_WR = IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 = IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDIO__CAN2_RXCAN = IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 = IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDIO__GPIO3_14 = IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDIO__IPU_DISPB_RD = IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 = IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR = IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_ERR__OWIRE_LINE = IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK = IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 = IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_ERR__GPIO3_15 = IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC = IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 = IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR = IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 = IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 = IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_ERR__KPP_COL_4 = IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_ERR__GPIO3_16 = IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO = IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_CRS__FEC_CRS = IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_CRS__IPU_CSI_D_1 = IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR = IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_CRS__KPP_COL_5 = IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_CRS__GPIO3_17 = IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_CRS__IPU_FLASH_STROBE = IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1 = IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 = IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC = IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC = IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA1__KPP_COL_6 = IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA1__GPIO3_18 = IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 = IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1 = IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 = IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS = IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA1__KPP_COL_7 = IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA1__GPIO3_19 = IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 = IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2 = IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 = IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA2__KPP_ROW_4 = IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA2__GPIO3_20 = IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2 = IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 = IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD = IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA2__KPP_ROW_5 = IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA2__GPIO3_21 = IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3 = IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 = IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC = IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA3__KPP_ROW_6 = IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_RDATA3__GPIO3_22 = IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3 = IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 = IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA3__KPP_ROW_7 = IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL),
+ MX35_PAD_FEC_TDATA3__GPIO3_23 = IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK = IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+
+ MX35_PAD_TEST_MODE__TCU_TEST_MODE = IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX35_H__ */
diff --git a/arch/arm/include/asm/arch-mx35/iomux.h b/arch/arm/include/asm/arch-mx35/iomux.h
deleted file mode 100644
index 52c15bc63a..0000000000
--- a/arch/arm/include/asm/arch-mx35/iomux.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MX35_IOMUX_H__
-#define __MACH_MX35_IOMUX_H__
-
-#include <asm/arch/imx-regs.h>
-
-/*
- * various IOMUX functions
- */
-typedef enum iomux_pin_config {
- MUX_CONFIG_FUNC = 0, /* used as function */
- MUX_CONFIG_ALT1, /* used as alternate function 1 */
- MUX_CONFIG_ALT2, /* used as alternate function 2 */
- MUX_CONFIG_ALT3, /* used as alternate function 3 */
- MUX_CONFIG_ALT4, /* used as alternate function 4 */
- MUX_CONFIG_ALT5, /* used as alternate function 5 */
- MUX_CONFIG_ALT6, /* used as alternate function 6 */
- MUX_CONFIG_ALT7, /* used as alternate function 7 */
- MUX_CONFIG_SION = 0x1 << 4, /* used as LOOPBACK:MUX SION bit */
- MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /* used as GPIO */
-} iomux_pin_cfg_t;
-
-/*
- * various IOMUX pad functions
- */
-typedef enum iomux_pad_config {
- PAD_CTL_DRV_3_3V = 0x0 << 13,
- PAD_CTL_DRV_1_8V = 0x1 << 13,
- PAD_CTL_HYS_CMOS = 0x0 << 8,
- PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
- PAD_CTL_PKE_NONE = 0x0 << 7,
- PAD_CTL_PKE_ENABLE = 0x1 << 7,
- PAD_CTL_PUE_KEEPER = 0x0 << 6,
- PAD_CTL_PUE_PUD = 0x1 << 6,
- PAD_CTL_100K_PD = 0x0 << 4,
- PAD_CTL_47K_PU = 0x1 << 4,
- PAD_CTL_100K_PU = 0x2 << 4,
- PAD_CTL_22K_PU = 0x3 << 4,
- PAD_CTL_ODE_CMOS = 0x0 << 3,
- PAD_CTL_ODE_OpenDrain = 0x1 << 3,
- PAD_CTL_DRV_NORMAL = 0x0 << 1,
- PAD_CTL_DRV_HIGH = 0x1 << 1,
- PAD_CTL_DRV_MAX = 0x2 << 1,
- PAD_CTL_SRE_SLOW = 0x0 << 0,
- PAD_CTL_SRE_FAST = 0x1 << 0
-} iomux_pad_config_t;
-
-/*
- * various IOMUX general purpose functions
- */
-typedef enum iomux_gp_func {
- MUX_SDCTL_CSD0_SEL = 0x1 << 0,
- MUX_SDCTL_CSD1_SEL = 0x1 << 1,
- MUX_TAMPER_DETECT_EN = 0x1 << 2,
-} iomux_gp_func_t;
-
-/*
- * various IOMUX input select register index
- */
-typedef enum iomux_input_select {
- MUX_IN_AMX_P5_RXCLK = 0,
- MUX_IN_AMX_P5_RXFS,
- MUX_IN_AMX_P6_DA,
- MUX_IN_AMX_P6_DB,
- MUX_IN_AMX_P6_RXCLK,
- MUX_IN_AMX_P6_RXFS,
- MUX_IN_AMX_P6_TXCLK,
- MUX_IN_AMX_P6_TXFS,
- MUX_IN_CAN1_CANRX,
- MUX_IN_CAN2_CANRX,
- MUX_IN_CCM_32K_MUXED,
- MUX_IN_CCM_PMIC_RDY,
- MUX_IN_CSPI1_SS2_B,
- MUX_IN_CSPI1_SS3_B,
- MUX_IN_CSPI2_CLK_IN,
- MUX_IN_CSPI2_DATAREADY_B,
- MUX_IN_CSPI2_MISO,
- MUX_IN_CSPI2_MOSI,
- MUX_IN_CSPI2_SS0_B,
- MUX_IN_CSPI2_SS1_B,
- MUX_IN_CSPI2_SS2_B,
- MUX_IN_CSPI2_SS3_B,
- MUX_IN_EMI_WEIM_DTACK_B,
- MUX_IN_ESDHC1_DAT4_IN,
- MUX_IN_ESDHC1_DAT5_IN,
- MUX_IN_ESDHC1_DAT6_IN,
- MUX_IN_ESDHC1_DAT7_IN,
- MUX_IN_ESDHC3_CARD_CLK_IN,
- MUX_IN_ESDHC3_CMD_IN,
- MUX_IN_ESDHC3_DAT0,
- MUX_IN_ESDHC3_DAT1,
- MUX_IN_ESDHC3_DAT2,
- MUX_IN_ESDHC3_DAT3,
- MUX_IN_GPIO1_IN_0,
- MUX_IN_GPIO1_IN_10,
- MUX_IN_GPIO1_IN_11,
- MUX_IN_GPIO1_IN_1,
- MUX_IN_GPIO1_IN_20,
- MUX_IN_GPIO1_IN_21,
- MUX_IN_GPIO1_IN_22,
- MUX_IN_GPIO1_IN_2,
- MUX_IN_GPIO1_IN_3,
- MUX_IN_GPIO1_IN_4,
- MUX_IN_GPIO1_IN_5,
- MUX_IN_GPIO1_IN_6,
- MUX_IN_GPIO1_IN_7,
- MUX_IN_GPIO1_IN_8,
- MUX_IN_GPIO1_IN_9,
- MUX_IN_GPIO2_IN_0,
- MUX_IN_GPIO2_IN_10,
- MUX_IN_GPIO2_IN_11,
- MUX_IN_GPIO2_IN_12,
- MUX_IN_GPIO2_IN_13,
- MUX_IN_GPIO2_IN_14,
- MUX_IN_GPIO2_IN_15,
- MUX_IN_GPIO2_IN_16,
- MUX_IN_GPIO2_IN_17,
- MUX_IN_GPIO2_IN_18,
- MUX_IN_GPIO2_IN_19,
- MUX_IN_GPIO2_IN_20,
- MUX_IN_GPIO2_IN_21,
- MUX_IN_GPIO2_IN_22,
- MUX_IN_GPIO2_IN_23,
- MUX_IN_GPIO2_IN_24,
- MUX_IN_GPIO2_IN_25,
- MUX_IN_GPIO2_IN_26,
- MUX_IN_GPIO2_IN_27,
- MUX_IN_GPIO2_IN_28,
- MUX_IN_GPIO2_IN_29,
- MUX_IN_GPIO2_IN_2,
- MUX_IN_GPIO2_IN_30,
- MUX_IN_GPIO2_IN_31,
- MUX_IN_GPIO2_IN_3,
- MUX_IN_GPIO2_IN_4,
- MUX_IN_GPIO2_IN_5,
- MUX_IN_GPIO2_IN_6,
- MUX_IN_GPIO2_IN_7,
- MUX_IN_GPIO2_IN_8,
- MUX_IN_GPIO2_IN_9,
- MUX_IN_GPIO3_IN_0,
- MUX_IN_GPIO3_IN_10,
- MUX_IN_GPIO3_IN_11,
- MUX_IN_GPIO3_IN_12,
- MUX_IN_GPIO3_IN_13,
- MUX_IN_GPIO3_IN_14,
- MUX_IN_GPIO3_IN_15,
- MUX_IN_GPIO3_IN_4,
- MUX_IN_GPIO3_IN_5,
- MUX_IN_GPIO3_IN_6,
- MUX_IN_GPIO3_IN_7,
- MUX_IN_GPIO3_IN_8,
- MUX_IN_GPIO3_IN_9,
- MUX_IN_I2C3_SCL_IN,
- MUX_IN_I2C3_SDA_IN,
- MUX_IN_IPU_DISPB_D0_VSYNC,
- MUX_IN_IPU_DISPB_D12_VSYNC,
- MUX_IN_IPU_DISPB_SD_D,
- MUX_IN_IPU_SENSB_DATA_0,
- MUX_IN_IPU_SENSB_DATA_1,
- MUX_IN_IPU_SENSB_DATA_2,
- MUX_IN_IPU_SENSB_DATA_3,
- MUX_IN_IPU_SENSB_DATA_4,
- MUX_IN_IPU_SENSB_DATA_5,
- MUX_IN_IPU_SENSB_DATA_6,
- MUX_IN_IPU_SENSB_DATA_7,
- MUX_IN_KPP_COL_0,
- MUX_IN_KPP_COL_1,
- MUX_IN_KPP_COL_2,
- MUX_IN_KPP_COL_3,
- MUX_IN_KPP_COL_4,
- MUX_IN_KPP_COL_5,
- MUX_IN_KPP_COL_6,
- MUX_IN_KPP_COL_7,
- MUX_IN_KPP_ROW_0,
- MUX_IN_KPP_ROW_1,
- MUX_IN_KPP_ROW_2,
- MUX_IN_KPP_ROW_3,
- MUX_IN_KPP_ROW_4,
- MUX_IN_KPP_ROW_5,
- MUX_IN_KPP_ROW_6,
- MUX_IN_KPP_ROW_7,
- MUX_IN_OWIRE_BATTERY_LINE,
- MUX_IN_SPDIF_HCKT_CLK2,
- MUX_IN_SPDIF_SPDIF_IN1,
- MUX_IN_UART3_UART_RTS_B,
- MUX_IN_UART3_UART_RXD_MUX,
- MUX_IN_USB_OTG_DATA_0,
- MUX_IN_USB_OTG_DATA_1,
- MUX_IN_USB_OTG_DATA_2,
- MUX_IN_USB_OTG_DATA_3,
- MUX_IN_USB_OTG_DATA_4,
- MUX_IN_USB_OTG_DATA_5,
- MUX_IN_USB_OTG_DATA_6,
- MUX_IN_USB_OTG_DATA_7,
- MUX_IN_USB_OTG_DIR,
- MUX_IN_USB_OTG_NXT,
- MUX_IN_USB_UH2_DATA_0,
- MUX_IN_USB_UH2_DATA_1,
- MUX_IN_USB_UH2_DATA_2,
- MUX_IN_USB_UH2_DATA_3,
- MUX_IN_USB_UH2_DATA_4,
- MUX_IN_USB_UH2_DATA_5,
- MUX_IN_USB_UH2_DATA_6,
- MUX_IN_USB_UH2_DATA_7,
- MUX_IN_USB_UH2_DIR,
- MUX_IN_USB_UH2_NXT,
- MUX_IN_USB_UH2_USB_OC,
-} iomux_input_select_t;
-
-/*
- * various IOMUX input functions
- */
-typedef enum iomux_input_config {
- INPUT_CTL_PATH0 = 0x0,
- INPUT_CTL_PATH1,
- INPUT_CTL_PATH2,
- INPUT_CTL_PATH3,
- INPUT_CTL_PATH4,
- INPUT_CTL_PATH5,
- INPUT_CTL_PATH6,
- INPUT_CTL_PATH7,
-} iomux_input_cfg_t;
-
-/*
- * Request ownership for an IO pin. This function has to be the first one
- * being called before that pin is used. The caller has to check the
- * return value to make sure it returns 0.
- *
- * @param pin a name defined by iomux_pin_name_t
- * @param cfg an input function as defined in iomux_pin_cfg_t
- *
- * @return 0 if successful; Non-zero otherwise
- */
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
-
-/*
- * Release ownership for an IO pin
- *
- * @param pin a name defined by iomux_pin_name_t
- * @param cfg an input function as defined in iomux_pin_cfg_t
- */
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
-
-/*
- * This function enables/disables the general purpose function for a particular
- * signal.
- *
- * @param gp one signal as defined in iomux_gp_func_t
- * @param en 1 to enable; 0 to disable
- */
-void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en);
-
-/*
- * This function configures the pad value for a IOMUX pin.
- *
- * @param pin a pin number as defined in iomux_pin_name_t
- * @param config the ORed value of elements defined in
- * iomux_pad_config_t
- */
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-
-/*
- * This function configures input path.
- *
- * @param input index of input select register as defined in
- * iomux_input_select_t
- * @param config the binary value of elements defined in
- * iomux_input_cfg_t
- */
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-#endif
diff --git a/arch/arm/include/asm/arch-mx35/mx35_pins.h b/arch/arm/include/asm/arch-mx35/mx35_pins.h
deleted file mode 100644
index 00e5e75835..0000000000
--- a/arch/arm/include/asm/arch-mx35/mx35_pins.h
+++ /dev/null
@@ -1,353 +0,0 @@
-/*
- * (C) Copyright 2011
- * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
- *
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MXC_MX35_PINS_H__
-#define __ASM_ARCH_MXC_MX35_PINS_H__
-
-/*!
- * @file arch-mxc/mx35_pins.h
- *
- * @brief MX35 I/O Pin List
- *
- * @ingroup GPIO_MX35
- */
-
-#ifndef __ASSEMBLY__
-
-/*!
- * @name IOMUX/PAD Bit field definitions
- */
-
-/*! @{ */
-
-/*!
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 |23 - 21| 20 - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P | IO_I | RSVD | PAD_I | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 7 contains MUX_I used to identify the register
- * offset (base is IOMUX_module_base ) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The similar field
- * definitions are used for the pad control register.the MX35_PIN_A0 is
- * defined in the enumeration: ( 0x28 << MUX_I) |( 0x368 << PAD_I)
- * So the absolute address is: IOMUX_module_base + 0x28.
- * The pad control register offset is: 0x368.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I 0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I 10
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * reserved filed
- */
-#define RSVD_I 21
-
-#define MUX_IO_P 29
-#define MUX_IO_I 24
-#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
- GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
- ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-
-#define NON_GPIO_I 0x7
-#define PIN_TO_MUX_MASK ((1<<(PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK ((1<<(RSVD_I - PAD_I)) - 1)
-#define NON_MUX_I PIN_TO_MUX_MASK
-
-#define _MXC_BUILD_PIN(gp, gi, mi, pi) \
- (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
- ((mi) << MUX_I) | ((pi) << PAD_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, mi, pi) \
- _MXC_BUILD_PIN(gp, gi, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
- _MXC_BUILD_PIN(NON_GPIO_I, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-
-/*! @} End IOMUX/PAD Bit field definitions */
-
-/*!
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX35 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-typedef enum iomux_pins {
- MX35_PIN_CAPTURE = _MXC_BUILD_GPIO_PIN(0, 4, 0x4, 0x328),
- MX35_PIN_COMPARE = _MXC_BUILD_GPIO_PIN(0, 5, 0x8, 0x32C),
- MX35_PIN_WATCHDOG_RST = _MXC_BUILD_GPIO_PIN(0, 6, 0xC, 0x330),
- MX35_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 0x10, 0x334),
- MX35_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 0x14, 0x338),
- MX35_PIN_GPIO2_0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x18, 0x33C),
- MX35_PIN_GPIO3_0 = _MXC_BUILD_GPIO_PIN(2, 1, 0x1C, 0x340),
- MX35_PIN_CLKO = _MXC_BUILD_GPIO_PIN(0, 8, 0x20, 0x34C),
-
- MX35_PIN_POWER_FAIL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x360),
- MX35_PIN_VSTBY = _MXC_BUILD_GPIO_PIN(0, 7, 0x24, 0x364),
- MX35_PIN_A0 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x368),
- MX35_PIN_A1 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x36C),
- MX35_PIN_A2 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x370),
- MX35_PIN_A3 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x374),
- MX35_PIN_A4 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x378),
- MX35_PIN_A5 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x37C),
- MX35_PIN_A6 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x380),
- MX35_PIN_A7 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x384),
- MX35_PIN_A8 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x388),
- MX35_PIN_A9 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x38C),
- MX35_PIN_A10 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x390),
- MX35_PIN_MA10 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x394),
- MX35_PIN_A11 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x398),
- MX35_PIN_A12 = _MXC_BUILD_NON_GPIO_PIN(0x5C, 0x39C),
- MX35_PIN_A13 = _MXC_BUILD_NON_GPIO_PIN(0x60, 0x3A0),
- MX35_PIN_A14 = _MXC_BUILD_NON_GPIO_PIN(0x64, 0x3A4),
- MX35_PIN_A15 = _MXC_BUILD_NON_GPIO_PIN(0x68, 0x3A8),
- MX35_PIN_A16 = _MXC_BUILD_NON_GPIO_PIN(0x6C, 0x3AC),
- MX35_PIN_A17 = _MXC_BUILD_NON_GPIO_PIN(0x70, 0x3B0),
- MX35_PIN_A18 = _MXC_BUILD_NON_GPIO_PIN(0x74, 0x3B4),
- MX35_PIN_A19 = _MXC_BUILD_NON_GPIO_PIN(0x78, 0x3B8),
- MX35_PIN_A20 = _MXC_BUILD_NON_GPIO_PIN(0x7C, 0x3BC),
- MX35_PIN_A21 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x3C0),
- MX35_PIN_A22 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x3C4),
- MX35_PIN_A23 = _MXC_BUILD_NON_GPIO_PIN(0x88, 0x3C8),
- MX35_PIN_A24 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x3CC),
- MX35_PIN_A25 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x3D0),
-
- MX35_PIN_EB0 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x46C),
- MX35_PIN_EB1 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x470),
- MX35_PIN_OE = _MXC_BUILD_NON_GPIO_PIN(0x9C, 0x474),
- MX35_PIN_CS0 = _MXC_BUILD_NON_GPIO_PIN(0xA0, 0x478),
- MX35_PIN_CS1 = _MXC_BUILD_NON_GPIO_PIN(0xA4, 0x47C),
- MX35_PIN_CS2 = _MXC_BUILD_NON_GPIO_PIN(0xA8, 0x480),
- MX35_PIN_CS3 = _MXC_BUILD_NON_GPIO_PIN(0xAC, 0x484),
- MX35_PIN_CS4 = _MXC_BUILD_GPIO_PIN(0, 20, 0xB0, 0x488),
- MX35_PIN_CS5 = _MXC_BUILD_GPIO_PIN(0, 21, 0xB4, 0x48C),
- MX35_PIN_NFCE_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xB8, 0x490),
-
- MX35_PIN_LBA = _MXC_BUILD_NON_GPIO_PIN(0xBC, 0x498),
- MX35_PIN_BCLK = _MXC_BUILD_NON_GPIO_PIN(0xC0, 0x49C),
- MX35_PIN_RW = _MXC_BUILD_NON_GPIO_PIN(0xC4, 0x4A0),
-
- MX35_PIN_NFWE_B = _MXC_BUILD_GPIO_PIN(0, 18, 0xC8, 0x4CC),
- MX35_PIN_NFRE_B = _MXC_BUILD_GPIO_PIN(0, 19, 0xCC, 0x4D0),
- MX35_PIN_NFALE = _MXC_BUILD_GPIO_PIN(0, 20, 0xD0, 0x4D4),
- MX35_PIN_NFCLE = _MXC_BUILD_GPIO_PIN(0, 21, 0xD4, 0x4D8),
- MX35_PIN_NFWP_B = _MXC_BUILD_GPIO_PIN(0, 22, 0xD8, 0x4DC),
- MX35_PIN_NFRB = _MXC_BUILD_GPIO_PIN(0, 23, 0xDC, 0x4E0),
-
- MX35_PIN_D15 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E4),
- MX35_PIN_D14 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E8),
- MX35_PIN_D13 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4EC),
- MX35_PIN_D12 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F0),
- MX35_PIN_D11 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F4),
- MX35_PIN_D10 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4F8),
- MX35_PIN_D9 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4FC),
- MX35_PIN_D8 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x500),
- MX35_PIN_D7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x504),
- MX35_PIN_D6 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x508),
- MX35_PIN_D5 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x50C),
- MX35_PIN_D4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x510),
- MX35_PIN_D3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x514),
- MX35_PIN_D2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x518),
- MX35_PIN_D1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x51C),
- MX35_PIN_D0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x520),
-
- MX35_PIN_CSI_D8 = _MXC_BUILD_GPIO_PIN(0, 20, 0xE0, 0x524),
- MX35_PIN_CSI_D9 = _MXC_BUILD_GPIO_PIN(0, 21, 0xE4, 0x528),
- MX35_PIN_CSI_D10 = _MXC_BUILD_GPIO_PIN(0, 22, 0xE8, 0x52C),
- MX35_PIN_CSI_D11 = _MXC_BUILD_GPIO_PIN(0, 23, 0xEC, 0x530),
- MX35_PIN_CSI_D12 = _MXC_BUILD_GPIO_PIN(0, 24, 0xF0, 0x534),
- MX35_PIN_CSI_D13 = _MXC_BUILD_GPIO_PIN(0, 25, 0xF4, 0x538),
- MX35_PIN_CSI_D14 = _MXC_BUILD_GPIO_PIN(0, 26, 0xF8, 0x53C),
- MX35_PIN_CSI_D15 = _MXC_BUILD_GPIO_PIN(0, 27, 0xFC, 0x540),
- MX35_PIN_CSI_MCLK = _MXC_BUILD_GPIO_PIN(0, 28, 0x100, 0x544),
- MX35_PIN_CSI_VSYNC = _MXC_BUILD_GPIO_PIN(0, 29, 0x104, 0x548),
- MX35_PIN_CSI_HSYNC = _MXC_BUILD_GPIO_PIN(0, 30, 0x108, 0x54C),
- MX35_PIN_CSI_PIXCLK = _MXC_BUILD_GPIO_PIN(0, 31, 0x10C, 0x550),
-
- MX35_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(1, 24, 0x110, 0x554),
- MX35_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(1, 25, 0x114, 0x558),
- MX35_PIN_I2C2_CLK = _MXC_BUILD_GPIO_PIN(1, 26, 0x118, 0x55C),
- MX35_PIN_I2C2_DAT = _MXC_BUILD_GPIO_PIN(1, 27, 0x11C, 0x560),
-
- MX35_PIN_STXD4 = _MXC_BUILD_GPIO_PIN(1, 28, 0x120, 0x564),
- MX35_PIN_SRXD4 = _MXC_BUILD_GPIO_PIN(1, 29, 0x124, 0x568),
- MX35_PIN_SCK4 = _MXC_BUILD_GPIO_PIN(1, 30, 0x128, 0x56C),
- MX35_PIN_STXFS4 = _MXC_BUILD_GPIO_PIN(1, 31, 0x12C, 0x570),
- MX35_PIN_STXD5 = _MXC_BUILD_GPIO_PIN(0, 0, 0x130, 0x574),
- MX35_PIN_SRXD5 = _MXC_BUILD_GPIO_PIN(0, 1, 0x134, 0x578),
- MX35_PIN_SCK5 = _MXC_BUILD_GPIO_PIN(0, 2, 0x138, 0x57C),
- MX35_PIN_STXFS5 = _MXC_BUILD_GPIO_PIN(0, 3, 0x13C, 0x580),
-
- MX35_PIN_SCKR = _MXC_BUILD_GPIO_PIN(0, 4, 0x140, 0x584),
- MX35_PIN_FSR = _MXC_BUILD_GPIO_PIN(0, 5, 0x144, 0x588),
- MX35_PIN_HCKR = _MXC_BUILD_GPIO_PIN(0, 6, 0x148, 0x58C),
- MX35_PIN_SCKT = _MXC_BUILD_GPIO_PIN(0, 7, 0x14C, 0x590),
- MX35_PIN_FST = _MXC_BUILD_GPIO_PIN(0, 8, 0x150, 0x594),
- MX35_PIN_HCKT = _MXC_BUILD_GPIO_PIN(0, 9, 0x154, 0x598),
- MX35_PIN_TX5_RX0 = _MXC_BUILD_GPIO_PIN(0, 10, 0x158, 0x59C),
- MX35_PIN_TX4_RX1 = _MXC_BUILD_GPIO_PIN(0, 11, 0x15C, 0x5A0),
- MX35_PIN_TX3_RX2 = _MXC_BUILD_GPIO_PIN(0, 12, 0x160, 0x5A4),
- MX35_PIN_TX2_RX3 = _MXC_BUILD_GPIO_PIN(0, 13, 0x164, 0x5A8),
- MX35_PIN_TX1 = _MXC_BUILD_GPIO_PIN(0, 14, 0x168, 0x5AC),
- MX35_PIN_TX0 = _MXC_BUILD_GPIO_PIN(0, 15, 0x16C, 0x5B0),
-
- MX35_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(0, 16, 0x170, 0x5B4),
- MX35_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(0, 17, 0x174, 0x5B8),
- MX35_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(0, 18, 0x178, 0x5BC),
- MX35_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(0, 19, 0x17C, 0x5C0),
- MX35_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(2, 4, 0x180, 0x5C4),
- MX35_PIN_CSPI1_SPI_RDY = _MXC_BUILD_GPIO_PIN(2, 5, 0x184, 0x5C8),
-
- MX35_PIN_RXD1 = _MXC_BUILD_GPIO_PIN(2, 6, 0x188, 0x5CC),
- MX35_PIN_TXD1 = _MXC_BUILD_GPIO_PIN(2, 7, 0x18C, 0x5D0),
- MX35_PIN_RTS1 = _MXC_BUILD_GPIO_PIN(2, 8, 0x190, 0x5D4),
- MX35_PIN_CTS1 = _MXC_BUILD_GPIO_PIN(2, 9, 0x194, 0x5D8),
- MX35_PIN_RXD2 = _MXC_BUILD_GPIO_PIN(2, 10, 0x198, 0x5DC),
- MX35_PIN_TXD2 = _MXC_BUILD_GPIO_PIN(1, 11, 0x19C, 0x5E0),
- MX35_PIN_RTS2 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1A0, 0x5E4),
- MX35_PIN_CTS2 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1A4, 0x5E8),
-
- MX35_PIN_USBOTG_PWR = _MXC_BUILD_GPIO_PIN(2, 14, 0x1A8, 0x60C),
- MX35_PIN_USBOTG_OC = _MXC_BUILD_GPIO_PIN(2, 15, 0x1AC, 0x610),
-
- MX35_PIN_LD0 = _MXC_BUILD_GPIO_PIN(1, 0, 0x1B0, 0x614),
- MX35_PIN_LD1 = _MXC_BUILD_GPIO_PIN(1, 1, 0x1B4, 0x618),
- MX35_PIN_LD2 = _MXC_BUILD_GPIO_PIN(1, 2, 0x1B8, 0x61C),
- MX35_PIN_LD3 = _MXC_BUILD_GPIO_PIN(1, 3, 0x1BC, 0x620),
- MX35_PIN_LD4 = _MXC_BUILD_GPIO_PIN(1, 4, 0x1C0, 0x624),
- MX35_PIN_LD5 = _MXC_BUILD_GPIO_PIN(1, 5, 0x1C4, 0x628),
- MX35_PIN_LD6 = _MXC_BUILD_GPIO_PIN(1, 6, 0x1C8, 0x62C),
- MX35_PIN_LD7 = _MXC_BUILD_GPIO_PIN(1, 7, 0x1CC, 0x630),
- MX35_PIN_LD8 = _MXC_BUILD_GPIO_PIN(1, 8, 0x1D0, 0x634),
- MX35_PIN_LD9 = _MXC_BUILD_GPIO_PIN(1, 9, 0x1D4, 0x638),
- MX35_PIN_LD10 = _MXC_BUILD_GPIO_PIN(1, 10, 0x1D8, 0x63C),
- MX35_PIN_LD11 = _MXC_BUILD_GPIO_PIN(1, 11, 0x1DC, 0x640),
- MX35_PIN_LD12 = _MXC_BUILD_GPIO_PIN(1, 12, 0x1E0, 0x644),
- MX35_PIN_LD13 = _MXC_BUILD_GPIO_PIN(1, 13, 0x1E4, 0x648),
- MX35_PIN_LD14 = _MXC_BUILD_GPIO_PIN(1, 14, 0x1E8, 0x64C),
- MX35_PIN_LD15 = _MXC_BUILD_GPIO_PIN(1, 15, 0x1EC, 0x650),
- MX35_PIN_LD16 = _MXC_BUILD_GPIO_PIN(1, 16, 0x1F0, 0x654),
- MX35_PIN_LD17 = _MXC_BUILD_GPIO_PIN(1, 17, 0x1F4, 0x658),
- MX35_PIN_LD18 = _MXC_BUILD_GPIO_PIN(2, 24, 0x1F8, 0x65C),
- MX35_PIN_LD19 = _MXC_BUILD_GPIO_PIN(2, 25, 0x1FC, 0x660),
- MX35_PIN_LD20 = _MXC_BUILD_GPIO_PIN(2, 26, 0x200, 0x664),
- MX35_PIN_LD21 = _MXC_BUILD_GPIO_PIN(2, 27, 0x204, 0x668),
- MX35_PIN_LD22 = _MXC_BUILD_GPIO_PIN(2, 28, 0x208, 0x66C),
- MX35_PIN_LD23 = _MXC_BUILD_GPIO_PIN(2, 29, 0x20C, 0x670),
-
- MX35_PIN_D3_HSYNC = _MXC_BUILD_GPIO_PIN(2, 30, 0x210, 0x674),
- MX35_PIN_D3_FPSHIFT = _MXC_BUILD_GPIO_PIN(2, 31, 0x214, 0x678),
- MX35_PIN_D3_DRDY = _MXC_BUILD_GPIO_PIN(0, 0, 0x218, 0x67C),
- MX35_PIN_CONTRAST = _MXC_BUILD_GPIO_PIN(0, 1, 0x21C, 0x680),
- MX35_PIN_D3_VSYNC = _MXC_BUILD_GPIO_PIN(0, 2, 0x220, 0x684),
- MX35_PIN_D3_REV = _MXC_BUILD_GPIO_PIN(0, 3, 0x224, 0x688),
- MX35_PIN_D3_CLS = _MXC_BUILD_GPIO_PIN(0, 4, 0x228, 0x68C),
- MX35_PIN_D3_SPL = _MXC_BUILD_GPIO_PIN(0, 5, 0x22C, 0x690),
-
- MX35_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 6, 0x230, 0x694),
- MX35_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 7, 0x234, 0x698),
- MX35_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 8, 0x238, 0x69C),
- MX35_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 9, 0x23C, 0x6A0),
- MX35_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 10, 0x240, 0x6A4),
- MX35_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 11, 0x244, 0x6A8),
- MX35_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(1, 0, 0x248, 0x6AC),
- MX35_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(1, 1, 0x24C, 0x6B0),
- MX35_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(1, 2, 0x250, 0x6B4),
- MX35_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(1, 3, 0x254, 0x6B8),
- MX35_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(1, 4, 0x258, 0x6BC),
- MX35_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(1, 5, 0x25C, 0x6C0),
-
- MX35_PIN_ATA_CS0 = _MXC_BUILD_GPIO_PIN(1, 6, 0x260, 0x6C4),
- MX35_PIN_ATA_CS1 = _MXC_BUILD_GPIO_PIN(1, 7, 0x264, 0x6C8),
- MX35_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(1, 8, 0x268, 0x6CC),
- MX35_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(1, 9, 0x26C, 0x6D0),
- MX35_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(1, 10, 0x270, 0x6D4),
- MX35_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(1, 11, 0x274, 0x6D8),
- MX35_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(1, 12, 0x278, 0x6DC),
- MX35_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 13, 0x27C, 0x6E0),
- MX35_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 14, 0x280, 0x6E4),
- MX35_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 15, 0x284, 0x6E8),
- MX35_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 16, 0x288, 0x6EC),
- MX35_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 17, 0x28C, 0x6F0),
- MX35_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 18, 0x290, 0x6F4),
- MX35_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 19, 0x294, 0x6F8),
- MX35_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 20, 0x298, 0x6FC),
- MX35_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 21, 0x29C, 0x700),
- MX35_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 22, 0x2A0, 0x704),
- MX35_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 23, 0x2A4, 0x708),
- MX35_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 24, 0x2A8, 0x70C),
- MX35_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 25, 0x2AC, 0x710),
- MX35_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 26, 0x2B0, 0x714),
- MX35_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 27, 0x2B4, 0x718),
- MX35_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 28, 0x2B8, 0x71C),
- MX35_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(1, 29, 0x2BC, 0x720),
- MX35_PIN_ATA_BUFF_EN = _MXC_BUILD_GPIO_PIN(1, 30, 0x2C0, 0x724),
- MX35_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(1, 31, 0x2C4, 0x728),
- MX35_PIN_ATA_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 0x2C8, 0x72C),
- MX35_PIN_ATA_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 0x2CC, 0x730),
- MX35_PIN_ATA_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 0x2D0, 0x734),
-
- MX35_PIN_MLB_CLK = _MXC_BUILD_GPIO_PIN(2, 3, 0x2D4, 0x738),
- MX35_PIN_MLB_DAT = _MXC_BUILD_GPIO_PIN(2, 4, 0x2D8, 0x73C),
- MX35_PIN_MLB_SIG = _MXC_BUILD_GPIO_PIN(2, 5, 0x2DC, 0x740),
-
- MX35_PIN_FEC_TX_CLK = _MXC_BUILD_GPIO_PIN(2, 6, 0x2E0, 0x744),
- MX35_PIN_FEC_RX_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 0x2E4, 0x748),
- MX35_PIN_FEC_RX_DV = _MXC_BUILD_GPIO_PIN(2, 8, 0x2E8, 0x74C),
- MX35_PIN_FEC_COL = _MXC_BUILD_GPIO_PIN(2, 9, 0x2EC, 0x750),
- MX35_PIN_FEC_RDATA0 = _MXC_BUILD_GPIO_PIN(2, 10, 0x2F0, 0x754),
- MX35_PIN_FEC_TDATA0 = _MXC_BUILD_GPIO_PIN(2, 11, 0x2F4, 0x758),
- MX35_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(2, 12, 0x2F8, 0x75C),
- MX35_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(2, 13, 0x2FC, 0x760),
- MX35_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(2, 14, 0x300, 0x764),
- MX35_PIN_FEC_TX_ERR = _MXC_BUILD_GPIO_PIN(2, 15, 0x304, 0x768),
- MX35_PIN_FEC_RX_ERR = _MXC_BUILD_GPIO_PIN(2, 16, 0x308, 0x76C),
- MX35_PIN_FEC_CRS = _MXC_BUILD_GPIO_PIN(2, 17, 0x30C, 0x770),
- MX35_PIN_FEC_RDATA1 = _MXC_BUILD_GPIO_PIN(2, 18, 0x310, 0x774),
- MX35_PIN_FEC_TDATA1 = _MXC_BUILD_GPIO_PIN(2, 19, 0x314, 0x778),
- MX35_PIN_FEC_RDATA2 = _MXC_BUILD_GPIO_PIN(2, 20, 0x318, 0x77C),
- MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780),
- MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784),
- MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788),
-} iomux_pin_name_t;
-
-#endif
-#endif
diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index 9cdfb48a7a..6910192659 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -68,5 +68,6 @@ void set_usboh3_clk(void);
void enable_usboh3_clk(unsigned char enable);
void mxc_set_sata_internal_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+void enable_nfc_clk(unsigned char enable);
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index a71cc13e2a..8984e423e6 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -267,6 +267,8 @@
/* M4IF */
#define M4IF_FBPM0 0x40
#define M4IF_FIDBP 0x48
+#define M4IF_GENP_WEIM_MM_MASK 0x00000001
+#define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
/* Assuming 24MHz input clock with doubler ON */
/* MFI PDF */
@@ -499,7 +501,7 @@ struct iim_regs {
u32 sdat;
u32 prev;
u32 srev;
- u32 preg_p;
+ u32 prg_p;
u32 scs0;
u32 scs1;
u32 scs2;
@@ -508,12 +510,22 @@ struct iim_regs {
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
+#if defined(CONFIG_MX51)
} bank[4];
+#elif defined(CONFIG_MX53)
+ } bank[5];
+#endif
};
struct fuse_bank0_regs {
- u32 fuse0_23[24];
+ u32 fuse0_7[8];
+ u32 uid[8];
+ u32 fuse16_23[8];
+#if defined(CONFIG_MX51)
+ u32 imei[8];
+#elif defined(CONFIG_MX53)
u32 gp[8];
+#endif
};
struct fuse_bank1_regs {
@@ -522,6 +534,14 @@ struct fuse_bank1_regs {
u32 fuse15_31[0x11];
};
+#if defined(CONFIG_MX53)
+struct fuse_bank4_regs {
+ u32 fuse0_4[5];
+ u32 gp[3];
+ u32 fuse8_31[0x18];
+};
+#endif
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
index 4f37295994..70aaa37f9d 100644
--- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
@@ -21,29 +21,8 @@
#include <asm/imx-common/iomux-v3.h>
-#define PAD_CTL_DVS (1 << 13)
-#define PAD_CTL_INPUT_DDR (1 << 9)
-#define PAD_CTL_HYS (1 << 8)
-
-#define PAD_CTL_PKE (1 << 7)
-#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
-#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
-#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
-
-#define PAD_CTL_ODE (1 << 3)
-
-#define PAD_CTL_DSE_LOW (0 << 1)
-#define PAD_CTL_DSE_MED (1 << 1)
-#define PAD_CTL_DSE_HIGH (2 << 1)
-#define PAD_CTL_DSE_MAX (3 << 1)
-
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
/* Pad control groupings */
-#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
+#define MX51_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
PAD_CTL_HYS | PAD_CTL_SRE_FAST)
#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
@@ -51,17 +30,17 @@
#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
PAD_CTL_HYS)
-#define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
- PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
- PAD_CTL_HYS | PAD_CTL_PUE)
+#define MX51_USBH_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
-#define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
- PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
+#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
PAD_CTL_SRE_FAST | PAD_CTL_DVS)
#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
-#define __NA_ 0x000
+#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
/*
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
@@ -69,26 +48,57 @@
* See also iomux-v3.h
*/
-/* PAD MUX ALT INPSE PATH PADCTRL */
+/* PAD MUX ALT INPSE PATH PADCTRL */
enum {
- MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D17__GPIO2_1 = IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D21__GPIO2_5 = IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_EIM_D26__UART3_TXD = IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL),
MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A16__GPIO2_10 = IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A17__GPIO2_11 = IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A20__GPIO2_14 = IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
MX51_PAD_EIM_A26__GPIO2_20 = IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL),
- MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_EB2__FEC_MDIO = IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS),
+ MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_EB3__GPIO2_23 = IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_EIM_CS2__SD1_CD = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS2__GPIO2_27 = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_CS5__FEC_CRS = IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2),
+ MX51_PAD_DRAM_RAS__DRAM_RAS = IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_CAS__DRAM_CAS = IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDWE__DRAM_SDWE = IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDCKE0__DRAM_SDCKE0 = IOMUX_PAD(0x4b0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDCKE1__DRAM_SDCKE1 = IOMUX_PAD(0x4b4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDCLK__DRAM_SDCLK = IOMUX_PAD(0x4b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDQS0__DRAM_SDQS0 = IOMUX_PAD(0x4bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDQS1__DRAM_SDQS1 = IOMUX_PAD(0x4c0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDQS2__DRAM_SDQS2 = IOMUX_PAD(0x4c4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDQS3__DRAM_SDQS3 = IOMUX_PAD(0x4c8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_CS0__DRAM_CS0 = IOMUX_PAD(0x4cc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_CS1__DRAM_CS1 = IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM0__DRAM_DQM0 = IOMUX_PAD(0x4d4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM1__DRAM_DQM1 = IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM2__DRAM_DQM2 = IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM3__DRAM_DQM3 = IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
@@ -96,19 +106,38 @@ enum {
MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RB2__FEC_COL = IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2),
+ MX51_PAD_NANDF_RB2__GPIO3_10 = IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_RB3__FEC_RX_CLK = IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2),
+ MX51_PAD_NANDF_RB3__GPIO3_11 = IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS3__FEC_MDC = IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_CS3__PATA_CS_1 = IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS4__FEC_TDATA1 = IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_CS4__PATA_DA_0 = IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS5__FEC_TDATA2 = IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_CS5__PATA_DA_1 = IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS6__FEC_TDATA3 = IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS7__FEC_TX_EN = IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK = IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4),
+ MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D12__PATA_DATA12 = IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D11__FEC_RX_DV = IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D11__PATA_DATA11 = IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D10__GPIO3_30 = IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_NANDF_D10__PATA_DATA10 = IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D9__FEC_RDATA0 = IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4),
+ MX51_PAD_NANDF_D9__GPIO3_31 = IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_NANDF_D9__PATA_DATA9 = IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_D8__FEC_TDATA0 = IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5),
MX51_PAD_NANDF_D8__PATA_DATA8 = IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D7__PATA_DATA7 = IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D6__PATA_DATA6 = IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
@@ -118,34 +147,52 @@ enum {
MX51_PAD_NANDF_D2__PATA_DATA2 = IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D1__PATA_DATA1 = IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_CSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_CSPI1_SS0__GPIO4_24 = IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSPI1_SS1__ECSPI1_SS1 = IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_CSPI1_SS1__GPIO4_25 = IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_CSPI1_RDY__ECSPI1_RDY = IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_CSPI1_RDY__GPIO4_26 = IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL),
MX51_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL),
MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL),
MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL),
MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL),
- MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_STP__USBH1_STP = IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
MX51_PAD_USBH1_STP__GPIO1_27 = IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL),
- MX51_PAD_USBH1_NXT__USBH1_NXT = IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA0__USBH1_DATA0 = IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA1__USBH1_DATA1 = IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA2__USBH1_DATA2 = IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA3__USBH1_DATA3 = IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA4__USBH1_DATA4 = IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
- MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL),
+ MX51_PAD_USBH1_STP__USBH1_STP = IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_NXT__USBH1_NXT = IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA0__USBH1_DATA0 = IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA1__USBH1_DATA1 = IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA2__USBH1_DATA2 = IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA3__USBH1_DATA3 = IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA4__USBH1_DATA4 = IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_DI1_PIN11__ECSPI1_SS2 = IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_DI1_PIN12__GPIO3_1 = IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_PIN13__GPIO3_2 = IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_D0_CS__GPIO3_3 = IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_D1_CS__GPIO3_4 = IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DISPB2_SER_DIN__GPIO3_5 = IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DI_GP4__DI2_PIN15 = IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS),
MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_0__SD1_CD = IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
MX51_PAD_GPIO1_1__SD1_WP = IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL),
MX51_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
@@ -154,11 +201,36 @@ enum {
MX51_PAD_SD2_DATA1__SD2_DATA1 = IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
MX51_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL),
+ MX51_PAD_GPIO1_2__GPIO1_2 = IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_2__PWM1_PWMO = IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL),
MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_GPIO1_7__GPIO1_7 = IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL),
MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL),
+ MX51_GRP_DDRPKS = IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B4 = IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_PKEDDR = IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDR_A0 = IOMUX_PAD(0x83c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDR_A1 = IOMUX_PAD(0x848, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDRAPUS = IOMUX_PAD(0x84c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR0 = IOMUX_PAD(0x85c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR1 = IOMUX_PAD(0x864, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR2 = IOMUX_PAD(0x86c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_HYSDDR3 = IOMUX_PAD(0x874, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_SR_B0 = IOMUX_PAD(0x878, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDRAPKS = IOMUX_PAD(0x87c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_SR_B1 = IOMUX_PAD(0x880, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDRPUS = IOMUX_PAD(0x884, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_SR_B2 = IOMUX_PAD(0x88c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_PKEADDR = IOMUX_PAD(0x890, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_SR_B4 = IOMUX_PAD(0x89c, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_INMODE1 = IOMUX_PAD(0x8a0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B0 = IOMUX_PAD(0x8a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B1 = IOMUX_PAD(0x8ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DRAM_B2 = IOMUX_PAD(0x8b8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_GRP_DDR_SR_A1 = IOMUX_PAD(0x8bc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
};
#endif /* __IOMUX_MX51_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx53.h b/arch/arm/include/asm/arch-mx5/iomux-mx53.h
new file mode 100644
index 0000000000..f55c0f5004
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/iomux-mx53.h
@@ -0,0 +1,1232 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on Freescale's Linux i.MX iomux-mx53.h file:
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_MX53_H__
+#define __IOMUX_MX53_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define MX53_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+
+/*
+ * The naming convention for the pad modes is MX53_PAD_<padname>__<padmode>
+ * If <padname> refers to a GPIO, it is named GPIO_<unit>
+ * If <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
+ * See also iomux-v3.h
+ */
+
+/* PAD MUX ALT INPSE PATH PADCTRL */
+enum {
+ MX53_PAD_GPIO_19__KPP_COL_5 = IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__GPIO4_5 = IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__CCM_CLKO = IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__SPDIF_OUT1 = IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 = IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__ECSPI1_RDY = IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__FEC_TDATA_3 = IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_19__SRC_INT_BOOT = IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL0__GPIO4_6 = IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC = IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL0__UART4_TXD_MUX = IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_KEY_COL0__ECSPI1_SCLK = IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL0__FEC_RDATA_3 = IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL0__SRC_ANY_PU_RST = IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW0__GPIO4_7 = IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW0__UART4_RXD_MUX = IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW0__FEC_TX_ER = IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL1__GPIO4_8 = IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL1__UART5_TXD_MUX = IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL1__FEC_RX_CLK = IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL1__USBPHY1_TXREADY = IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__GPIO4_9 = IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__UART5_RXD_MUX = IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__FEC_COL = IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW1__USBPHY1_RXVALID = IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__GPIO4_10 = IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__FEC_MDIO = IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__FEC_RDATA_2 = IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE = IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__GPIO4_11 = IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__FEC_MDC = IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__FEC_TDATA_2 = IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW2__USBPHY1_RXERROR = IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__GPIO4_12 = IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__USBOH3_H2_DP = IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__FEC_CRS = IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK = IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__GPIO4_13 = IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__USBOH3_H2_DM = IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK = IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__CCM_PLL4_BYP = IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 = IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL4__GPIO4_14 = IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL4__IPU_SISG_4 = IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 = IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__GPIO4_15 = IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__IPU_SISG_5 = IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID = IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK = IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_DISP_CLK__GPIO4_16 = IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR = IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 = IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 = IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID = IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 = IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN15__GPIO4_17 = IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC = IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 = IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN15__USBPHY1_BVALID = IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 = IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN2__GPIO4_18 = IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD = IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 = IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION = IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 = IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN3__GPIO4_19 = IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 = IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN3__USBPHY1_IDDIG = IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 = IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__GPIO4_20 = IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__ESDHC1_WP = IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 = IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT = IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 = IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__GPIO4_21 = IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__CSPI_SCLK = IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 = IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 = IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY = IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 = IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__GPIO4_22 = IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__CSPI_MOSI = IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 = IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL
+ = IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 = IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID = IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 = IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__GPIO4_23 = IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__CSPI_MISO = IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 = IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 = IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE = IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 = IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__GPIO4_24 = IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__CSPI_SS0 = IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 = IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 = IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR = IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 = IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__GPIO4_25 = IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__CSPI_SS1 = IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 = IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 = IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK = IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 = IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__GPIO4_26 = IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__CSPI_SS2 = IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 = IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 = IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 = IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 = IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__GPIO4_27 = IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__CSPI_SS3 = IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 = IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 = IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 = IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 = IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__GPIO4_28 = IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__CSPI_RDY = IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 = IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 = IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID = IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 = IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__GPIO4_29 = IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B = IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 = IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT8__USBPHY2_AVALID = IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 = IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__GPIO4_30 = IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B = IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 = IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 = IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 = IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT10__GPIO4_31 = IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP = IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3
+ = IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 = IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 = IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 = IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT11__GPIO5_5 = IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT = IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4
+ = IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 = IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 = IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 = IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT12__GPIO5_6 = IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK = IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5
+ = IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 = IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 = IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 = IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT13__GPIO5_7 = IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0
+ = IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 = IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 = IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 = IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT14__GPIO5_8 = IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1
+ = IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 = IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 = IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 = IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__GPIO5_9 = IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__ECSPI2_SS1 = IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2
+ = IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 = IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 = IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 = IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__GPIO5_10 = IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC = IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3
+ = IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 = IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 = IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 = IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__GPIO5_11 = IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD = IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4
+ = IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 = IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 = IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__GPIO5_12 = IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5
+ = IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 = IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 = IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 = IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__GPIO5_13 = IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__ECSPI2_SCLK = IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD = IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC = IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6
+ = IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 = IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 = IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 = IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__GPIO5_14 = IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC = IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7
+ = IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 = IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT20__SATA_PHY_TDI = IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 = IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__GPIO5_15 = IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD = IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 = IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT21__SATA_PHY_TDO = IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 = IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__GPIO5_16 = IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 = IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT22__SATA_PHY_TCK = IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 = IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__GPIO5_17 = IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD = IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 = IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_DISP0_DAT23__SATA_PHY_TMS = IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK = IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_PIXCLK__GPIO5_18 = IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 = IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 = IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC = IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_MCLK__GPIO5_19 = IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK = IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 = IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 = IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_MCLK__TPIU_TRCTL = IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN = IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DATA_EN__GPIO5_20 = IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 = IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 = IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK = IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC = IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_VSYNC__GPIO5_21 = IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 = IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 = IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 = IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 = IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__GPIO5_22 = IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__KPP_COL_5 = IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__ECSPI1_SCLK = IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP = IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC = IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 = IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 = IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 = IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__GPIO5_23 = IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__KPP_ROW_5 = IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__ECSPI1_MOSI = IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT = IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD = IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 = IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 = IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 = IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__GPIO5_24 = IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__KPP_COL_6 = IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__ECSPI1_MISO = IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK = IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 = IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 = IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 = IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__GPIO5_25 = IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__KPP_ROW_6 = IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__ECSPI1_SS0 = IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR = IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD = IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 = IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 = IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 = IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__GPIO5_26 = IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__KPP_COL_7 = IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__ECSPI2_SCLK = IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC = IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__I2C1_SDA = IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 = IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 = IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 = IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__GPIO5_27 = IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__KPP_ROW_7 = IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__ECSPI2_MOSI = IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR = IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__I2C1_SCL = IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 = IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 = IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 = IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__GPIO5_28 = IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__UART1_TXD_MUX = IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__ECSPI2_MISO = IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC = IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 = IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 = IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 = IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 = IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__GPIO5_29 = IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__UART1_RXD_MUX = IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__ECSPI2_SS0 = IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS = IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 = IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 = IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 = IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 = IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__GPIO5_30 = IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__UART4_TXD_MUX = IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 = IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 = IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 = IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 = IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 = IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__GPIO5_31 = IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__UART4_RXD_MUX = IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 = IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 = IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 = IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 = IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 = IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__GPIO6_0 = IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__UART5_TXD_MUX = IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 = IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 = IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 = IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 = IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__GPIO6_1 = IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__UART5_RXD_MUX = IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 = IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 = IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 = IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 = IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 = IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__GPIO6_2 = IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__UART4_RTS = IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 = IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 = IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 = IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 = IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 = IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__GPIO6_3 = IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__UART4_CTS = IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 = IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 = IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 = IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 = IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 = IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__GPIO6_4 = IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__UART5_RTS = IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 = IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 = IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 = IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 = IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 = IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__GPIO6_5 = IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__UART5_CTS = IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 = IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 = IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 = IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK = IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__EMI_WEIM_A_25 = IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__GPIO5_2 = IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__ECSPI2_RDY = IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__IPU_DI1_PIN12 = IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__CSPI_SS1 = IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__IPU_DI0_D1_CS = IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A25__USBPHY1_BISTOK = IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 = IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB2__GPIO2_30 = IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK = IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS = IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB2__ECSPI1_SS0 = IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB2__I2C2_SCL = IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D16__EMI_WEIM_D_16 = IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D16__GPIO3_16 = IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D16__IPU_DI0_PIN5 = IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK = IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D16__ECSPI1_SCLK = IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL),
+ MX53_PAD_EIM_D16__I2C2_SDA = IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D17__EMI_WEIM_D_17 = IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D17__GPIO3_17 = IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D17__IPU_DI0_PIN6 = IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN = IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D17__ECSPI1_MISO = IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL),
+ MX53_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__EMI_WEIM_D_18 = IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__GPIO3_18 = IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__IPU_DI0_PIN7 = IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO = IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D18__IPU_DI1_D0_CS = IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__EMI_WEIM_D_19 = IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__GPIO3_19 = IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__IPU_DI0_PIN8 = IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS = IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D19__USBOH3_USBH2_OC = IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__EMI_WEIM_D_20 = IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__GPIO3_20 = IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__IPU_DI0_PIN16 = IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__IPU_SER_DISP0_CS = IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__CSPI_SS0 = IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__EPIT2_EPITO = IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D20__UART1_RTS = IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D20__USBOH3_USBH2_PWR = IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__EMI_WEIM_D_21 = IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__GPIO3_21 = IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__IPU_DI0_PIN17 = IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK = IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__CSPI_SCLK = IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__I2C1_SCL = IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D21__USBOH3_USBOTG_OC = IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D22__EMI_WEIM_D_22 = IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D22__GPIO3_22 = IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D22__IPU_DI0_PIN1 = IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN = IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D22__CSPI_MISO = IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__EMI_WEIM_D_23 = IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__GPIO3_23 = IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D23__UART1_DCD = IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__IPU_DI0_D0_CS = IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__IPU_DI1_PIN2 = IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN = IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D23__IPU_DI1_PIN14 = IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 = IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__GPIO2_31 = IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__UART3_RTS = IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_EB3__UART1_RI = IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__IPU_DI1_PIN3 = IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC = IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB3__IPU_DI1_PIN16 = IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__EMI_WEIM_D_24 = IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__GPIO3_24 = IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__UART3_TXD_MUX = IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D24__ECSPI1_SS2 = IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__CSPI_SS2 = IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__ECSPI2_SS2 = IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D24__UART1_DTR = IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__EMI_WEIM_D_25 = IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__GPIO3_25 = IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__UART3_RXD_MUX = IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D25__ECSPI1_SS3 = IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__CSPI_SS3 = IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC = IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__ECSPI2_SS3 = IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D25__UART1_DSR = IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__EMI_WEIM_D_26 = IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__GPIO3_26 = IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__UART2_TXD_MUX = IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D26__FIRI_RXD = IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__IPU_CSI0_D_1 = IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__IPU_DI1_PIN11 = IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__IPU_SISG_2 = IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 = IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__EMI_WEIM_D_27 = IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__GPIO3_27 = IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__UART2_RXD_MUX = IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D27__FIRI_TXD = IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__IPU_CSI0_D_0 = IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__IPU_DI1_PIN13 = IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__IPU_SISG_3 = IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 = IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__EMI_WEIM_D_28 = IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__GPIO3_28 = IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__UART2_CTS = IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO = IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__CSPI_MOSI = IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__IPU_EXT_TRIG = IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D28__IPU_DI0_PIN13 = IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__EMI_WEIM_D_29 = IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__GPIO3_29 = IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__UART2_RTS = IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS = IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__CSPI_SS0 = IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__IPU_DI1_PIN15 = IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__IPU_CSI1_VSYNC = IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D29__IPU_DI0_PIN14 = IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__EMI_WEIM_D_30 = IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__GPIO3_30 = IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D30__IPU_CSI0_D_3 = IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__IPU_DI0_PIN11 = IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 = IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D30__USBOH3_USBH2_OC = IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__EMI_WEIM_D_31 = IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__GPIO3_31 = IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_EIM_D31__IPU_CSI0_D_2 = IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__IPU_DI0_PIN12 = IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 = IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_D31__USBOH3_USBH2_PWR = IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A24__EMI_WEIM_A_24 = IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A24__GPIO5_4 = IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 = IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A24__IPU_CSI1_D_19 = IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A24__IPU_SISG_2 = IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A24__USBPHY2_BVALID = IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A23__EMI_WEIM_A_23 = IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A23__GPIO6_6 = IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 = IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A23__IPU_CSI1_D_18 = IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A23__IPU_SISG_3 = IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A23__USBPHY2_ENDSESSION = IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A22__EMI_WEIM_A_22 = IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 = IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A22__IPU_CSI1_D_17 = IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A22__SRC_BT_CFG1_7 = IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A21__EMI_WEIM_A_21 = IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A21__GPIO2_17 = IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 = IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A21__IPU_CSI1_D_16 = IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A21__SRC_BT_CFG1_6 = IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A20__EMI_WEIM_A_20 = IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A20__GPIO2_18 = IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 = IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A20__IPU_CSI1_D_15 = IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A20__SRC_BT_CFG1_5 = IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A19__EMI_WEIM_A_19 = IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A19__GPIO2_19 = IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 = IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A19__IPU_CSI1_D_14 = IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A19__SRC_BT_CFG1_4 = IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A18__EMI_WEIM_A_18 = IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A18__GPIO2_20 = IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 = IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A18__IPU_CSI1_D_13 = IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A18__SRC_BT_CFG1_3 = IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A17__EMI_WEIM_A_17 = IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A17__GPIO2_21 = IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 = IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A17__IPU_CSI1_D_12 = IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A17__SRC_BT_CFG1_2 = IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A16__EMI_WEIM_A_16 = IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A16__GPIO2_22 = IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK = IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK = IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_A16__SRC_BT_CFG1_1 = IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 = IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS0__GPIO2_23 = IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS0__ECSPI2_SCLK = IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS0__IPU_DI1_PIN5 = IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 = IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS1__GPIO2_24 = IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS1__ECSPI2_MOSI = IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL),
+ MX53_PAD_EIM_CS1__IPU_DI1_PIN6 = IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_OE__EMI_WEIM_OE = IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_OE__GPIO2_25 = IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_OE__ECSPI2_MISO = IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL),
+ MX53_PAD_EIM_OE__IPU_DI1_PIN7 = IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_OE__USBPHY2_IDDIG = IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_RW__EMI_WEIM_RW = IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_RW__GPIO2_26 = IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_RW__ECSPI2_SS0 = IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL),
+ MX53_PAD_EIM_RW__IPU_DI1_PIN8 = IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT = IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_LBA__EMI_WEIM_LBA = IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_LBA__GPIO2_27 = IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_LBA__ECSPI2_SS1 = IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_LBA__IPU_DI1_PIN17 = IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 = IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 = IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB0__GPIO2_28 = IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 = IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB0__IPU_CSI1_D_11 = IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB0__GPC_PMIC_RDY = IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 = IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 = IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB1__GPIO2_29 = IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 = IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB1__IPU_CSI1_D_10 = IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 = IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 = IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA0__GPIO3_0 = IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 = IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA0__IPU_CSI1_D_9 = IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 = IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 = IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA1__GPIO3_1 = IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 = IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA1__IPU_CSI1_D_8 = IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 = IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 = IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA2__GPIO3_2 = IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 = IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA2__IPU_CSI1_D_7 = IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 = IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 = IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA3__GPIO3_3 = IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 = IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA3__IPU_CSI1_D_6 = IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 = IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 = IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA4__GPIO3_4 = IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 = IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA4__IPU_CSI1_D_5 = IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 = IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 = IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA5__GPIO3_5 = IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 = IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA5__IPU_CSI1_D_4 = IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 = IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 = IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA6__GPIO3_6 = IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 = IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA6__IPU_CSI1_D_3 = IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 = IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 = IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA7__GPIO3_7 = IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 = IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA7__IPU_CSI1_D_2 = IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 = IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 = IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA8__GPIO3_8 = IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 = IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA8__IPU_CSI1_D_1 = IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 = IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 = IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA9__GPIO3_9 = IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 = IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA9__IPU_CSI1_D_0 = IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 = IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 = IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA10__GPIO3_10 = IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA10__IPU_DI1_PIN15 = IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN = IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 = IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 = IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA11__GPIO3_11 = IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA11__IPU_DI1_PIN2 = IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC = IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 = IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA12__GPIO3_12 = IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA12__IPU_DI1_PIN3 = IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC = IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 = IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA13__GPIO3_13 = IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA13__IPU_DI1_D0_CS = IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK = IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 = IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA14__GPIO3_14 = IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA14__IPU_DI1_D1_CS = IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK = IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 = IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA15__GPIO3_15 = IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA15__IPU_DI1_PIN1 = IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_DA15__IPU_DI1_PIN4 = IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B = IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_WE_B__GPIO6_12 = IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B = IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_RE_B__GPIO6_13 = IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT = IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_WAIT__GPIO5_0 = IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B = IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX3_P__GPIO6_22 = IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 = IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX2_P__GPIO6_24 = IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 = IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_CLK_P__GPIO6_26 = IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK = IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX1_P__GPIO6_28 = IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 = IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX0_P__GPIO6_30 = IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 = IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX3_P__GPIO7_22 = IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 = IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_CLK_P__GPIO7_24 = IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX2_P__GPIO7_26 = IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 = IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX1_P__GPIO7_28 = IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX0_P__GPIO7_30 = IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_10__GPIO4_0 = IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_10__OSC32k_32K_OUT = IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_11__GPIO4_1 = IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_12__GPIO4_2 = IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_13__GPIO4_3 = IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_14__GPIO4_4 = IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CLE__EMI_NANDF_CLE = IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CLE__GPIO6_7 = IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 = IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_ALE__EMI_NANDF_ALE = IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_ALE__GPIO6_8 = IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 = IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B = IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_WP_B__GPIO6_9 = IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 = IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 = IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_RB0__GPIO6_10 = IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 = IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 = IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS0__GPIO6_11 = IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 = IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 = IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS1__GPIO6_14 = IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS1__MLB_MLBCLK = IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 = IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 = IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__GPIO6_15 = IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__IPU_SISG_0 = IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__EMI_WEIM_CRE = IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK = IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__MLB_MLBSIG = IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 = IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 = IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__GPIO6_16 = IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__IPU_SISG_1 = IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__ESAI1_TX1 = IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 = IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__MLB_MLBDAT = IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL),
+ MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 = IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__GPIO1_22 = IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__ESAI1_SCKR = IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__FEC_COL = IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 = IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 = IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 = IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_REF_CLK__FEC_TX_CLK = IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_REF_CLK__GPIO1_23 = IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_REF_CLK__ESAI1_FSR = IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 = IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 = IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RX_ER__FEC_RX_ER = IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RX_ER__GPIO1_24 = IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RX_ER__ESAI1_HCKR = IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RX_ER__FEC_RX_CLK = IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL),
+ MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 = IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_CRS_DV__FEC_RX_DV = IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_CRS_DV__GPIO1_25 = IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_CRS_DV__ESAI1_SCKT = IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD1__FEC_RDATA_1 = IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD1__GPIO1_26 = IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD1__ESAI1_FST = IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD1__MLB_MLBSIG = IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 = IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD0__FEC_RDATA_0 = IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD0__GPIO1_27 = IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD0__ESAI1_HCKT = IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_RXD0__OSC32k_32K_OUT = IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TX_EN__GPIO1_28 = IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 = IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD1__FEC_TDATA_1 = IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD1__GPIO1_29 = IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 = IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD1__MLB_MLBCLK = IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK = IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD0__FEC_TDATA_0 = IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD0__GPIO1_30 = IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 = IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 = IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDC__GPIO1_31 = IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 = IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDC__MLB_MLBDAT = IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG = IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 = IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOW__PATA_DIOW = IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOW__GPIO6_17 = IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOW__UART1_TXD_MUX = IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 = IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMACK__PATA_DMACK = IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMACK__GPIO6_18 = IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMACK__UART1_RXD_MUX = IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 = IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMARQ__PATA_DMARQ = IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMARQ__GPIO7_0 = IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMARQ__UART2_TXD_MUX = IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 = IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 = IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN = IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_BUFFER_EN__GPIO7_1 = IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX = IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 = IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 = IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_INTRQ__PATA_INTRQ = IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_INTRQ__GPIO7_2 = IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_INTRQ__UART2_CTS = IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_INTRQ__CAN1_TXCAN = IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 = IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 = IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOR__PATA_DIOR = IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOR__GPIO7_3 = IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOR__UART2_RTS = IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_DIOR__CAN1_RXCAN = IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL),
+ MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 = IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B = IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_RESET_B__GPIO7_4 = IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_RESET_B__ESDHC3_CMD = IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_RESET_B__UART1_CTS = IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_RESET_B__CAN2_TXCAN = IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 = IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_IORDY__PATA_IORDY = IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_IORDY__GPIO7_5 = IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_IORDY__ESDHC3_CLK = IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_IORDY__UART1_RTS = IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_IORDY__CAN2_RXCAN = IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL),
+ MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 = IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_0__PATA_DA_0 = IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_0__GPIO7_6 = IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_0__ESDHC3_RST = IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_0__OWIRE_LINE = IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 = IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_1__PATA_DA_1 = IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_1__GPIO7_7 = IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_1__ESDHC4_CMD = IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DA_1__UART3_CTS = IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 = IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_2__PATA_DA_2 = IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_2__GPIO7_8 = IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DA_2__ESDHC4_CLK = IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DA_2__UART3_RTS = IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 = IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_CS_0__PATA_CS_0 = IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_CS_0__GPIO7_9 = IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_CS_0__UART3_TXD_MUX = IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 = IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_CS_1__PATA_CS_1 = IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_CS_1__GPIO7_10 = IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_CS_1__UART3_RXD_MUX = IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL),
+ MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 = IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__PATA_DATA_0 = IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__GPIO2_0 = IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 = IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__ESDHC3_DAT4 = IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 = IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 = IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 = IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA1__PATA_DATA_1 = IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA1__GPIO2_1 = IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 = IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA1__ESDHC3_DAT5 = IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 = IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 = IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA2__PATA_DATA_2 = IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA2__GPIO2_2 = IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 = IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA2__ESDHC3_DAT6 = IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 = IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 = IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA3__PATA_DATA_3 = IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA3__GPIO2_3 = IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 = IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA3__ESDHC3_DAT7 = IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 = IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 = IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA4__PATA_DATA_4 = IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA4__GPIO2_4 = IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 = IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA4__ESDHC4_DAT4 = IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 = IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 = IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA5__PATA_DATA_5 = IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA5__GPIO2_5 = IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 = IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA5__ESDHC4_DAT5 = IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 = IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 = IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA6__PATA_DATA_6 = IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA6__GPIO2_6 = IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 = IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA6__ESDHC4_DAT6 = IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 = IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 = IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA7__PATA_DATA_7 = IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA7__GPIO2_7 = IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 = IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA7__ESDHC4_DAT7 = IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 = IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 = IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__PATA_DATA_8 = IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__GPIO2_8 = IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__ESDHC1_DAT4 = IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 = IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__ESDHC3_DAT0 = IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 = IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 = IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__PATA_DATA_9 = IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__GPIO2_9 = IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__ESDHC1_DAT5 = IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 = IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__ESDHC3_DAT1 = IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 = IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 = IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__PATA_DATA_10 = IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__GPIO2_10 = IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__ESDHC1_DAT6 = IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 = IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__ESDHC3_DAT2 = IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 = IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 = IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__PATA_DATA_11 = IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__GPIO2_11 = IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__ESDHC1_DAT7 = IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 = IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__ESDHC3_DAT3 = IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 = IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 = IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__PATA_DATA_12 = IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__GPIO2_12 = IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__ESDHC2_DAT4 = IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 = IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__ESDHC4_DAT0 = IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 = IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 = IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__PATA_DATA_13 = IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__GPIO2_13 = IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__ESDHC2_DAT5 = IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 = IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__ESDHC4_DAT1 = IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 = IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 = IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__PATA_DATA_14 = IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__GPIO2_14 = IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__ESDHC2_DAT6 = IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 = IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__ESDHC4_DAT2 = IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 = IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 = IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__PATA_DATA_15 = IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__GPIO2_15 = IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__ESDHC2_DAT7 = IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 = IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__ESDHC4_DAT3 = IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 = IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 = IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0 = IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD1_DATA0__GPIO1_16 = IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA0__GPT_CAPIN1 = IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA0__CSPI_MISO = IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA0__CCM_PLL3_BYP = IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1 = IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD1_DATA1__GPIO1_17 = IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA1__GPT_CAPIN2 = IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA1__CSPI_SS0 = IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA1__CCM_PLL4_BYP = IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL),
+ MX53_PAD_SD1_CMD__ESDHC1_CMD = IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD1_CMD__GPIO1_18 = IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_CMD__GPT_CMPOUT1 = IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_CMD__CSPI_MOSI = IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL),
+ MX53_PAD_SD1_CMD__CCM_PLL1_BYP = IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2 = IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__GPIO1_19 = IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__GPT_CMPOUT2 = IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__PWM2_PWMO = IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__WDOG1_WDOG_B = IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__CSPI_SS1 = IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA2__CCM_PLL2_BYP = IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_CLK__ESDHC1_CLK = IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD1_CLK__GPIO1_20 = IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_CLK__OSC32k_32K_OUT = IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_CLK__GPT_CLKIN = IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_CLK__CSPI_SCLK = IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL),
+ MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 = IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3 = IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__GPIO1_21 = IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__GPT_CMPOUT3 = IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__PWM1_PWMO = IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__WDOG2_WDOG_B = IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__CSPI_SS2 = IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 = IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_CLK__ESDHC2_CLK = IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD2_CLK__GPIO1_10 = IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_CLK__KPP_COL_5 = IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL),
+ MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS = IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_CLK__CSPI_SCLK = IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL),
+ MX53_PAD_SD2_CLK__SCC_RANDOM_V = IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_CMD__ESDHC2_CMD = IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD2_CMD__GPIO1_11 = IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_CMD__KPP_ROW_5 = IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC = IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_CMD__CSPI_MOSI = IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL),
+ MX53_PAD_SD2_CMD__SCC_RANDOM = IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3 = IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD2_DATA3__GPIO1_12 = IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA3__KPP_COL_6 = IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC = IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA3__CSPI_SS2 = IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA3__SJC_DONE = IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2 = IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD2_DATA2__GPIO1_13 = IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA2__KPP_ROW_6 = IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD = IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA2__CSPI_SS1 = IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA2__SJC_FAIL = IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1 = IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD2_DATA1__GPIO1_14 = IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA1__KPP_COL_7 = IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS = IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA1__CSPI_SS0 = IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA1__RTIC_SEC_VIO = IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0 = IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL),
+ MX53_PAD_SD2_DATA0__GPIO1_15 = IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA0__KPP_ROW_7 = IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD = IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA0__CSPI_MISO = IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL),
+ MX53_PAD_SD2_DATA0__RTIC_DONE_INT = IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__GPIO1_0 = IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK = IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__EPIT1_EPITO = IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__SRTC_ALARM_DEB = IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__USBOH3_USBH1_PWR = IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_0__CSU_TD = IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__ESAI1_SCKR = IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__GPIO1_1 = IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__KPP_ROW_5 = IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK = IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__PWM2_PWMO = IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__WDOG2_WDOG_B = IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__ESDHC1_CD = IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_1__SRC_TESTER_ACK = IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__ESAI1_FSR = IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__GPIO1_9 = IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__KPP_COL_6 = IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__CCM_REF_EN_B = IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__PWM1_PWMO = IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__WDOG1_WDOG_B = IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__ESDHC1_WP = IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_9__SCC_FAIL_STATE = IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__ESAI1_HCKR = IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__GPIO1_3 = IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__I2C3_SCL = IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__DPLLIP1_TOG_EN = IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__CCM_CLKO2 = IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 = IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__USBOH3_USBH1_OC = IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_3__MLB_MLBCLK = IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__ESAI1_SCKT = IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__GPIO1_6 = IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__I2C3_SDA = IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__CCM_CCM_OUT_0 = IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__CSU_CSU_INT_DEB = IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 = IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__ESDHC2_LCTL = IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_6__MLB_MLBSIG = IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__ESAI1_FST = IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__GPIO1_2 = IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__KPP_ROW_6 = IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__CCM_CCM_OUT_1 = IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 = IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 = IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__ESDHC2_WP = IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_2__MLB_MLBDAT = IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__ESAI1_HCKT = IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__GPIO1_4 = IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__KPP_COL_7 = IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__CCM_CCM_OUT_2 = IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 = IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 = IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__ESDHC2_CD = IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_4__SCC_SEC_STATE = IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__ESAI1_TX2_RX3 = IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__GPIO1_5 = IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__KPP_ROW_7 = IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__CCM_CLKO = IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 = IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 = IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_5__CCM_PLL1_BYP = IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__ESAI1_TX4_RX1 = IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__GPIO1_7 = IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__EPIT1_EPITO = IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__CAN1_TXCAN = IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__UART2_TXD_MUX = IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL),
+ MX53_PAD_GPIO_7__FIRI_RXD = IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__SPDIF_PLOCK = IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_7__CCM_PLL2_BYP = IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__ESAI1_TX5_RX0 = IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__GPIO1_8 = IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__EPIT2_EPITO = IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__CAN1_RXCAN = IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__UART2_RXD_MUX = IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL),
+ MX53_PAD_GPIO_8__FIRI_TXD = IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__SPDIF_SRCLK = IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_8__CCM_PLL3_BYP = IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__ESAI1_TX3_RX2 = IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__GPIO7_11 = IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT = IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 = IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__SPDIF_IN1 = IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__I2C3_SDA = IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL),
+ MX53_PAD_GPIO_16__SJC_DE_B = IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__ESAI1_TX0 = IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__GPIO7_12 = IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 = IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__GPC_PMIC_RDY = IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG = IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__SPDIF_OUT1 = IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__IPU_SNOOP2 = IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_17__SJC_JTAG_ACT = IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__ESAI1_TX1 = IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__GPIO7_13 = IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 = IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__OWIRE_LINE = IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG = IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK = IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__ESDHC1_LCTL = IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL),
+ MX53_PAD_GPIO_18__SRC_SYSTEM_RST = IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL),
+};
+
+#endif /* __IOMUX_MX53_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h
deleted file mode 100644
index e3765a37e3..0000000000
--- a/arch/arm/include/asm/arch-mx5/iomux.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __MACH_MX5_IOMUX_H__
-#define __MACH_MX5_IOMUX_H__
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx5x_pins.h>
-
-typedef unsigned int iomux_pin_name_t;
-
-/* various IOMUX output functions */
-typedef enum iomux_config {
- IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
- IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
- IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
- IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
- IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
- IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
- IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
- IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
- IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
- IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
-} iomux_pin_cfg_t;
-
-/* various IOMUX pad functions */
-typedef enum iomux_pad_config {
- PAD_CTL_SRE_SLOW = 0x0 << 0, /* Slow slew rate */
- PAD_CTL_SRE_FAST = 0x1 << 0, /* Fast slew rate */
- PAD_CTL_DRV_LOW = 0x0 << 1, /* Low drive strength */
- PAD_CTL_DRV_MEDIUM = 0x1 << 1, /* Medium drive strength */
- PAD_CTL_DRV_HIGH = 0x2 << 1, /* High drive strength */
- PAD_CTL_DRV_MAX = 0x3 << 1, /* Max drive strength */
- PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, /* Opendrain disable */
- PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */
- PAD_CTL_100K_PD = 0x0 << 4, /* 100Kohm pulldown */
- PAD_CTL_47K_PU = 0x1 << 4, /* 47Kohm pullup */
- PAD_CTL_100K_PU = 0x2 << 4, /* 100Kohm pullup */
- PAD_CTL_22K_PU = 0x3 << 4, /* 22Kohm pullup */
- PAD_CTL_PUE_KEEPER = 0x0 << 6, /* enable pulldown */
- PAD_CTL_PUE_PULL = 0x1 << 6, /* enable pullup */
- PAD_CTL_PKE_NONE = 0x0 << 7, /* Disable pullup/pulldown */
- PAD_CTL_PKE_ENABLE = 0x1 << 7, /* Enable pullup/pulldown */
- PAD_CTL_HYS_NONE = 0x0 << 8, /* Hysteresis disabled */
- PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */
- PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
- PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
- PAD_CTL_DRV_VOT_LOW = 0x1 << 13, /* Low voltage mode */
- PAD_CTL_DRV_VOT_HIGH = 0x0 << 13,/* High voltage mode */
-} iomux_pad_config_t;
-
-/* various IOMUX input functions */
-typedef enum iomux_input_config {
- INPUT_CTL_PATH0 = 0x0,
- INPUT_CTL_PATH1,
- INPUT_CTL_PATH2,
- INPUT_CTL_PATH3,
- INPUT_CTL_PATH4,
- INPUT_CTL_PATH5,
- INPUT_CTL_PATH6,
- INPUT_CTL_PATH7,
-} iomux_input_config_t;
-
-void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
-void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
-unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
-void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
-
-#endif /* __MACH_MX5_IOMUX_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h
deleted file mode 100644
index 3457f6a632..0000000000
--- a/arch/arm/include/asm/arch-mx5/mx5x_pins.h
+++ /dev/null
@@ -1,879 +0,0 @@
-/*
- * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__
-#define __ASM_ARCH_MX5_MX5X_PINS_H__
-
-#ifndef __ASSEMBLY__
-
-/*
- * In order to identify pins more effectively, each mux-controlled pin's
- * enumerated value is constructed in the following way:
- *
- * -------------------------------------------------------------------
- * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
- * -------------------------------------------------------------------
- * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
- * -------------------------------------------------------------------
- *
- * Bit 0 to 9 contains MUX_I used to identify the register
- * offset (0-based. base is IOMUX_module_base) defined in the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
- * similar field definitions are used for the pad control register.
- * The IOMUX controller can be split in two parts. At the begeinning,
- * there is the register definitions for the multiplexing each pin.
- * Then there is a set of registers (PAD_I) to configure each pin
- * (pullup, pulldown, etc).
- * PAD_I defines the offset of the pad register for each pin.
- * GPIO_I defines, if available, the number of gpio that can be
- * connected to that pad
- * IO_I defines the multiplexer mode required to set the pad in gpio mode
- * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs
- *
- * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
- * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
- * It means the mux control register is at register offset 0x28. The pad control
- * register offset is: 0x250 and also occupy the least significant bits
- * within the register.
- */
-
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * MUX control register offset
- */
-#define MUX_I 0
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent the
- * PAD control register offset
- */
-#define PAD_I 10
-/*!
- * Starting bit position within each entry of \b iomux_pins to represent which
- * mux mode is for GPIO (0-based)
- */
-#define GPIO_I 21
-
-#define MUX_IO_P 29
-#define MUX_IO_I 24
-#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
- GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
- ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
-#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
-
-#define NON_GPIO_PORT 0x7
-#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
-#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
-#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
-
-#define NON_MUX_I PIN_TO_MUX_MASK
-#define NON_PAD_I PIN_TO_PAD_MASK
-
-#if defined(CONFIG_MX51)
-#define MUX_I_START 0x001C
-#define PAD_I_START 0x3F0
-#define INPUT_CTL_START 0x8C4
-#define MUX_I_END (PAD_I_START - 4)
-#elif defined(CONFIG_MX53)
-#define MUX_I_START 0x0020
-#define PAD_I_START 0x348
-#define INPUT_CTL_START 0x730
-#define MUX_I_END (PAD_I_START - 4)
-#else
-#error "CPU_TYPE not defined"
-#endif
-
-#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
- (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
- ((mi) << MUX_I) | \
- ((pi - PAD_I_START) << PAD_I) | \
- ((ga) << GPIO_I))
-
-#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
- _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
-
-#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
- _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
-
-#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
-#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
-#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
-#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
-
-/*
- * This enumeration is constructed based on the Section
- * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
- * value is constructed based on the rules described above.
- */
-enum {
- MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
- MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
- MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
- MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
- MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
- MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
- MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
- MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
- MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
- MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
- MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
- MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
- MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
- MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
- MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
- MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
- MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
- MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
- MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
- MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
- MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
- MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
- MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
- MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
- MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
- MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
- MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
- MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
- MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
- MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
- MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
- MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
- MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
- MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
- MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
- MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
- MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
- MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
- MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
- MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
- MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
- MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
- MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
- MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
- MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
- MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
- MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
- MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
- MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
- MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
- MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
- MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
- MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
- MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
- MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
- MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
- MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
- MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
- MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
- MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
- MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
- MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
- MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
- MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
- MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
- MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
- MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
- MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
- MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
- MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
- MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
- MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
- MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
- MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
- MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
- MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
- MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
- MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
- MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
- MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
- MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
- MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
- MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
- MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
- MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
- MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
- MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
- MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
- MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
- MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
- MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
- MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
- MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
- MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
- MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
- MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
- MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
- MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
- MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
- MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
- MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
- MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
- MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
- MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
- MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
- MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
- MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
- MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
- MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
- MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
- MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
- MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
- MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
- MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
- MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
- MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
- MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
- MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
- MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
- MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
- MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
- MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
- MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
- MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
- MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
- MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
- MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
- MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
- MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
- MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
- MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
- MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
- MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
- MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
- MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
- MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
- MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
- MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
- MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
- MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
- MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
- MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
- MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
- MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
- MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
- MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
- MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
- MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
- MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
- MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
- MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
- MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
- MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
- MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
- MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
- MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
- MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
- MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
- MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
- MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
- MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
- MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
- MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
- MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
- MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
- MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
- MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
- MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
- MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
- MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
- MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
- MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
- MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
- MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
- MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
- MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
- MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
- MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
- MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
- MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
- MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
- MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
- MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
- MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
- MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
- MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
- MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
- MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
- MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
- MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
- MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
- MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
- MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
- MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
- MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
- MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
- MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
- MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
- MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
- MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
- MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
- MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
- MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
- MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
- MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
- MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
- MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
- MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
- MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
- MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
- MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
- MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
- MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
- MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
- MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
- MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
- MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
- MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
- MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
- MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
- MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
- MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
- MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
- MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
- MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
- MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
- MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
- MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
- MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
- MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
- MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
- MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
- MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
- MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
- MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
- MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
- MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
- MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
- MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
- MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
- MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
- MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
- MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
- MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
- MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
- MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
- MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
- MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
- MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
- MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
- MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
- MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
-
- /* The following are PADS used for drive strength */
-
- MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
- MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
- MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
- MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
- MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C),
- MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884),
- MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
- MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
- MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
- MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
- MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
- MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
- MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C),
- MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C),
- MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4),
- MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC),
- MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8),
- MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C),
- MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0),
- MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0),
- MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4),
- MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC),
- MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C),
- MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848),
- MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868),
- MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4),
- MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8),
- MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac),
- MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0),
- MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4),
- MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8),
- MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC),
- MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0),
- MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4),
- MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8),
- MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC),
- MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0),
- MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4),
- MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
- MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
- MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
-};
-
-enum {
- MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN(3, 5, 1, 0x20, 0x348),
- MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN(3, 6, 1, 0x24, 0x34C),
- MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN(3, 7, 1, 0x28, 0x350),
- MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN(3, 8, 1, 0x2C, 0x354),
- MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN(3, 9, 1, 0x30, 0x358),
- MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN(3, 10, 1, 0x34, 0x35C),
- MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN(3, 11, 1, 0x38, 0x360),
- MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN(3, 12, 1, 0x3C, 0x364),
- MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN(3, 13, 1, 0x40, 0x368),
- MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN(3, 14, 1, 0x44, 0x36C),
- MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN(3, 15, 1, 0x48, 0x370),
- MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x374),
- MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 1, 0x4C, 0x378),
- MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN(3, 17, 1, 0x50, 0x37C),
- MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN(3, 18, 1, 0x54, 0x380),
- MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN(3, 19, 1, 0x58, 0x384),
- MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN(3, 20, 1, 0x5C, 0x388),
- MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN(3, 21, 1, 0x60, 0x38C),
- MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN(3, 22, 1, 0x64, 0x390),
- MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN(3, 23, 1, 0x68, 0x394),
- MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN(3, 24, 1, 0x6C, 0x398),
- MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN(3, 25, 1, 0x70, 0x39C),
- MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN(3, 26, 1, 0x74, 0x3A0),
- MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN(3, 27, 1, 0x78, 0x3A4),
- MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN(3, 28, 1, 0x7C, 0x3A8),
- MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN(3, 29, 1, 0x80, 0x3AC),
- MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN(3, 30, 1, 0x84, 0x3B0),
- MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN(3, 31, 1, 0x88, 0x3B4),
- MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN(4, 5, 1, 0x8C, 0x3B8),
- MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN(4, 6, 1, 0x90, 0x3BC),
- MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN(4, 7, 1, 0x94, 0x3C0),
- MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN(4, 8, 1, 0x98, 0x3C4),
- MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN(4, 9, 1, 0x9C, 0x3C8),
- MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN(4, 10, 1, 0xA0, 0x3CC),
- MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN(4, 11, 1, 0xA4, 0x3D0),
- MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN(4, 12, 1, 0xA8, 0x3D4),
- MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN(4, 13, 1, 0xAC, 0x3D8),
- MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN(4, 14, 1, 0xB0, 0x3DC),
- MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN(4, 15, 1, 0xB4, 0x3E0),
- MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN(4, 16, 1, 0xB8, 0x3E4),
- MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN(4, 17, 1, 0xBC, 0x3E8),
- MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN(4, 18, 1, 0xC0, 0x3EC),
- MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN(4, 19, 1, 0xC4, 0x3F0),
- MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN(4, 20, 1, 0xC8, 0x3F4),
- MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN(4, 21, 1, 0xCC, 0x3F8),
- MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN(4, 22, 1, 0xD0, 0x3FC),
- MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN(4, 23, 1, 0xD4, 0x400),
- MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN(4, 24, 1, 0xD8, 0x404),
- MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN(4, 25, 1, 0xDC, 0x408),
- MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN(4, 26, 1, 0xE0, 0x40C),
- MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN(4, 27, 1, 0xE4, 0x410),
- MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN(4, 28, 1, 0xE8, 0x414),
- MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN(4, 29, 1, 0xEC, 0x418),
- MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN(4, 30, 1, 0xF0, 0x41C),
- MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN(4, 31, 1, 0xF4, 0x420),
- MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN(5, 0, 1, 0xF8, 0x424),
- MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN(5, 1, 1, 0xFC, 0x428),
- MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN(5, 2, 1, 0x100, 0x42C),
- MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN(5, 3, 1, 0x104, 0x430),
- MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN(5, 4, 1, 0x108, 0x434),
- MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN(5, 5, 1, 0x10C, 0x438),
- MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x43C),
- MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x440),
- MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x444),
- MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x448),
- MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x44C),
- MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x450),
- MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x454),
- MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(4, 2, 1, 0x110, 0x458),
- MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0x114, 0x45C),
- MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(2, 16, 1, 0x118, 0x460),
- MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(2, 17, 1, 0x11C, 0x464),
- MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(2, 18, 1, 0x120, 0x468),
- MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(2, 19, 1, 0x124, 0x46C),
- MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(2, 20, 1, 0x128, 0x470),
- MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(2, 21, 1, 0x12C, 0x474),
- MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(2, 22, 1, 0x130, 0x478),
- MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(2, 23, 1, 0x134, 0x47C),
- MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0x138, 0x480),
- MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(2, 24, 1, 0x13C, 0x484),
- MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN(2, 25, 1, 0x140, 0x488),
- MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN(2, 26, 1, 0x144, 0x48C),
- MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(2, 27, 1, 0x148, 0x490),
- MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN(2, 28, 1, 0x14C, 0x494),
- MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN(2, 29, 1, 0x150, 0x498),
- MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN(2, 30, 1, 0x154, 0x49C),
- MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN(2, 31, 1, 0x158, 0x4A0),
- MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4A4),
- MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(4, 4, 1, 0x15C, 0x4A8),
- MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(5, 6, 1, 0x160, 0x4AC),
- MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0x164, 0x4B0),
- MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0x168, 0x4B4),
- MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0x16C, 0x4B8),
- MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0x170, 0x4BC),
- MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0x174, 0x4C0),
- MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0x178, 0x4C4),
- MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0x17C, 0x4C8),
- MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0x180, 0x4CC),
- MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0x184, 0x4D0),
- MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0x188, 0x4D4),
- MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0x18C, 0x4D8),
- MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0x190, 0x4DC),
- MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x4E0),
- MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0x194, 0x4E4),
- MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0x198, 0x4E8),
- MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN(2, 0, 1, 0x19C, 0x4EC),
- MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0x1A0, 0x4F0),
- MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x1A4, 0x4F4),
- MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN(2, 3, 1, 0x1A8, 0x4F8),
- MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN(2, 4, 1, 0x1AC, 0x4FC),
- MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN(2, 5, 1, 0x1B0, 0x500),
- MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN(2, 6, 1, 0x1B4, 0x504),
- MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN(2, 7, 1, 0x1B8, 0x508),
- MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN(2, 8, 1, 0x1BC, 0x50C),
- MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN(2, 9, 1, 0x1C0, 0x510),
- MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN(2, 10, 1, 0x1C4, 0x514),
- MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN(2, 11, 1, 0x1C8, 0x518),
- MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN(2, 12, 1, 0x1CC, 0x51C),
- MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN(2, 13, 1, 0x1D0, 0x520),
- MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN(2, 14, 1, 0x1D4, 0x524),
- MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN(2, 15, 1, 0x1D8, 0x528),
- MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(5, 12, 1, 0x1DC, 0x52C),
- MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(5, 13, 1, 0x1E0, 0x530),
- MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN(4, 0, 1, 0x1E4, 0x534),
- MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x538),
- MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x53C),
- MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN(5, 22, 0, 0x1EC, NON_PAD_I),
- MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN(5, 24, 0, 0x1F0, NON_PAD_I),
- MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN(5, 26, 0, 0x1F4, NON_PAD_I),
- MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN(5, 28, 0, 0x1F8, NON_PAD_I),
- MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN(5, 30, 0, 0x1FC, NON_PAD_I),
- MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN(6, 22, 0, 0x200, NON_PAD_I),
- MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN(6, 24, 0, 0x204, NON_PAD_I),
- MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN(6, 26, 0, 0x208, NON_PAD_I),
- MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN(6, 28, 0, 0x20C, NON_PAD_I),
- MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN(6, 30, 0, 0x210, NON_PAD_I),
- MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN(3, 0, 0, 0x214, 0x540),
- MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN(3, 1, 0, 0x218, 0x544),
- MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN(3, 2, 0, 0x21C, 0x548),
- MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN(3, 3, 0, 0x220, 0x54C),
- MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN(3, 4, 0, 0x224, 0x550),
- MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x554),
- MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x558),
- MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x55C),
- MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x560),
- MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x564),
- MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x568),
- MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x56C),
- MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x570),
- MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x574),
- MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x578),
- MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x57C),
- MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x580),
- MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x584),
- MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x588),
- MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x58C),
- MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x590),
- MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x594),
- MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x598),
- MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x59C),
- MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(5, 7, 1, 0x228, 0x5A0),
- MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(5, 8 , 1, 0x22C, 0x5A4),
- MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(5, 9, 1, 0x230, 0x5A8),
- MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(5, 10, 1, 0x234, 0x5AC),
- MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(5, 11, 1, 0x238, 0x5B0),
- MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(5, 14, 1, 0x23C, 0x5B4),
- MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(5, 15, 1, 0x240, 0x5B8),
- MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(5, 16, 1, 0x244, 0x5BC),
- MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5C0),
- MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN(0, 22, 1, 0x248, 0x5C4),
- MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN(0, 23, 1, 0x24C, 0x5C8),
- MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN(0, 24, 1, 0x250, 0x5CC),
- MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN(0, 25, 1, 0x254, 0x5D0),
- MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN(0, 26, 1, 0x258, 0x5D4),
- MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN(0, 27, 1, 0x25C, 0x5D8),
- MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN(0, 28, 1, 0x260, 0x5DC),
- MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN(0, 29, 1, 0x264, 0x5E0),
- MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN(0, 30, 1, 0x268, 0x5E4),
- MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN(0, 31, 1, 0x26C, 0x5E8),
- MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5EC),
- MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN(5, 17, 1, 0x270, 0x5F0),
- MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN(5, 18, 1, 0x274, 0x5F4),
- MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN(6, 0, 1, 0x278, 0x5F8),
- MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN(6, 1, 1, 0x27C, 0x5FC),
- MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN(6, 2, 1, 0x280, 0x600),
- MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN(6, 3, 1, 0x284, 0x604),
- MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN(6, 4, 1, 0x288, 0x608),
- MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN(6, 5, 1, 0x28C, 0x60C),
- MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN(6, 6, 1, 0x290, 0x610),
- MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN(6, 7, 1, 0x294, 0x614),
- MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN(6, 8, 1, 0x298, 0x618),
- MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN(6, 9, 1, 0x29C, 0x61C),
- MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN(6, 10, 1, 0x2A0, 0x620),
- MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x624),
- MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x2A4, 0x628),
- MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x2A8, 0x62C),
- MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x2AC, 0x630),
- MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x2B0, 0x634),
- MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x2B4, 0x638),
- MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x2B8, 0x63C),
- MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x2BC, 0x640),
- MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x2C0, 0x644),
- MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x2C4, 0x648),
- MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x2C8, 0x64C),
- MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x2CC, 0x650),
- MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0x2D0, 0x654),
- MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0x2D4, 0x658),
- MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0x2D8, 0x65C),
- MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0x2DC, 0x660),
- MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0x2E0, 0x664),
- MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x668),
- MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 16, 1, 0x2E4, 0x66C),
- MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 17, 1, 0x2E8, 0x670),
- MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN(0, 18, 1, 0x2EC, 0x674),
- MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 19, 1, 0x2F0, 0x678),
- MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN(0, 20, 1, 0x2F4, 0x67C),
- MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 21, 1, 0x2F8, 0x680),
- MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x684),
- MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN(0, 10, 1, 0x2FC, 0x688),
- MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN(0, 11, 1, 0x300, 0x68C),
- MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN(0, 12, 1, 0x304, 0x690),
- MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 1, 0x308, 0x694),
- MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN(0, 14, 1, 0x30C, 0x698),
- MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN(0, 15, 1, 0x310, 0x69C),
- MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6A0),
- MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x314, 0x6A4),
- MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x318, 0x6A8),
- MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN(0, 9, 1, 0x31C, 0x6AC),
- MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN(0, 3, 1, 0x320, 0x6B0),
- MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN(0, 6, 1, 0x324, 0x6B4),
- MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN(0, 2, 1, 0x328, 0x6B8),
- MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN(0, 4, 1, 0x32C, 0x6BC),
- MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN(0, 5, 1, 0x330, 0x6C0),
- MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN(0, 7, 1, 0x334, 0x6C4),
- MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN(0, 8, 1, 0x338, 0x6C8),
- MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN(6, 11, 1, 0x33C, 0x6CC),
- MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN(6, 12, 1, 0x340, 0x6D0),
- MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN(6, 13, 1, 0x344, 0x6D4),
- MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6D8),
- MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6DC),
- MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E0),
- MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E4),
- MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6E8),
- MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6EC),
- MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F0),
- MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6F4),
- MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x6FC),
- MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x708),
- MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x70C),
- MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x710),
- MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x714),
- MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x718),
- MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x71C),
- MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x720),
- MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x724),
- MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x728),
- MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x72C),
-};
-/* various IOMUX input select register index */
-typedef enum iomux_input_select {
- MX51_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
- MX51_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
- MX51_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
- MX51_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
- MX51_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
- MX51_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
- MX51_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
- MX51_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
- MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
- MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
- MX51_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
- MX51_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
- MX51_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
- MX51_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
- MX51_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
- MX51_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
- MX51_CCM_IPP_DI_CLK_SELECT_INPUT,
- /* TO2 */
- MX51_CCM_IPP_DI1_CLK_SELECT_INPUT,
- MX51_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
- MX51_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
- MX51_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MX51_CSPI_IPP_IND_MISO_SELECT_INPUT,
- MX51_CSPI_IPP_IND_MOSI_SELECT_INPUT,
- MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
- MX51_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
- MX51_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
- MX51_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
- /* TO2 */
- MX51_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
- MX51_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
- MX51_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
- MX51_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
- MX51_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
- MX51_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
- MX51_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
- MX51_FEC_FEC_COL_SELECT_INPUT,
- MX51_FEC_FEC_CRS_SELECT_INPUT,
- MX51_FEC_FEC_MDI_SELECT_INPUT,
- MX51_FEC_FEC_RDATA_0_SELECT_INPUT,
- MX51_FEC_FEC_RDATA_1_SELECT_INPUT,
- MX51_FEC_FEC_RDATA_2_SELECT_INPUT,
- MX51_FEC_FEC_RDATA_3_SELECT_INPUT,
- MX51_FEC_FEC_RX_CLK_SELECT_INPUT,
- MX51_FEC_FEC_RX_DV_SELECT_INPUT,
- MX51_FEC_FEC_RX_ER_SELECT_INPUT,
- MX51_FEC_FEC_TX_CLK_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
- MX51_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
- /* TO2 */
- MX51_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
- MX51_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
- MX51_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
- /* TO2 */
- MX51_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
- /* TO2 */
- MX51_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
- MX51_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
- MX51_I2C1_IPP_SCL_IN_SELECT_INPUT,
- MX51_I2C1_IPP_SDA_IN_SELECT_INPUT,
- MX51_I2C2_IPP_SCL_IN_SELECT_INPUT,
- MX51_I2C2_IPP_SDA_IN_SELECT_INPUT,
- MX51_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
- MX51_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
- MX51_KPP_IPP_IND_COL_6_SELECT_INPUT,
- MX51_KPP_IPP_IND_COL_7_SELECT_INPUT,
- MX51_KPP_IPP_IND_ROW_4_SELECT_INPUT,
- MX51_KPP_IPP_IND_ROW_5_SELECT_INPUT,
- MX51_KPP_IPP_IND_ROW_6_SELECT_INPUT,
- MX51_KPP_IPP_IND_ROW_7_SELECT_INPUT,
- MX51_UART1_IPP_UART_RTS_B_SELECT_INPUT,
- MX51_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT,
- MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX51_UART3_IPP_UART_RTS_B_SELECT_INPUT,
- MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
- MX51_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
- MX51PUT_NUM_MUX,
- /* MX53 */
- MX53_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
- MX53_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
- MX53_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT,
- MX53_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT,
- MX53_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
- MX53_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
- MX53_AUDMUX_P5_INPUT_DA_AMX_SELECT_I,
- MX53_AUDMUX_P5_INPUT_DB_AMX_SELECT_I,
- MX53_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
- MX53_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT,
- MX53_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
- MX53_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
- MX53_CAN1_IPP_IND_CANRX_SELECT_INPUT,
- MX53_CAN2_IPP_IND_CANRX_SELECT_INPUT,
- MX53_CCM_IPP_ASRC_EXT_SELECT_INPUT,
- MX53_CCM_IPP_DI1_CLK_SELECT_INPUT,
- MX53_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
- MX53_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
- MX53_CCM_PLL3_BYPASS_CLK_SELECT_INPUT,
- MX53_CCM_PLL4_BYPASS_CLK_SELECT_INPUT,
- MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
- MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
- MX53_CSPI_IPP_IND_SS_B_0_SELECT_INPUT,
- MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
- MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
- MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
- MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
- MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,
- MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
- MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
- MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
- MX53_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT,
- MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SCKT_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
- MX53_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
- MX53_ESDHC1_IPP_WP_ON_SELECT_INPUT,
- MX53_FEC_FEC_COL_SELECT_INPUT,
- MX53_FEC_FEC_MDI_SELECT_INPUT,
- MX53_FEC_FEC_RX_CLK_SELECT_INPUT,
- MX53_FIRI_IPP_IND_RXD_SELECT_INPUT,
- MX53_GPC_PMIC_RDY_SELECT_INPUT,
- MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
- MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
- MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
- MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
- MX53_I2C3_IPP_SCL_IN_SELECT_INPUT,
- MX53_I2C3_IPP_SDA_IN_SELECT_INPUT,
- MX53_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
- MX53_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
- MX53_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
- MX53_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT,
- MX53_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT,
- MX53_KPP_IPP_IND_COL_5_SELECT_INPUT,
- MX53_KPP_IPP_IND_COL_6_SELECT_INPUT,
- MX53_KPP_IPP_IND_COL_7_SELECT_INPUT,
- MX53_KPP_IPP_IND_ROW_5_SELECT_INPUT,
- MX53_KPP_IPP_IND_ROW_6_SELECT_INPUT,
- MX53_KPP_IPP_IND_ROW_7_SELECT_INPUT,
- MX53_MLB_MLBCLK_IN_SELECT_INPUT,
- MX53_MLB_MLBDAT_IN_SELECT_INPUT,
- MX53_MLB_MLBSIG_IN_SELECT_INPUT,
- MX53_OWIRE_BATTERY_LINE_IN_SELECT_INPUT,
- MX53_SDMA_EVENTS_14_SELECT_INPUT,
- MX53_SDMA_EVENTS_15_SELECT_INPUT,
- MX53_SPDIF_SPDIF_IN1_SELECT_INPUT,
- MX53_UART1_IPP_UART_RTS_B_SELECT_INPUT,
- MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX53_UART2_IPP_UART_RTS_B_SELECT_INPUT,
- MX53_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX53_UART3_IPP_UART_RTS_B_SELECT_INPUT,
- MX53_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX53_UART4_IPP_UART_RTS_B_SELECT_INPUT,
- MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX53_UART5_IPP_UART_RTS_B_SELECT_INPUT,
- MX53_UART5_IPP_UART_RXD_MUX_SELECT_INPUT,
- MX53_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT,
- MX53_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT,
- MX53_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT,
-} iomux_input_select_t;
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx5/spl.h b/arch/arm/include/asm/arch-mx5/spl.h
new file mode 100644
index 0000000000..e0b6e3e5b2
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/spl.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_ARCH_SPL_H__
+#define __ASM_ARCH_SPL_H__
+
+#define BOOT_DEVICE_NONE 0
+#define BOOT_DEVICE_NAND 1
+
+#endif /* __ASM_ARCH_SPL_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index db377cc31d..cfd4edcb5e 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -61,6 +61,7 @@ enum mxc_clock {
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
+void enable_ocotp_clk(unsigned char enable);
void enable_usboh3_clk(unsigned char enable);
int enable_sata_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 76764571a7..aa9747ce33 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -20,6 +20,7 @@
#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
+#define CCM_CCOSR 0x020c4060
#define CCM_CCGR0 0x020C4068
#define CCM_CCGR1 0x020C406c
#define CCM_CCGR2 0x020C4070
@@ -244,7 +245,12 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+#ifdef CONFIG_MX6SL
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F
+#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
+#else
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
+#endif
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
/* Define the bits in register CS1CDR */
@@ -262,10 +268,13 @@ struct mxc_ccm_reg {
/* Define the bits in register CS2CDR */
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
@@ -412,183 +421,183 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR_CG_MASK 3
#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
-#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
-#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
-#define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4
-#define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA)
+#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
+#define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
+#define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
#define MXC_CCM_CCGR0_ASRC_OFFSET 6
-#define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET)
+#define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
-#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
-#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
-#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
#define MXC_CCM_CCGR0_CAN1_OFFSET 14
-#define MXC_CCM_CCGR0_CAN1_MASK (3<<MXC_CCM_CCGR0_CAN1_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
-#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
#define MXC_CCM_CCGR0_CAN2_OFFSET 18
-#define MXC_CCM_CCGR0_CAN2_MASK (3<<MXC_CCM_CCGR0_CAN2_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
-#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
-#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
#define MXC_CCM_CCGR0_DCIC1_OFFSET 24
-#define MXC_CCM_CCGR0_DCIC1_MASK (3<<MXC_CCM_CCGR0_DCIC1_OFFSET)
+#define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
#define MXC_CCM_CCGR0_DCIC2_OFFSET 26
-#define MXC_CCM_CCGR0_DCIC2_MASK (3<<MXC_CCM_CCGR0_DCIC2_OFFSET)
+#define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
#define MXC_CCM_CCGR0_DTCP_OFFSET 28
-#define MXC_CCM_CCGR0_DTCP_MASK (3<<MXC_CCM_CCGR0_DTCP_OFFSET)
+#define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
-#define MXC_CCM_CCGR1_ECSPI1S_MASK (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
-#define MXC_CCM_CCGR1_ECSPI2S_MASK (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
-#define MXC_CCM_CCGR1_ECSPI3S_MASK (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
-#define MXC_CCM_CCGR1_ECSPI4S_MASK (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
-#define MXC_CCM_CCGR1_ECSPI5S_MASK (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
-#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
-#define MXC_CCM_CCGR1_EPIT1S_MASK (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
-#define MXC_CCM_CCGR1_EPIT2S_MASK (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
#define MXC_CCM_CCGR1_ESAIS_OFFSET 16
-#define MXC_CCM_CCGR1_ESAIS_MASK (3<<MXC_CCM_CCGR1_ESAIS_OFFSET)
+#define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
-#define MXC_CCM_CCGR1_GPT_BUS_MASK (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
-#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
#define MXC_CCM_CCGR1_GPU2D_OFFSET 24
-#define MXC_CCM_CCGR1_GPU2D_MASK (3<<MXC_CCM_CCGR1_GPU2D_OFFSET)
+#define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
#define MXC_CCM_CCGR1_GPU3D_OFFSET 26
-#define MXC_CCM_CCGR1_GPU3D_MASK (3<<MXC_CCM_CCGR1_GPU3D_OFFSET)
+#define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
-#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
-#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
-#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
-#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
-#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
-#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
+#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
-#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
-#define MXC_CCM_CCGR2_IPMUX1_MASK (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
-#define MXC_CCM_CCGR2_IPMUX2_MASK (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
-#define MXC_CCM_CCGR2_IPMUX3_MASK (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
-#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
-#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
-#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
-#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
-#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
-#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
-#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
-#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
-#define MXC_CCM_CCGR3_LDB_DI0_MASK (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
-#define MXC_CCM_CCGR3_LDB_DI1_MASK (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
-#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
#define MXC_CCM_CCGR3_MLB_OFFSET 18
-#define MXC_CCM_CCGR3_MLB_MASK (3<<MXC_CCM_CCGR3_MLB_OFFSET)
+#define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
-#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
-#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
-#define MXC_CCM_CCGR3_OCRAM_MASK (3<<MXC_CCM_CCGR3_OCRAM_OFFSET)
+#define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
-#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
+#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
#define MXC_CCM_CCGR4_PCIE_OFFSET 0
-#define MXC_CCM_CCGR4_PCIE_MASK (3<<MXC_CCM_CCGR4_PCIE_OFFSET)
+#define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
-#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
-#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
-#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
#define MXC_CCM_CCGR4_PWM1_OFFSET 16
-#define MXC_CCM_CCGR4_PWM1_MASK (3<<MXC_CCM_CCGR4_PWM1_OFFSET)
+#define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
#define MXC_CCM_CCGR4_PWM2_OFFSET 18
-#define MXC_CCM_CCGR4_PWM2_MASK (3<<MXC_CCM_CCGR4_PWM2_OFFSET)
+#define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
#define MXC_CCM_CCGR4_PWM3_OFFSET 20
-#define MXC_CCM_CCGR4_PWM3_MASK (3<<MXC_CCM_CCGR4_PWM3_OFFSET)
+#define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
#define MXC_CCM_CCGR4_PWM4_OFFSET 22
-#define MXC_CCM_CCGR4_PWM4_MASK (3<<MXC_CCM_CCGR4_PWM4_OFFSET)
+#define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
-#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
-#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
#define MXC_CCM_CCGR5_ROM_OFFSET 0
-#define MXC_CCM_CCGR5_ROM_MASK (3<<MXC_CCM_CCGR5_ROM_OFFSET)
+#define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
#define MXC_CCM_CCGR5_SATA_OFFSET 4
-#define MXC_CCM_CCGR5_SATA_MASK (3<<MXC_CCM_CCGR5_SATA_OFFSET)
+#define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
#define MXC_CCM_CCGR5_SDMA_OFFSET 6
-#define MXC_CCM_CCGR5_SDMA_MASK (3<<MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
#define MXC_CCM_CCGR5_SPBA_OFFSET 12
-#define MXC_CCM_CCGR5_SPBA_MASK (3<<MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
#define MXC_CCM_CCGR5_SPDIF_OFFSET 14
-#define MXC_CCM_CCGR5_SPDIF_MASK (3<<MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
#define MXC_CCM_CCGR5_SSI1_OFFSET 18
-#define MXC_CCM_CCGR5_SSI1_MASK (3<<MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
#define MXC_CCM_CCGR5_SSI2_OFFSET 20
-#define MXC_CCM_CCGR5_SSI2_MASK (3<<MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
#define MXC_CCM_CCGR5_SSI3_OFFSET 22
-#define MXC_CCM_CCGR5_SSI3_MASK (3<<MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
#define MXC_CCM_CCGR5_UART_OFFSET 24
-#define MXC_CCM_CCGR5_UART_MASK (3<<MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
-#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
-#define MXC_CCM_CCGR6_USBOH3_MASK (3<<MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
-#define MXC_CCM_CCGR6_USDHC1_MASK (3<<MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
-#define MXC_CCM_CCGR6_USDHC2_MASK (3<<MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
-#define MXC_CCM_CCGR6_USDHC3_MASK (3<<MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
-#define MXC_CCM_CCGR6_USDHC4_MASK (3<<MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
-#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
-#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
#define BP_ANADIG_PLL_SYS_RSVD0 20
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index d79ab2f13f..03abb2a8b7 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -25,6 +25,13 @@
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
+
+#ifdef CONFIG_MX6SL
+#define GPU_2D_ARB_BASE_ADDR 0x02200000
+#define GPU_2D_ARB_END_ADDR 0x02203FFF
+#define OPENVG_ARB_BASE_ADDR 0x02204000
+#define OPENVG_ARB_END_ADDR 0x02207FFF
+#else
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00103FFF
#define APBH_DMA_ARB_BASE_ADDR 0x00110000
@@ -37,9 +44,19 @@
#define GPU_2D_ARB_END_ADDR 0x00137FFF
#define DTCP_ARB_BASE_ADDR 0x00138000
#define DTCP_ARB_END_ADDR 0x0013BFFF
+#endif /* CONFIG_MX6SL */
+
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */
+#ifdef CONFIG_MX6SL
+#define GPV2_BASE_ADDR 0x00D00000
+#else
#define GPV2_BASE_ADDR 0x00200000
+#endif
+
#define GPV3_BASE_ADDR 0x00300000
#define GPV4_BASE_ADDR 0x00800000
#define IRAM_BASE_ADDR 0x00900000
@@ -70,10 +87,17 @@
#define WEIM_ARB_BASE_ADDR 0x08000000
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
+#ifdef CONFIG_MX6SL
+#define MMDC0_ARB_BASE_ADDR 0x80000000
+#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
+#define MMDC1_ARB_BASE_ADDR 0xC0000000
+#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
+#else
#define MMDC0_ARB_BASE_ADDR 0x10000000
#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
#define MMDC1_ARB_BASE_ADDR 0x80000000
#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
+#endif
#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
#define IPU_SOC_OFFSET 0x00200000
@@ -89,6 +113,16 @@
#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
+#ifdef CONFIG_MX6SL
+#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
+#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
+#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
+#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
+#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
+#else
#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
@@ -96,6 +130,8 @@
#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#endif
+
#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
@@ -128,18 +164,35 @@
#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
+#ifdef CONFIG_MX6SL
+#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
+#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#else
#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#endif
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
+#ifdef CONFIG_MX6SL
+#define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
+#else
#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
+#endif
+
#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
+#ifdef CONFIG_MX6SL
+#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
+#else
#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
+#endif
+
#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
@@ -149,7 +202,12 @@
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
+#ifdef CONFIG_MX6SL
+#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#else
#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#endif
+
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
@@ -171,7 +229,6 @@
#define CHIP_REV_1_0 0x10
#define IRAM_SIZE 0x00040000
-#define IMX_IIM_BASE OCOTP_BASE_ADDR
#define FEC_QUIRK_ENET_MAC
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
@@ -200,12 +257,6 @@ struct src {
u32 gpr10;
};
-/* OCOTP Registers */
-struct ocotp_regs {
- u32 reserved[0x198];
- u32 gp1; /* 0x660 */
-};
-
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
@@ -365,14 +416,22 @@ struct cspi_regs {
#define MXC_CSPICON_POL 4
#define MXC_CSPICON_PHA 0
#define MXC_CSPICON_SSPOL 12
+#ifdef CONFIG_MX6SL
+#define MXC_SPI_BASE_ADDRESSES \
+ ECSPI1_BASE_ADDR, \
+ ECSPI2_BASE_ADDR, \
+ ECSPI3_BASE_ADDR, \
+ ECSPI4_BASE_ADDR
+#else
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
ECSPI3_BASE_ADDR, \
ECSPI4_BASE_ADDR, \
ECSPI5_BASE_ADDR
+#endif
-struct iim_regs {
+struct ocotp_regs {
u32 ctrl;
u32 ctrl_set;
u32 ctrl_clr;
@@ -383,9 +442,9 @@ struct iim_regs {
u32 rsvd1[3];
u32 read_ctrl;
u32 rsvd2[3];
- u32 fuse_data;
+ u32 read_fuse_data;
u32 rsvd3[3];
- u32 sticky;
+ u32 sw_sticky;
u32 rsvd4[3];
u32 scs;
u32 scs_set;
@@ -400,7 +459,16 @@ struct iim_regs {
struct fuse_bank {
u32 fuse_regs[0x20];
- } bank[15];
+ } bank[16];
+};
+
+struct fuse_bank0_regs {
+ u32 lock;
+ u32 rsvd0[3];
+ u32 uid_low;
+ u32 rsvd1[3];
+ u32 uid_high;
+ u32 rsvd2[0x17];
};
struct fuse_bank4_regs {
@@ -411,7 +479,11 @@ struct fuse_bank4_regs {
u32 mac_addr_low;
u32 rsvd2[3];
u32 mac_addr_high;
- u32 rsvd3[0x13];
+ u32 rsvd3[0xb];
+ u32 gp1;
+ u32 rsvd4[3];
+ u32 gp2;
+ u32 rsvd5[3];
};
struct aipstz_regs {
diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
index 63f485666a..ce865a6b8f 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -24,7 +24,11 @@
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#include "mx6dl_pins.h"
#else
+#if defined(CONFIG_MX6SL)
+#include "mx6sl_pins.h"
+#else
#error "Please select cpu"
+#endif /* CONFIG_MX6SL */
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index 9846f1bcb5..a4134a0d09 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -22,33 +22,6 @@
#include <asm/imx-common/iomux-v3.h>
-/* Use to set PAD control */
-#define PAD_CTL_HYS (1 << 16)
-#define PAD_CTL_PUS_100K_DOWN (0 << 14)
-#define PAD_CTL_PUS_47K_UP (1 << 14)
-#define PAD_CTL_PUS_100K_UP (2 << 14)
-#define PAD_CTL_PUS_22K_UP (3 << 14)
-
-#define PAD_CTL_PUE (1 << 13)
-#define PAD_CTL_PKE (1 << 12)
-#define PAD_CTL_ODE (1 << 11)
-#define PAD_CTL_SPEED_LOW (1 << 6)
-#define PAD_CTL_SPEED_MED (2 << 6)
-#define PAD_CTL_SPEED_HIGH (3 << 6)
-#define PAD_CTL_DSE_DISABLE (0 << 3)
-#define PAD_CTL_DSE_240ohm (1 << 3)
-#define PAD_CTL_DSE_120ohm (2 << 3)
-#define PAD_CTL_DSE_80ohm (3 << 3)
-#define PAD_CTL_DSE_60ohm (4 << 3)
-#define PAD_CTL_DSE_48ohm (5 << 3)
-#define PAD_CTL_DSE_40ohm (6 << 3)
-#define PAD_CTL_DSE_34ohm (7 << 3)
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
-#define IOMUX_CONFIG_SION 0x10
-#define NO_MUX_I 0
-#define NO_PAD_I 0
enum {
MX6_PAD_CSI0_DAT10__UART1_TXD = IOMUX_PAD(0x0360, 0x004C, 3, 0x0000, 0, 0),
MX6_PAD_CSI0_DAT11__UART1_RXD = IOMUX_PAD(0x0364, 0x0050, 3, 0x08FC, 1, 0),
@@ -93,6 +66,7 @@ enum {
MX6_PAD_EIM_D28__I2C1_SDA = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
MX6_PAD_EIM_D28__GPIO_3_28 = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
MX6_PAD_EIM_D29__GPIO_3_29 = IOMUX_PAD(0x0548, 0x0178, 5, 0x0000, 0, 0),
+ MX6_PAD_EIM_DA9__GPIO_3_9 = IOMUX_PAD(0x0590, 0x01C0, 5, 0x0000, 0, 0),
MX6_PAD_ENET_MDC__ENET_MDC = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
@@ -102,6 +76,7 @@ enum {
MX6_PAD_GPIO_17__GPIO_7_12 = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_18__GPIO_7_13 = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_19__GPIO_4_5 = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+ MX6_PAD_GPIO_2__GPIO_1_2 = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_5__GPIO_1_5 = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
MX6_PAD_GPIO_5__I2C3_SCL = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
@@ -134,8 +109,14 @@ enum {
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, 0),
+ MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
MX6_PAD_SD1_CMD__GPIO_1_18 = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
MX6_PAD_SD1_DAT3__GPIO_1_21 = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, 0),
MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 1c1c00855f..02a40d4f5c 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -24,33 +24,6 @@
#include <asm/imx-common/iomux-v3.h>
-/* Use to set PAD control */
-#define PAD_CTL_HYS (1 << 16)
-#define PAD_CTL_PUS_100K_DOWN (0 << 14)
-#define PAD_CTL_PUS_47K_UP (1 << 14)
-#define PAD_CTL_PUS_100K_UP (2 << 14)
-#define PAD_CTL_PUS_22K_UP (3 << 14)
-
-#define PAD_CTL_PUE (1 << 13)
-#define PAD_CTL_PKE (1 << 12)
-#define PAD_CTL_ODE (1 << 11)
-#define PAD_CTL_SPEED_LOW (1 << 6)
-#define PAD_CTL_SPEED_MED (2 << 6)
-#define PAD_CTL_SPEED_HIGH (3 << 6)
-#define PAD_CTL_DSE_DISABLE (0 << 3)
-#define PAD_CTL_DSE_240ohm (1 << 3)
-#define PAD_CTL_DSE_120ohm (2 << 3)
-#define PAD_CTL_DSE_80ohm (3 << 3)
-#define PAD_CTL_DSE_60ohm (4 << 3)
-#define PAD_CTL_DSE_48ohm (5 << 3)
-#define PAD_CTL_DSE_40ohm (6 << 3)
-#define PAD_CTL_DSE_34ohm (7 << 3)
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
-
-#define NO_MUX_I 0
-#define NO_PAD_I 0
-
enum {
MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT1__ECSPI5_SS0 = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
new file mode 100644
index 0000000000..3c0ede0e5d
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6SL_PINS_H__
+#define __ASM_ARCH_MX6_MX6SL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+enum {
+ MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
+ MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
+ MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
+};
+#endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 3193297610..38e4e516eb 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -24,6 +24,8 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
+#include <asm/imx-common/regs-common.h>
+
#define MXC_CPU_MX51 0x51
#define MXC_CPU_MX53 0x53
#define MXC_CPU_MX6SL 0x60
@@ -46,4 +48,12 @@ void set_vddsoc(u32 mv);
int fecmxc_initialize(bd_t *bis);
u32 get_ahb_clk(void);
u32 get_periph_clk(void);
+
+int mxs_reset_block(struct mxs_register_32 *reg);
+int mxs_wait_mask_set(struct mxs_register_32 *reg,
+ uint32_t mask,
+ unsigned int timeout);
+int mxs_wait_mask_clr(struct mxs_register_32 *reg,
+ uint32_t mask,
+ unsigned int timeout);
#endif
diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h
index 3f7d3f0de5..9be53f0a71 100644
--- a/arch/arm/include/asm/arch-mxs/clock.h
+++ b/arch/arm/include/asm/arch-mxs/clock.h
@@ -59,6 +59,7 @@ uint32_t mxc_get_clock(enum mxc_clock clk);
void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
+void mxs_set_lcdclk(uint32_t freq);
/* Compatibility with the FEC Ethernet driver */
#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK)
diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h
index 8f67497760..dc21e34012 100644
--- a/arch/arm/include/asm/arch-mxs/imx-regs.h
+++ b/arch/arm/include/asm/arch-mxs/imx-regs.h
@@ -23,11 +23,11 @@
#ifndef __IMX_REGS_H__
#define __IMX_REGS_H__
-#include <asm/arch/regs-apbh.h>
+#include <asm/imx-common/regs-apbh.h>
#include <asm/arch/regs-base.h>
-#include <asm/arch/regs-bch.h>
+#include <asm/imx-common/regs-bch.h>
#include <asm/arch/regs-digctl.h>
-#include <asm/arch/regs-gpmi.h>
+#include <asm/imx-common/regs-gpmi.h>
#include <asm/arch/regs-i2c.h>
#include <asm/arch/regs-lcdif.h>
#include <asm/arch/regs-lradc.h>
diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h
index 42887154c4..d919fb239a 100644
--- a/arch/arm/include/asm/arch-mxs/iomux.h
+++ b/arch/arm/include/asm/arch-mxs/iomux.h
@@ -71,7 +71,11 @@ typedef u32 iomux_cfg_t;
#define PAD_16MA 3
#define PAD_1V8 0
+#if defined(CONFIG_MX28)
#define PAD_3V3 1
+#else
+#define PAD_3V3 0
+#endif
#define PAD_NOPULL 0
#define PAD_PULLUP 1
diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
index 62810eca41..c3cba337f9 100644
--- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h
@@ -26,7 +26,7 @@
#ifndef __MX23_REGS_CLKCTRL_H__
#define __MX23_REGS_CLKCTRL_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
index 23e9adc25a..1c2c82e1bd 100644
--- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
@@ -26,7 +26,7 @@
#ifndef __MX28_REGS_CLKCTRL_H__
#define __MX28_REGS_CLKCTRL_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-digctl.h b/arch/arm/include/asm/arch-mxs/regs-digctl.h
index d0433254d5..d4a39668b0 100644
--- a/arch/arm/include/asm/arch-mxs/regs-digctl.h
+++ b/arch/arm/include/asm/arch-mxs/regs-digctl.h
@@ -22,7 +22,7 @@
#ifndef __MX28_REGS_DIGCTL_H__
#define __MX28_REGS_DIGCTL_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_digctl_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-i2c.h b/arch/arm/include/asm/arch-mxs/regs-i2c.h
index 067cfd3947..d062b5be24 100644
--- a/arch/arm/include/asm/arch-mxs/regs-i2c.h
+++ b/arch/arm/include/asm/arch-mxs/regs-i2c.h
@@ -23,7 +23,7 @@
#ifndef __MX28_REGS_I2C_H__
#define __MX28_REGS_I2C_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_i2c_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-lcdif.h b/arch/arm/include/asm/arch-mxs/regs-lcdif.h
index b90b2d437a..59ce23683d 100644
--- a/arch/arm/include/asm/arch-mxs/regs-lcdif.h
+++ b/arch/arm/include/asm/arch-mxs/regs-lcdif.h
@@ -26,16 +26,23 @@
#ifndef __MX28_REGS_LCDIF_H__
#define __MX28_REGS_LCDIF_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
+#if defined(CONFIG_MX28)
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
- mxs_reg_32(hw_lcdif_transfer_count) /* 0x30 */
- mxs_reg_32(hw_lcdif_cur_buf) /* 0x40 */
- mxs_reg_32(hw_lcdif_next_buf) /* 0x50 */
+#endif
+ mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */
+ mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */
+ mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */
+
+#if defined(CONFIG_MX23)
+ uint32_t reserved1[4];
+#endif
+
mxs_reg_32(hw_lcdif_timing) /* 0x60 */
mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
@@ -54,13 +61,19 @@ struct mxs_lcdif_regs {
mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
- mxs_reg_32(hw_lcdif_data) /* 0x180 */
- mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */
+
+#if defined(CONFIG_MX23)
+ uint32_t reserved2[12];
+#endif
+ mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
+ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
+#if defined(CONFIG_MX28)
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
- mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */
- mxs_reg_32(hw_lcdif_version) /* 0x1c0 */
- mxs_reg_32(hw_lcdif_debug0) /* 0x1d0 */
- mxs_reg_32(hw_lcdif_debug1) /* 0x1e0 */
+#endif
+ mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */
+ mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */
+ mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */
+ mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */
mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
};
#endif
@@ -191,8 +204,13 @@ struct mxs_lcdif_regs {
#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
+#if defined(CONFIG_MX23)
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24)
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24
+#elif defined(CONFIG_MX28)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
+#endif
#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
diff --git a/arch/arm/include/asm/arch-mxs/regs-lradc.h b/arch/arm/include/asm/arch-mxs/regs-lradc.h
index 28d8382422..23fd0e3ac1 100644
--- a/arch/arm/include/asm/arch-mxs/regs-lradc.h
+++ b/arch/arm/include/asm/arch-mxs/regs-lradc.h
@@ -26,7 +26,7 @@
#ifndef __MX28_REGS_LRADC_H__
#define __MX28_REGS_LRADC_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_lradc_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-ocotp.h b/arch/arm/include/asm/arch-mxs/regs-ocotp.h
index 3269892f99..5af3855b58 100644
--- a/arch/arm/include/asm/arch-mxs/regs-ocotp.h
+++ b/arch/arm/include/asm/arch-mxs/regs-ocotp.h
@@ -26,7 +26,7 @@
#ifndef __MX28_REGS_OCOTP_H__
#define __MX28_REGS_OCOTP_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_ocotp_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
index d5841709c4..191093bf1e 100644
--- a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
+++ b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h
@@ -26,7 +26,7 @@
#ifndef __MX28_REGS_PINCTRL_H__
#define __MX28_REGS_PINCTRL_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_pinctrl_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
index 51a981a7c6..a7430c4efd 100644
--- a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
+++ b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h
@@ -22,7 +22,7 @@
#ifndef __MX23_REGS_POWER_H__
#define __MX23_REGS_POWER_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_power_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h
index 257ee88e82..4a73b1c650 100644
--- a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h
+++ b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h
@@ -22,7 +22,7 @@
#ifndef __MX28_REGS_POWER_H__
#define __MX28_REGS_POWER_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_power_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-rtc.h b/arch/arm/include/asm/arch-mxs/regs-rtc.h
index 6b2dd332e3..19265465c7 100644
--- a/arch/arm/include/asm/arch-mxs/regs-rtc.h
+++ b/arch/arm/include/asm/arch-mxs/regs-rtc.h
@@ -23,7 +23,7 @@
#ifndef __MX28_REGS_RTC_H__
#define __MX28_REGS_RTC_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_rtc_regs {
diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h
index 5920f9b4dc..0b61fa9d57 100644
--- a/arch/arm/include/asm/arch-mxs/regs-ssp.h
+++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h
@@ -25,7 +25,7 @@
#ifndef __MX28_REGS_SSP_H__
#define __MX28_REGS_SSP_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
#if defined(CONFIG_MX23)
diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h
index f8537f1636..df343bd6be 100644
--- a/arch/arm/include/asm/arch-mxs/regs-timrot.h
+++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h
@@ -25,7 +25,7 @@
#ifndef __MX28_REGS_TIMROT_H__
#define __MX28_REGS_TIMROT_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_timrot_regs {
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index ad984da0b4..e9a6ffeb83 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -143,40 +143,4 @@ struct s32ktimer {
#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
-/* Temporary SRAM stack used while low level init is done */
-#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
-/* SRAM scratch space entries */
-#define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
-#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
-#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
-#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
-#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
-#define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
-#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
-
-/* ROM code defines */
-/* Boot device */
-#define BOOT_DEVICE_MASK 0xFF
-#define BOOT_DEVICE_OFFSET 0x8
-#define DEV_DESC_PTR_OFFSET 0x4
-#define DEV_DATA_PTR_OFFSET 0x18
-#define BOOT_MODE_OFFSET 0x8
-#define RESET_REASON_OFFSET 0x9
-#define CH_FLAGS_OFFSET 0xA
-
-#define CH_FLAGS_CHSETTINGS (0x1 << 0)
-#define CH_FLAGS_CHRAM (0x1 << 1)
-#define CH_FLAGS_CHFLASH (0x1 << 2)
-#define CH_FLAGS_CHMMCSD (0x1 << 3)
-
-#ifndef __ASSEMBLY__
-struct omap_boot_parameters {
- char *boot_message;
- unsigned int mem_boot_descriptor;
- unsigned char omap_bootdevice;
- unsigned char reset_reason;
- unsigned char ch_flags;
-};
-#endif
#endif
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index d5f1868eee..039a1f2604 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -27,6 +27,8 @@
#include <asm/omap_common.h>
#include <asm/arch/mux_omap4.h>
+DECLARE_GLOBAL_DATA_PTR;
+
struct omap_sysinfo {
char *board_string;
};
@@ -58,13 +60,7 @@ void omap_vc_init(u16 speed_khz);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
-/*
- * This is used to verify if the configuration header
- * was executed by Romcode prior to control of transfer
- * to the bootloader. SPL is responsible for saving and
- * passing this to the u-boot.
- */
-extern struct omap_boot_parameters boot_params;
+void setup_warmreset_time(void);
static inline u32 running_from_sdram(void)
{
@@ -84,7 +80,7 @@ static inline u8 uboot_loaded_by_spl(void)
* variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
* mandatory section if CH is present.
*/
- if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
+ if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
return 0;
else
return running_from_sdram();
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index cfde374333..68afa76696 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -190,6 +190,10 @@
#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
+/* PRM_RSTTIME */
+#define RSTTIME1_SHIFT 0
+#define RSTTIME1_MASK (0x3ff << 0)
+
/* Clock frequencies */
#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
@@ -251,4 +255,10 @@
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
+/*
+ * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
+ * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
+ * into microsec and passing the value.
+ */
+#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
#endif /* _CLOCKS_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 5e62013236..044ab5581a 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -142,6 +142,8 @@ struct watchdog {
#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000)
#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000)
#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4 (OMAP54XX_L4_PER_BASE + 0x7A000)
+#define I2C_BASE5 (OMAP54XX_L4_PER_BASE + 0x7C000)
/* MUSB base */
#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000)
diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h
index 68be03be58..ec39a5318d 100644
--- a/arch/arm/include/asm/arch-omap5/i2c.h
+++ b/arch/arm/include/asm/arch-omap5/i2c.h
@@ -23,7 +23,7 @@
#ifndef _OMAP5_I2C_H_
#define _OMAP5_I2C_H_
-#define I2C_BUS_MAX 3
+#define I2C_BUS_MAX 5
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 887fcaa5ff..4f43a903d8 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -191,19 +191,6 @@ struct s32ktimer {
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
-#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
-/*
- * SRAM scratch space entries
- */
-#define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR
-#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
-#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
-#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
-#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
-#define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
-#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
-
/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
#define OMAP4430_ES1_0 0x44300100
@@ -214,21 +201,6 @@ struct s32ktimer {
#define OMAP4460_ES1_0 0x44600100
#define OMAP4460_ES1_1 0x44600110
-/* ROM code defines */
-/* Boot device */
-#define BOOT_DEVICE_MASK 0xFF
-#define BOOT_DEVICE_OFFSET 0x8
-#define DEV_DESC_PTR_OFFSET 0x4
-#define DEV_DATA_PTR_OFFSET 0x18
-#define BOOT_MODE_OFFSET 0x8
-#define RESET_REASON_OFFSET 0x9
-#define CH_FLAGS_OFFSET 0xA
-
-#define CH_FLAGS_CHSETTINGS (0x1 << 0)
-#define CH_FLAGS_CHRAM (0x1 << 1)
-#define CH_FLAGS_CHFLASH (0x1 << 2)
-#define CH_FLAGS_CHMMCSD (0x1 << 3)
-
/* CONTROL_SRCOMP_XXX_SIDE */
#define OVERRIDE_XS_SHIFT 30
#define OVERRIDE_XS_MASK (1 << 30)
@@ -249,14 +221,6 @@ struct srcomp_params {
s8 multiply_factor;
};
-struct omap_boot_parameters {
- char *boot_message;
- unsigned int mem_boot_descriptor;
- unsigned char omap_bootdevice;
- unsigned char reset_reason;
- unsigned char ch_flags;
-};
-
struct ctrl_ioregs {
u32 ctrl_ddrch;
u32 ctrl_lpddr2ch;
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index e66ab44341..b79161d79a 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -27,6 +27,8 @@
#include <asm/omap_common.h>
#include <asm/arch/clocks.h>
+DECLARE_GLOBAL_DATA_PTR;
+
struct pad_conf_entry {
u32 offset;
u32 val;
@@ -64,14 +66,7 @@ u32 warm_reset(void);
void force_emif_self_refresh(void);
void get_ioregs(const struct ctrl_ioregs **regs);
void srcomp_enable(void);
-
-/*
- * This is used to verify if the configuration header
- * was executed by Romcode prior to control of transfer
- * to the bootloader. SPL is responsible for saving and
- * passing this to the u-boot.
- */
-extern struct omap_boot_parameters boot_params;
+void setup_warmreset_time(void);
static inline u32 running_from_sdram(void)
{
@@ -91,7 +86,7 @@ static inline u8 uboot_loaded_by_spl(void)
* variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
* mandatory section if CH is present.
*/
- if ((boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
+ if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
return 0;
else
return running_from_sdram();
@@ -122,4 +117,13 @@ static inline u32 omap_hw_init_context(void)
#endif
}
+static inline u32 div_round_up(u32 num, u32 den)
+{
+ return (num + den - 1)/den;
+}
+
+static inline u32 usec_to_32k(u32 usec)
+{
+ return div_round_up(32768 * usec, 1000000);
+}
#endif
diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h
index 44b800f681..2397bcef0d 100644
--- a/arch/arm/include/asm/arch-pxa/hardware.h
+++ b/arch/arm/include/asm/arch-pxa/hardware.h
@@ -77,17 +77,6 @@
#define GPIO_FALLING_EDGE 1
#define GPIO_RISING_EDGE 2
#define GPIO_BOTH_EDGES 3
-extern void set_GPIO_IRQ_edge( int gpio_nr, int edge_mask );
-
-/*
- * Handy routine to set GPIO alternate functions
- */
-extern void set_GPIO_mode( int gpio_mode );
-
-/*
- * return current lclk frequency in units of 10kHz
- */
-extern unsigned int get_lclk_frequency_10khz(void);
#endif
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 3e642e92f8..5fe4838d9b 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -72,6 +72,7 @@ struct timerus {
/* These are the available SKUs (product types) for Tegra */
enum {
+ SKU_ID_T20_7 = 0x7,
SKU_ID_T20 = 0x8,
SKU_ID_T25SE = 0x14,
SKU_ID_AP25 = 0x17,
@@ -81,6 +82,7 @@ enum {
SKU_ID_T33 = 0x80,
SKU_ID_T30 = 0x81, /* Cardhu value */
SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
+ SKU_ID_T114_1 = 0x01,
};
/*
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index d0c69da971..8b8a91ae65 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -23,16 +23,28 @@
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
-#define XPSS_SYS_CTRL_BASEADDR 0xF8000000
-#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
-#define XPSS_SCU_BASEADDR 0xF8F00000
+#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
+#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
+#define ZYNQ_SCU_BASEADDR 0xF8F00000
+#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
+#define ZYNQ_GEM_BASEADDR0 0xE000B000
+#define ZYNQ_GEM_BASEADDR1 0xE000C000
+#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
+#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
+#define ZYNQ_I2C_BASEADDR0 0xE0004000
+#define ZYNQ_I2C_BASEADDR1 0xE0005000
/* Reflect slcr offsets */
struct slcr_regs {
u32 scl; /* 0x0 */
u32 slcr_lock; /* 0x4 */
u32 slcr_unlock; /* 0x8 */
- u32 reserved1[125];
+ u32 reserved0[75];
+ u32 gem0_rclk_ctrl; /* 0x138 */
+ u32 gem1_rclk_ctrl; /* 0x13c */
+ u32 gem0_clk_ctrl; /* 0x140 */
+ u32 gem1_clk_ctrl; /* 0x144 */
+ u32 reserved1[46];
u32 pss_rst_ctrl; /* 0x200 */
u32 reserved2[15];
u32 fpga_rst_ctrl; /* 0x240 */
@@ -41,15 +53,21 @@ struct slcr_regs {
u32 boot_mode; /* 0x25c */
u32 reserved4[116];
u32 trust_zone; /* 0x430 */ /* FIXME */
- u32 reserved5[115];
+ u32 reserved5_1[63];
+ u32 pss_idcode; /* 0x530 */
+ u32 reserved5_2[51];
u32 ddr_urgent; /* 0x600 */
u32 reserved6[6];
u32 ddr_urgent_sel; /* 0x61c */
- u32 reserved7[188];
+ u32 reserved7[56];
+ u32 mio_pin[54]; /* 0x700 - 0x7D4 */
+ u32 reserved8[74];
+ u32 lvl_shftr_en; /* 0x900 */
+ u32 reserved9[3];
u32 ocm_cfg; /* 0x910 */
};
-#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
+#define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
struct devcfg_regs {
u32 ctrl; /* 0x0 */
@@ -72,7 +90,7 @@ struct devcfg_regs {
u32 read_count; /* 0x8c */
};
-#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
+#define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
struct scu_regs {
u32 reserved1[16];
@@ -80,6 +98,6 @@ struct scu_regs {
u32 filter_end; /* 0x44 */
};
-#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
+#define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index e78890011a..2317121ca6 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -26,5 +26,12 @@
extern void zynq_slcr_lock(void);
extern void zynq_slcr_unlock(void);
extern void zynq_slcr_cpu_reset(void);
+extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk);
+extern void zynq_slcr_devcfg_disable(void);
+extern void zynq_slcr_devcfg_enable(void);
+extern u32 zynq_slcr_get_idcode(void);
+
+/* Driver extern functions */
+extern int zynq_sdhci_init(u32 regbase);
#endif /* _SYS_PROTO_H_ */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 37ac0daa70..7611d0a18b 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -24,6 +24,10 @@
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
+#ifdef CONFIG_OMAP
+#include <asm/omap_boot.h>
+#endif
+
/* Architecture-specific global data */
struct arch_global_data {
#if defined(CONFIG_FSL_ESDHC)
@@ -51,6 +55,10 @@ struct arch_global_data {
unsigned long tlb_addr;
unsigned long tlb_size;
#endif
+
+#ifdef CONFIG_OMAP
+ struct omap_boot_parameters omap_boot_params;
+#endif
};
#include <asm-generic/global_data.h>
diff --git a/arch/arm/include/asm/arch-mxs/dma.h b/arch/arm/include/asm/imx-common/dma.h
index 1ac8696e64..cb74528970 100644
--- a/arch/arm/include/asm/arch-mxs/dma.h
+++ b/arch/arm/include/asm/imx-common/dma.h
@@ -72,6 +72,18 @@ enum {
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
+#elif defined(CONFIG_MX6)
+enum {
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+ MXS_MAX_DMA_CHANNELS,
+};
#endif
/*
diff --git a/arch/arm/include/asm/imx-common/imximage.cfg b/arch/arm/include/asm/imx-common/imximage.cfg
new file mode 100644
index 0000000000..95daa3d581
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/imximage.cfg
@@ -0,0 +1,30 @@
+/*
+ * i.MX image header offset values
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ */
+
+/*
+ * NOTE: This file must be kept in sync with tools/imximage.h because
+ * tools/imximage.c can not cross-include headers from arch/arm/
+ * and vice-versa.
+ */
+
+#ifndef __ASM_IMX_COMMON_IMXIMAGE_CFG__
+#define __ASM_IMX_COMMON_IMXIMAGE_CFG__
+
+/* Standard image header offset for NAND, SATA, SD, SPI flash. */
+#define FLASH_OFFSET_STANDARD 0x400
+/* Specific image header offset for booting from OneNAND. */
+#define FLASH_OFFSET_ONENAND 0x100
+/* Specific image header offset for booting from memory-mapped NOR. */
+#define FLASH_OFFSET_NOR 0x1000
+
+#endif /* __ASM_IMX_COMMON_IMXIMAGE_CFG__ */
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index c34bb76ad4..0b4e76333e 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -23,6 +23,8 @@
#ifndef __MACH_IOMUX_V3_H__
#define __MACH_IOMUX_V3_H__
+#include <common.h>
+
/*
* build IOMUX_PAD structure
*
@@ -84,7 +86,68 @@ typedef u64 iomux_v3_cfg_t;
((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
+#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
+ MUX_PAD_CTRL(pad))
+
+#define __NA_ 0x000
+#define NO_MUX_I 0
+#define NO_PAD_I 0
+
#define NO_PAD_CTRL (1 << 17)
+
+#ifdef CONFIG_MX6
+
+#define PAD_CTL_HYS (1 << 16)
+
+#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE)
+#define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE)
+#define PAD_CTL_PKE (1 << 12)
+
+#define PAD_CTL_ODE (1 << 11)
+
+#define PAD_CTL_SPEED_LOW (1 << 6)
+#define PAD_CTL_SPEED_MED (2 << 6)
+#define PAD_CTL_SPEED_HIGH (3 << 6)
+
+#define PAD_CTL_DSE_DISABLE (0 << 3)
+#define PAD_CTL_DSE_240ohm (1 << 3)
+#define PAD_CTL_DSE_120ohm (2 << 3)
+#define PAD_CTL_DSE_80ohm (3 << 3)
+#define PAD_CTL_DSE_60ohm (4 << 3)
+#define PAD_CTL_DSE_48ohm (5 << 3)
+#define PAD_CTL_DSE_40ohm (6 << 3)
+#define PAD_CTL_DSE_34ohm (7 << 3)
+
+#else
+
+#define PAD_CTL_DVS (1 << 13)
+#define PAD_CTL_INPUT_DDR (1 << 9)
+#define PAD_CTL_HYS (1 << 8)
+
+#define PAD_CTL_PKE (1 << 7)
+#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
+#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE)
+
+#define PAD_CTL_ODE (1 << 3)
+
+#define PAD_CTL_DSE_LOW (0 << 1)
+#define PAD_CTL_DSE_MED (1 << 1)
+#define PAD_CTL_DSE_HIGH (2 << 1)
+#define PAD_CTL_DSE_MAX (3 << 1)
+
+#endif
+
+#define PAD_CTL_SRE_SLOW (0 << 0)
+#define PAD_CTL_SRE_FAST (1 << 0)
+
+#define IOMUX_CONFIG_SION 0x10
+
#define GPIO_PIN_MASK 0x1f
#define GPIO_PORT_SHIFT 5
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
@@ -95,10 +158,8 @@ typedef u64 iomux_v3_cfg_t;
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-#define MUX_CONFIG_SION (0x1 << 4)
-
-int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
+void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
#endif /* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/include/asm/arch-mxs/regs-apbh.h b/arch/arm/include/asm/imx-common/regs-apbh.h
index fcef4b80e3..bcec6e0b95 100644
--- a/arch/arm/include/asm/arch-mxs/regs-apbh.h
+++ b/arch/arm/include/asm/imx-common/regs-apbh.h
@@ -26,7 +26,7 @@
#ifndef __REGS_APBH_H__
#define __REGS_APBH_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
@@ -109,7 +109,7 @@ struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_version)
};
-#elif defined(CONFIG_MX28)
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
@@ -288,6 +288,17 @@ struct mxs_apbh_regs {
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
+#elif defined(CONFIG_MX6)
+#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040
+#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080
+#define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100
#endif
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
@@ -393,6 +404,10 @@ struct mxs_apbh_regs {
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif
+#if defined(CONFIG_MX6)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
+#endif
+
#if defined(CONFIG_MX23)
#define APBH_DEVSEL_CH7_MASK (0xf << 28)
#define APBH_DEVSEL_CH7_OFFSET 28
diff --git a/arch/arm/include/asm/arch-mxs/regs-bch.h b/arch/arm/include/asm/imx-common/regs-bch.h
index 40baa4d1f9..dbe7ac8ed6 100644
--- a/arch/arm/include/asm/arch-mxs/regs-bch.h
+++ b/arch/arm/include/asm/imx-common/regs-bch.h
@@ -26,7 +26,7 @@
#ifndef __MX28_REGS_BCH_H__
#define __MX28_REGS_BCH_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_bch_regs {
@@ -136,8 +136,13 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
+#if defined(CONFIG_MX6)
+#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
+#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
+#else
#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
+#endif
#define BCH_FLASHLAYOUT0_ECC0_NONE (0x0 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC2 (0x1 << 12)
#define BCH_FLASHLAYOUT0_ECC0_ECC4 (0x2 << 12)
@@ -161,8 +166,13 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
+#if defined(CONFIG_MX6)
+#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
+#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
+#else
#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
+#endif
#define BCH_FLASHLAYOUT1_ECCN_NONE (0x0 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC2 (0x1 << 12)
#define BCH_FLASHLAYOUT1_ECCN_ECC4 (0x2 << 12)
diff --git a/arch/arm/include/asm/arch-mxs/regs-common.h b/arch/arm/include/asm/imx-common/regs-common.h
index bcea419f99..bcea419f99 100644
--- a/arch/arm/include/asm/arch-mxs/regs-common.h
+++ b/arch/arm/include/asm/imx-common/regs-common.h
diff --git a/arch/arm/include/asm/arch-mxs/regs-gpmi.h b/arch/arm/include/asm/imx-common/regs-gpmi.h
index 624d618560..3409b9430c 100644
--- a/arch/arm/include/asm/arch-mxs/regs-gpmi.h
+++ b/arch/arm/include/asm/imx-common/regs-gpmi.h
@@ -26,7 +26,7 @@
#ifndef __MX28_REGS_GPMI_H__
#define __MX28_REGS_GPMI_H__
-#include <asm/arch/regs-common.h>
+#include <asm/imx-common/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_gpmi_regs {
diff --git a/arch/arm/include/asm/omap_boot.h b/arch/arm/include/asm/omap_boot.h
new file mode 100644
index 0000000000..a803965ac5
--- /dev/null
+++ b/arch/arm/include/asm/omap_boot.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK 0xFF
+#define BOOT_DEVICE_OFFSET 0x8
+#define DEV_DESC_PTR_OFFSET 0x4
+#define DEV_DATA_PTR_OFFSET 0x18
+#define BOOT_MODE_OFFSET 0x8
+#define RESET_REASON_OFFSET 0x9
+#define CH_FLAGS_OFFSET 0xA
+
+#define CH_FLAGS_CHSETTINGS (0x1 << 0)
+#define CH_FLAGS_CHRAM (0x1 << 1)
+#define CH_FLAGS_CHFLASH (0x1 << 2)
+#define CH_FLAGS_CHMMCSD (0x1 << 3)
+
+#ifndef __ASSEMBLY__
+struct omap_boot_parameters {
+ char *boot_message;
+ unsigned int mem_boot_descriptor;
+ unsigned char omap_bootdevice;
+ unsigned char reset_reason;
+ unsigned char ch_flags;
+ unsigned long omap_bootmode;
+};
+#endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 091ddb508d..ee7b188d3a 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -25,6 +25,8 @@
#ifndef _OMAP_COMMON_H_
#define _OMAP_COMMON_H_
+#ifndef __ASSEMBLY__
+
#include <common.h>
#define NUM_SYS_CLKS 8
@@ -316,6 +318,7 @@ struct prcm_regs {
u32 cm_wkupaon_io_srcomp_clkctrl;
u32 prm_rstctrl;
u32 prm_rstst;
+ u32 prm_rsttime;
u32 prm_vc_val_bypass;
u32 prm_vc_cfg_i2c_mode;
u32 prm_vc_cfg_i2c_clk;
@@ -557,6 +560,7 @@ static inline u32 omap_revision(void)
extern u32 *const omap_si_rev;
return *omap_si_rev;
}
+#endif
/*
* silicon revisions.
@@ -583,4 +587,20 @@ static inline u32 omap_revision(void)
/* DRA7XX */
#define DRA752_ES1_0 0x07520100
+
+/*
+ * SRAM scratch space entries
+ */
+#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
+#define OMAP_SRAM_SCRATCH_OMAP_REV SRAM_SCRATCH_SPACE_ADDR
+#define OMAP_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP_SRAM_SCRATCH_BOOT_PARAMS (SRAM_SCRATCH_SPACE_ADDR + 0x24)
+#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+
#endif /* _OMAP_COMMON_H_ */
diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
index b53232fd36..4f4c9ecfea 100644
--- a/arch/powerpc/cpu/mpc512x/Makefile
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -38,7 +38,6 @@ COBJS-y += serial.o
COBJS-y += speed.o
COBJS-$(CONFIG_FSL_DIU_FB) += diu.o
COBJS-$(CONFIG_CMD_IDE) += ide.o
-COBJS-$(CONFIG_IIM) += iim.o
COBJS-$(CONFIG_PCI) += pci.o
# Stub implementations of cache management functions for USB
diff --git a/arch/powerpc/cpu/mpc512x/cpu_init.c b/arch/powerpc/cpu/mpc512x/cpu_init.c
index b308cb4be3..0e20ded4c7 100644
--- a/arch/powerpc/cpu/mpc512x/cpu_init.c
+++ b/arch/powerpc/cpu/mpc512x/cpu_init.c
@@ -201,7 +201,7 @@ void cpu_init_f (volatile immap_t * im)
*/
out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
-#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+#if defined(CONFIG_FSL_IIM) || defined(CONFIG_CMD_FUSE)
setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
#endif
}
diff --git a/arch/powerpc/cpu/mpc512x/iim.c b/arch/powerpc/cpu/mpc512x/iim.c
deleted file mode 100644
index abec8f61cc..0000000000
--- a/arch/powerpc/cpu/mpc512x/iim.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * Copyright 2008 Silicon Turnkey Express, Inc.
- * Martha Marx <mmarx@silicontkx.com>
- *
- * ADS5121 IIM (Fusebox) Interface
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_CMD_FUSE
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static char cur_bank = '1';
-
-char *iim_err_msg(u32 err)
-{
- static char *IIM_errs[] = {
- "Parity Error in cache",
- "Explicit Sense Cycle Error",
- "Write to Locked Register Error",
- "Read Protect Error",
- "Override Protect Error",
- "Write Protect Error"};
-
- int i;
-
- if (!err)
- return "";
- for (i = 1; i < 8; i++)
- if (err & (1 << i))
- printf("IIM - %s\n", IIM_errs[i-1]);
- return "";
-}
-
-int in_range(int n, int min, int max, char *err, char *usg)
-{
- if (n > max || n < min) {
- printf(err);
- printf("Usage:\n%s\n", usg);
- return 0;
- }
- return 1;
-}
-
-int ads5121_fuse_read(int bank, int fstart, int num)
-{
- iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
- u32 *iim_fb, dummy;
- int f, ctr;
-
- out_be32(&iim->err, in_be32(&iim->err));
- if (bank == 0)
- iim_fb = (u32 *)&(iim->fbac0);
- else
- iim_fb = (u32 *)&(iim->fbac1);
-/* try a read to see if Read Protect is set */
- dummy = in_be32(&iim_fb[0]);
- if (in_be32(&iim->err) & IIM_ERR_RPE) {
- printf("\tRead protect fuse is set\n");
- out_be32(&iim->err, IIM_ERR_RPE);
- return 0;
- }
- printf("Reading Bank %d cache\n", bank);
- for (f = fstart, ctr = 0; num > 0; ctr++, num--, f++) {
- if (ctr % 4 == 0)
- printf("F%2d:", f);
- printf("\t%#04x", (u8)(iim_fb[f]));
- if (ctr % 4 == 3)
- printf("\n");
- }
- if (ctr % 4 != 0)
- printf("\n");
-}
-
-int ads5121_fuse_override(int bank, int f, u8 val)
-{
- iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
- u32 *iim_fb;
- u32 iim_stat;
- int i;
-
- out_be32(&iim->err, in_be32(&iim->err));
- if (bank == 0)
- iim_fb = (u32 *)&(iim->fbac0);
- else
- iim_fb = (u32 *)&(iim->fbac1);
-/* try a read to see if Read Protect is set */
- iim_stat = in_be32(&iim_fb[0]);
- if (in_be32(&iim->err) & IIM_ERR_RPE) {
- printf("Read protect fuse is set on bank %d;"
- "Override protect may also be set\n", bank);
- printf("An attempt will be made to override\n");
- out_be32(&iim->err, IIM_ERR_RPE);
- }
- if (iim_stat & IIM_FBAC_FBOP) {
- printf("Override protect fuse is set on bank %d\n", bank);
- return 1;
- }
- if (f > IIM_FMAX) /* reset the entire bank */
- for (i = 0; i < IIM_FMAX + 1; i++)
- out_be32(&iim_fb[i], 0);
- else
- out_be32(&iim_fb[f], val);
- return 0;
-}
-
-int ads5121_fuse_prog(cmd_tbl_t *cmdtp, int bank, char *fuseno_bitno)
-{
- iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
- int f, i, bitno;
- u32 stat, err;
-
- f = simple_strtol(fuseno_bitno, NULL, 10);
- if (f == 0 && fuseno_bitno[0] != '0')
- f = -1;
- if (!in_range(f, 0, IIM_FMAX,
- "<frow> must be between 0-31\n\n", cmdtp->usage))
- return 1;
- bitno = -1;
- for (i = 0; i < 6; i++) {
- if (fuseno_bitno[i] == '_') {
- bitno = simple_strtol(&(fuseno_bitno[i+1]), NULL, 10);
- if (bitno == 0 && fuseno_bitno[i+1] != '0')
- bitno = -1;
- break;
- }
- }
- if (!in_range(bitno, 0, 7, "Bit number ranges from 0-7\n"
- "Example of <frow_bitno>: \"18_4\" sets bit 4 of row 18\n",
- cmdtp->usage))
- return 1;
- out_be32(&iim->err, in_be32(&iim->err));
- out_be32(&iim->prg_p, IIM_PRG_P_SET);
- out_be32(&iim->ua, IIM_SET_UA(bank, f));
- out_be32(&iim->la, IIM_SET_LA(f, bitno));
-#ifdef DEBUG
- printf("Programming disabled with DEBUG defined \n");
- printf(""Set up to pro
- printf("iim.ua = %x; iim.la = %x\n", iim->ua, iim->la);
-#else
- out_be32(&iim->fctl, IIM_FCTL_PROG_PULSE | IIM_FCTL_PROG);
- do
- udelay(20);
- while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
- out_be32(&iim->prg_p, 0);
- err = in_be32(&iim->err);
- if (stat & IIM_STAT_PRGD) {
- if (!(err & (IIM_ERR_WPE | IIM_ERR_WPE))) {
- printf("Fuse is successfully set");
- if (err)
- printf(" - however there are other errors");
- printf("\n");
- }
- iim->stat = 0;
- }
- if (err) {
- iim_err_msg(err);
- out_be32(&iim->err, in_be32(&iim->err));
- }
-#endif
-}
-
-int ads5121_fuse_sense(int bank, int fstart, int num)
-{
- iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
- u32 iim_fbac;
- u32 stat, err, err_hold = 0;
- int f, ctr;
-
- out_be32(&iim->err, in_be32(&iim->err));
- if (bank == 0)
- iim_fbac = in_be32(&iim->fbac0);
- else
- iim_fbac = in_be32(&iim->fbac1);
- if (iim_fbac & IIM_FBAC_FBESP) {
- printf("\tSense Protect disallows this operation\n");
- out_be32(&iim->err, IIM_FBAC_FBESP);
- return 1;
- }
- err = in_be32(&iim->err);
- if (err) {
- iim_err_msg(err);
- err_hold |= err;
- }
- if (err & IIM_ERR_RPE)
- printf("\tRead protect fuse is set; "
- "Sense Protect may be set but will be attempted\n");
- if (err)
- out_be32(&iim->err, err);
- printf("Sensing fuse(s) on Bank %d\n", bank);
- for (f = fstart, ctr = 0; num > 0; ctr++, f++, num--) {
- out_be32(&iim->ua, IIM_SET_UA(bank, f));
- out_be32(&iim->la, IIM_SET_LA(f, 0));
- out_be32(&iim->fctl, IIM_FCTL_ESNS_N);
- do
- udelay(20);
- while ((stat = in_be32(&iim->stat)) & IIM_STAT_BUSY);
- err = in_be32(&iim->err);
- if (err & IIM_ERR_SNSE) {
- iim_err_msg(err);
- out_be32(&iim->err, IIM_ERR_SNSE);
- return 1;
- }
- if (stat & IIM_STAT_SNSD) {
- out_be32(&iim->stat, 0);
- if (ctr % 4 == 0)
- printf("F%2d:", f);
- printf("\t%#04x", (u8)iim->sdat);
- if (ctr % 4 == 3)
- printf("\n");
- }
- if (err) {
- err_hold |= err;
- out_be32(&iim->err, err);
- }
- }
- if (ctr % 4 != 0)
- printf("\n");
- if (err_hold)
- iim_err_msg(err_hold);
-
- return 0;
-}
-
-int ads5121_fuse_stat(int bank)
-{
- iim512x_t *iim = &((immap_t *) CONFIG_SYS_IMMR)->iim;
- u32 iim_fbac;
- u32 err;
-
- out_be32(&iim->err, in_be32(&iim->err));
- if (bank == 0)
- iim_fbac = in_be32(&iim->fbac0);
- else
- iim_fbac = in_be32(&iim->fbac1);
- err = in_be32(&iim->err);
- if (err)
- iim_err_msg(err);
- if (err & IIM_ERR_RPE || iim_fbac & IIM_FBAC_FBRP) {
- if (iim_fbac == 0)
- printf("Since protection settings can't be read - "
- "try sensing fuse row 0;\n");
- return 0;
- }
- if (iim_fbac & IIM_PROTECTION)
- printf("Protection Fuses Bank %d = %#04x:\n", bank, iim_fbac);
- else if (!(err & IIM_ERR_RPE))
- printf("No Protection fuses are set\n");
- if (iim_fbac & IIM_FBAC_FBWP)
- printf("\tWrite Protect fuse is set\n");
- if (iim_fbac & IIM_FBAC_FBOP)
- printf("\tOverride Protect fuse is set\n");
- if (iim_fbac & IIM_FBAC_FBESP)
- printf("\tSense Protect Fuse is set\n");
- out_be32(&iim->err, in_be32(&iim->err));
-
- return 0;
-}
-
-int do_ads5121_fuse(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int frow, n, v, bank;
-
- if (cur_bank == '0')
- bank = 0;
- else
- bank = 1;
-
- switch (argc) {
- case 0:
- case 1:
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- case 2:
- if (strncmp(argv[1], "stat", 4) == 0)
- return ads5121_fuse_stat(bank);
- if (strncmp(argv[1], "read", 4) == 0)
- return ads5121_fuse_read(bank, 0, IIM_FMAX + 1);
- if (strncmp(argv[1], "sense", 5) == 0)
- return ads5121_fuse_sense(bank, 0, IIM_FMAX + 1);
- if (strncmp(argv[1], "ovride", 6) == 0)
- return ads5121_fuse_override(bank, IIM_FMAX + 1, 0);
- if (strncmp(argv[1], "bank", 4) == 0) {
- printf("Active Fuse Bank is %c\n", cur_bank);
- return 0;
- }
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- case 3:
- if (strncmp(argv[1], "bank", 4) == 0) {
- if (argv[2][0] == '0')
- cur_bank = '0';
- else if (argv[2][0] == '1')
- cur_bank = '1';
- else {
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- }
-
- printf("Setting Active Fuse Bank to %c\n", cur_bank);
- return 0;
- }
- if (strncmp(argv[1], "prog", 4) == 0)
- return ads5121_fuse_prog(cmdtp, bank, argv[2]);
-
- frow = (int)simple_strtol(argv[2], NULL, 10);
- if (frow == 0 && argv[2][0] != '0')
- frow = -1;
- if (!in_range(frow, 0, IIM_FMAX,
- "<frow> must be between 0-31\n\n", cmdtp->usage))
- return 1;
- if (strncmp(argv[1], "read", 4) == 0)
- return ads5121_fuse_read(bank, frow, 1);
- if (strncmp(argv[1], "ovride", 6) == 0)
- return ads5121_fuse_override(bank, frow, 0);
- if (strncmp(argv[1], "sense", 5) == 0)
- return ads5121_fuse_sense(bank, frow, 1);
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- case 4:
- frow = (int)simple_strtol(argv[2], NULL, 10);
- if (frow == 0 && argv[2][0] != '0')
- frow = -1;
- if (!in_range(frow, 0, IIM_FMAX,
- "<frow> must be between 0-31\n\n", cmdtp->usage))
- return 1;
- if (strncmp(argv[1], "read", 4) == 0) {
- n = (int)simple_strtol(argv[3], NULL, 10);
- if (!in_range(frow + n, frow + 1, IIM_FMAX + 1,
- "<frow>+<n> must be between 1-32\n\n",
- cmdtp->usage))
- return 1;
- return ads5121_fuse_read(bank, frow, n);
- }
- if (strncmp(argv[1], "ovride", 6) == 0) {
- v = (int)simple_strtol(argv[3], NULL, 10);
- return ads5121_fuse_override(bank, frow, v);
- }
- if (strncmp(argv[1], "sense", 5) == 0) {
- n = (int)simple_strtol(argv[3], NULL, 10);
- if (!in_range(frow + n, frow + 1, IIM_FMAX + 1,
- "<frow>+<n> must be between 1-32\n\n",
- cmdtp->usage))
- return 1;
- return ads5121_fuse_sense(bank, frow, n);
- }
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- default: /* at least 5 args */
- printf("Usage:\n%s\n", cmdtp->usage);
- return 1;
- }
-}
-
-U_BOOT_CMD(
- fuse, CONFIG_SYS_MAXARGS, 0, do_ads5121_fuse,
- " - Read, Sense, Override or Program Fuses\n",
- "bank <n> - sets active Fuse Bank to 0 or 1\n"
- " no args shows current active bank\n"
- "fuse stat - print active fuse bank's protection status\n"
- "fuse read [<frow> [<n>]] - print <n> fuse rows starting at <frow>\n"
- " no args to print entire bank's fuses\n"
- "fuse ovride [<frow> [<v>]]- override fuses at <frow> with <v>\n"
- " no <v> defaults to 0 for the row\n"
- " no args resets entire bank to 0\n"
- " NOTE - settings persist until hard reset\n"
- "fuse sense [<frow>] - senses current fuse at <frow>\n"
- " no args for entire bank\n"
- "fuse prog <frow_bit> - program fuse at row <frow>, bit <_bit>\n"
- " <frow> is 0-31, <bit> is 0-7; eg. 13_2 \n"
- " WARNING - this is permanent"
-);
-#endif /* CONFIG_CMD_FUSE */
diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
index d96e53646a..824821981d 100644
--- a/arch/powerpc/include/asm/immap_512x.h
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -1272,4 +1272,6 @@ static inline u32 get_pata_base (void)
#define CONFIG_SYS_MPC512x_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET)
+#define IIM_BASE_ADDR (CONFIG_SYS_IMMR + offsetof(immap_t, iim))
+
#endif /* __IMMAP_512x__ */
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
index f2b4284267..af5338eb5f 100644
--- a/board/CarMediaLab/flea3/flea3.c
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -29,8 +29,7 @@
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
-#include <asm/arch/mx35_pins.h>
-#include <asm/arch/iomux.h>
+#include <asm/arch/iomux-mx35.h>
#include <i2c.h>
#include <linux/types.h>
#include <asm/gpio.h>
@@ -165,62 +164,68 @@ static void board_setup_sdram(void)
static void setup_iomux_uart3(void)
{
- mxc_request_iomux(MX35_PIN_RTS2, MUX_CONFIG_ALT7);
- mxc_request_iomux(MX35_PIN_CTS2, MUX_CONFIG_ALT7);
+ static const iomux_v3_cfg_t uart3_pads[] = {
+ MX35_PAD_RTS2__UART3_RXD_MUX,
+ MX35_PAD_CTS2__UART3_TXD_MUX,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}
+#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
+
static void setup_iomux_i2c(void)
{
- int pad;
-
- mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
-
- pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
- | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+ static const iomux_v3_cfg_t i2c_pads[] = {
+ NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
- mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
- mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+ NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
+ NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
+ };
- mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
- mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
-
- mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
- mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
+ imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
}
static void setup_iomux_spi(void)
{
- mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
- mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+ static const iomux_v3_cfg_t spi_pads[] = {
+ MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
+ MX35_PAD_CSPI1_MISO__CSPI1_MISO,
+ MX35_PAD_CSPI1_SS0__CSPI1_SS0,
+ MX35_PAD_CSPI1_SS1__CSPI1_SS1,
+ MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
+ };
+
+ imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
}
static void setup_iomux_fec(void)
{
- /* setup pins for FEC */
- mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
- mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+ static const iomux_v3_cfg_t fec_pads[] = {
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX35_PAD_FEC_COL__FEC_COL,
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX35_PAD_FEC_MDC__FEC_MDC,
+ MX35_PAD_FEC_MDIO__FEC_MDIO,
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+ MX35_PAD_FEC_CRS__FEC_CRS,
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ };
+ /* setup pins for FEC */
+ imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
int board_early_init_f(void)
@@ -229,7 +234,7 @@ int board_early_init_f(void)
(struct ccm_regs *)IMX_CCM_BASE;
/* setup GPIO3_1 to set HighVCore signal */
- mxc_request_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_ALT5);
+ imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
gpio_direction_output(65, 1);
/* initialize PLL and clock configuration */
diff --git a/board/Seagate/goflexhome/Makefile b/board/Seagate/goflexhome/Makefile
new file mode 100644
index 0000000000..9948fe22d3
--- /dev/null
+++ b/board/Seagate/goflexhome/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+#
+# Based on dockstar/Makefile originally written by
+# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/Makefile originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := goflexhome.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c
new file mode 100644
index 0000000000..17c19053fa
--- /dev/null
+++ b/board/Seagate/goflexhome/goflexhome.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+ *
+ * Based on dockstar.c originally written by
+ * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.c originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_NF_IO2,
+ MPP1_NF_IO3,
+ MPP2_NF_IO4,
+ MPP3_NF_IO5,
+ MPP4_NF_IO6,
+ MPP5_NF_IO7,
+ MPP6_SYSRST_OUTn,
+ MPP7_GPO,
+ MPP8_UART0_RTS,
+ MPP9_UART0_CTS,
+ MPP10_UART0_TXD,
+ MPP11_UART0_RXD,
+ MPP12_SD_CLK,
+ MPP13_SD_CMD,
+ MPP14_SD_D0,
+ MPP15_SD_D1,
+ MPP16_SD_D2,
+ MPP17_SD_D3,
+ MPP18_NF_IO0,
+ MPP19_NF_IO1,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_TSMP9,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ kw_config_gpio(GOFLEXHOME_OE_VAL_LOW,
+ GOFLEXHOME_OE_VAL_HIGH,
+ GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /*
+ * arch number of board
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __func__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#define GREEN_LED (1 << 14)
+#define ORANGE_LED (1 << 15)
+#define BOTH_LEDS (GREEN_LED | ORANGE_LED)
+#define NEITHER_LED 0
+
+static void set_leds(u32 leds, u32 blinking)
+{
+ struct kwgpio_registers *r;
+ u32 oe;
+ u32 bl;
+
+ r = (struct kwgpio_registers *)KW_GPIO1_BASE;
+ oe = readl(&r->oe) | BOTH_LEDS;
+ writel(oe & ~leds, &r->oe); /* active low */
+ bl = readl(&r->blink_en) & ~BOTH_LEDS;
+ writel(bl | blinking, &r->blink_en);
+}
+
+void show_boot_progress(int val)
+{
+ switch (val) {
+ case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
+ set_leds(BOTH_LEDS, NEITHER_LED);
+ break;
+ case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
+ set_leds(GREEN_LED, GREEN_LED);
+ break;
+ default:
+ if (val < 0) /* error */
+ set_leds(ORANGE_LED, ORANGE_LED);
+ break;
+ }
+}
diff --git a/board/Seagate/goflexhome/kwbimage.cfg b/board/Seagate/goflexhome/kwbimage.cfg
new file mode 100644
index 0000000000..e984d72247
--- /dev/null
+++ b/board/Seagate/goflexhome/kwbimage.cfg
@@ -0,0 +1,168 @@
+#
+# Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+#
+# Based on dockstar/kwbimage.cfg originally written by
+# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
+#
+# Based on sheevaplug/kwbimage.cfg originally written by
+# Prafulla Wadaskar <prafulla@marvell.com>
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30 # DDR Configuration register
+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
+# bit 4: 0=addr/cmd in smame cycle
+# bit 5: 0=clk is driven during self refresh, we don't care for APX
+# bit 6: 0=use recommended falling edge of clk for addr/cmd
+# bit14: 0=input buffer always powered up
+# bit18: 1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31: 0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
+# bit3-0: TRAS lsbs
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20: TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000000d # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16: 0, Cs0AddrSel
+# bit17: 0, Cs1AddrSel
+# bit18: 0, Cs2AddrSel
+# bit19: 0, Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
+# bit0: 0, OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000 # DDR Operation
+# bit3-0: 0x0, DDR cmd
+# bit31-4: 0 required
+
+DATA 0xFFD0141C 0x00000C52 # DDR Mode
+# bit2-0: 2, BurstLen=2 required
+# bit3: 0, BurstType=0 required
+# bit6-4: 4, CL=5
+# bit7: 0, TestMode=0 normal
+# bit8: 0, DLL reset=0 normal
+# bit11-9: 6, auto-precharge write recovery ????????????
+# bit12: 0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000040 # DDR Extended Mode
+# bit0: 0, DDR DLL enabled
+# bit1: 0, DDR drive strenght normal
+# bit2: 0, DDR ODT control lsd (disabled)
+# bit5-3: 000, required
+# bit6: 1, DDR ODT control msb, (disabled)
+# bit9-7: 000, required
+# bit10: 0, differential DQS enabled
+# bit11: 0, required
+# bit12: 0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
+# bit2-0: 111, required
+# bit3 : 1 , MBUS Burst Chop disabled
+# bit6-4: 111, required
+# bit7 : 0
+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9 : 0 , no half clock cycle addition to dataout
+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0 required
+
+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
+# bit0: 1, Window enabled
+# bit1: 0, Write Protect disabled
+# bit3-2: 00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
+
+DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
+# bit3-2: 01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile
index 87495901fe..6719f3d446 100644
--- a/board/armltd/vexpress/Makefile
+++ b/board/armltd/vexpress/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
-COBJS := ca9x4_ct_vxp.o
+COBJS := vexpress_common.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/armltd/vexpress/ca9x4_ct_vxp.c b/board/armltd/vexpress/vexpress_common.c
index d5e109ec06..2c54869e2c 100644
--- a/board/armltd/vexpress/ca9x4_ct_vxp.c
+++ b/board/armltd/vexpress/vexpress_common.c
@@ -45,8 +45,7 @@
static ulong timestamp;
static ulong lastdec;
-static struct wdt *wdt_base = (struct wdt *)WDT_BASE;
-static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
+static struct systimer *systimer_base = (struct systimer *)V2M_TIMER01;
static struct sysctrl *sysctrl_base = (struct sysctrl *)SCTL_BASE;
static void flash__init(void);
@@ -166,20 +165,38 @@ static void vexpress_timer_init(void)
*/
writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
- writel(SYSTIMER_EN | SYSTIMER_32BIT | \
- readl(&systimer_base->timer0control), \
+ writel(SYSTIMER_EN | SYSTIMER_32BIT |
+ readl(&systimer_base->timer0control),
&systimer_base->timer0control);
reset_timer_masked();
}
+int v2m_cfg_write(u32 devfn, u32 data)
+{
+ /* Configuration interface broken? */
+ u32 val;
+
+ devfn |= SYS_CFG_START | SYS_CFG_WRITE;
+
+ val = readl(V2M_SYS_CFGSTAT);
+ writel(val & ~SYS_CFG_COMPLETE, V2M_SYS_CFGSTAT);
+
+ writel(data, V2M_SYS_CFGDATA);
+ writel(devfn, V2M_SYS_CFGCTRL);
+
+ do {
+ val = readl(V2M_SYS_CFGSTAT);
+ } while (val == 0);
+
+ return !!(val & SYS_CFG_ERR);
+}
+
/* Use the ARM Watchdog System to cause reset */
void reset_cpu(ulong addr)
{
- writeb(WDT_EN, &wdt_base->wdogcontrol);
- writel(WDT_RESET_LOAD, &wdt_base->wdogload);
- while (1)
- ;
+ if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
+ printf("Unable to reboot\n");
}
/*
@@ -251,7 +268,7 @@ unsigned long long get_ticks(void)
return get_timer(0);
}
-ulong get_tbclk (void)
+ulong get_tbclk(void)
{
return (ulong)CONFIG_SYS_HZ;
}
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index 3aa394a4bb..8d3fc75cd9 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -30,6 +30,7 @@
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
+#include <atmel_mci.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
# include <net.h>
@@ -143,6 +144,15 @@ static void at91sam9260ek_macb_hw_init(void)
}
#endif
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+ at91_mci_hw_init();
+
+ return atmel_mci_init((void *)ATMEL_BASE_MCI);
+}
+#endif
+
int board_early_init_f(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
@@ -157,18 +167,6 @@ int board_early_init_f(void)
int board_init(void)
{
-#ifdef CONFIG_AT91SAM9G20EK_2MMC
- /* arch number of AT91SAM9G20EK_2MMC-Board */
- gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK_2MMC;
-#else
-#ifdef CONFIG_AT91SAM9G20EK
- /* arch number of AT91SAM9G20EK-Board */
- gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK;
-#else
- /* arch number of AT91SAM9260EK-Board */
- gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
-#endif
-#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
diff --git a/board/atmel/at91sam9n12ek/Makefile b/board/atmel/at91sam9n12ek/Makefile
new file mode 100644
index 0000000000..3aa67d5eb8
--- /dev/null
+++ b/board/atmel/at91sam9n12ek/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Josh Wu <josh.wu@atmel.com>
+# Atmel corporation <www.atmel.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += at91sam9n12ek.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
new file mode 100644
index 0000000000..8752794c84
--- /dev/null
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -0,0 +1,228 @@
+/*
+ * (C) Copyright 2013 Atmel Corporation
+ * Josh Wu <josh.wu@atmel.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9x5_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <atmel_hlcdc.h>
+#include <atmel_mci.h>
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+#ifdef CONFIG_NAND_ATMEL
+static void at91sam9n12ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ unsigned long csa;
+
+ /* Assign CS3 to NAND/SmartMedia Interface */
+ csa = readl(&matrix->ebicsa);
+ csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+ /* Configure databus */
+ csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
+ /* Configure IO drive */
+ csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
+ writel(csa, &matrix->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[3].setup);
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
+ AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
+ &smc->cs[3].pulse);
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
+ &smc->cs[3].cycle);