diff options
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock_sun9i.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c index 78d373e573..3e6e2e06b4 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c @@ -37,16 +37,16 @@ void clock_init_safe(void) /* Set up dividers for AXI0 and APB0 on cluster 0: PLL1 / 2 = 204MHz */ writel(C0_CFG_AXI0_CLK_DIV_RATIO(2) | C0_CFG_APB0_CLK_DIV_RATIO(2), &ccm->c0_cfg); - writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(8), &ccm->ahb0_cfg); /* AHB0: 120MHz */ - writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(4), &ccm->ahb1_cfg); /* AHB1: 240MHz */ + /* GTBUS: 400MHz (PERIPH1 div 3) */ + writel(GTBUS_SRC_PLL_PERIPH1 | GTBUS_CLK_DIV_RATIO(3), &ccm->gtbus_cfg); + /* CCI400: 600MHz (PERIPH1 div 2) */ + writel(CCI400_SRC_PLL_PERIPH1 | CCI400_CLK_DIV_RATIO(2), &ccm->cci400_cfg); + + writel(AHB0_SRC_GTBUS_CLK | AHBx_CLK_DIV_RATIO(2), &ccm->ahb0_cfg); /* AHB0: 200MHz */ + writel(AHB1_SRC_GTBUS_CLK | AHBx_CLK_DIV_RATIO(2), &ccm->ahb1_cfg); /* AHB1: 200MHz */ writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(8), &ccm->ahb2_cfg); /* AHB2: 120MHz */ writel(APB0_SRC_PLL_PERIPH0 | APB0_CLK_DIV_RATIO(8), &ccm->apb0_cfg); /* APB0: 120MHz */ - /* GTBUS: 400MHz (PERIPH0 div 3) */ - writel(GTBUS_SRC_PLL_PERIPH1 | GTBUS_CLK_DIV_RATIO(3), &ccm->gtbus_cfg); - /* CCI400: 480MHz (PERIPH1 div 2) */ - writel(CCI400_SRC_PLL_PERIPH0 | CCI400_CLK_DIV_RATIO(2), &ccm->cci400_cfg); - /* Deassert DMA reset and open clock gating for DMA */ setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24)); setbits_le32(&ccm->apb1_gate, (1 << 24)); |