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authorReinhard Pfau <reinhard.pfau@gdsys.cc>2016-03-16 09:20:13 +0100
committerStefan Roese <sr@denx.de>2016-03-21 09:20:37 +0100
commita119357c43a4d4bd0e488a701255bcfea8f8bf6c (patch)
tree158ed8e068ebbfa6b283937fe6c98b3c41a56d9b /include
parent4709805657db221b05192d575392ebfd977ee1d2 (diff)
strider: use optimised bus timing for FPGA access
Use optimised bus timing for FPGA access. Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc> Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Diffstat (limited to 'include')
-rw-r--r--include/configs/strider.h11
1 files changed, 5 insertions, 6 deletions
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 7d9541bd83..d5f1981c0d 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -279,14 +279,13 @@
| BR_PS_16 /* 16 bit port */ \
| BR_MS_GPCM /* MSEL = GPCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
+
+#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET)
+ | OR_GPCM_SCY_5 \
+ | OR_GPCM_TRLX_CLEAR \
+ | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k) 0x0010