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authorPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2016-09-18 12:24:16 +0200
committerKlaus Goger <klaus.goger@theobroma-systems.com>2016-09-18 15:57:27 +0200
commit3ccb81251d5e84f53bce17a18a21538d5f2eb0ea (patch)
treeacda0dbeabf60050abcf20c2ac291ce959c57cfb /drivers
parent5a7df64aa96692ffb2043ffdda5200ef1b86fe55 (diff)
ARM: sun9i: SPI support for sun9i
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/sunxi_spi.c9
-rw-r--r--drivers/spi/sunxi_spi.h12
2 files changed, 15 insertions, 6 deletions
diff --git a/drivers/spi/sunxi_spi.c b/drivers/spi/sunxi_spi.c
index 5455f4b7a5..f9eeb8fe11 100644
--- a/drivers/spi/sunxi_spi.c
+++ b/drivers/spi/sunxi_spi.c
@@ -3,6 +3,7 @@
*
* Supported chips
* - Allwinner A31 (sun6i)
+ * - Allwinner A80 (sun9i)
*
* Copyright (C) 2015 Theobroma Systems Design und Consulting GmbH
* Octav Zlatior <octav.zlatior@theobroma-systems.com>
@@ -14,18 +15,19 @@
* the License, or (at your option) any later version.
*/
+#include <config.h>
#include <common.h>
#include <dm.h>
#include <spi.h>
#include <fdtdec.h>
#include <asm/errno.h>
-#include <configs/sun6i.h>
#include <asm/io.h>
-#include <asm/arch-sunxi/gpio.h>
-#include <asm/arch-sunxi/clock_sun6i.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clock.h>
#include "sunxi_spi.h"
+
DECLARE_GLOBAL_DATA_PTR;
// some arrays to make things easier to express
@@ -64,7 +66,6 @@ static int _sunxi_spi_xfer(struct sunxi_spi_reg* spi, unsigned int bitlen,
#ifdef CONFIG_SPL_BUILD
int i;
- printf("_sunxi_spi_xfer %p\n", spi);
#if 0
if (dout)
{
diff --git a/drivers/spi/sunxi_spi.h b/drivers/spi/sunxi_spi.h
index 5ae69c2aff..c45e6590d1 100644
--- a/drivers/spi/sunxi_spi.h
+++ b/drivers/spi/sunxi_spi.h
@@ -3,6 +3,7 @@
*
* Supported chips
* - Allwinner A31 (sun6i)
+ * - Allwinner A80 (sun9i)
*
* Copyright (C) 2015 Theobroma Systems Design und Consulting GmbH
* Octav Zlatior <octav.zlatior@theobroma-systems.com>
@@ -36,13 +37,20 @@
#define SUNXI_SPI0_MOSI_PIN SUNXI_GPC(0)
#define SUNXI_SPI0_MISO_PIN SUNXI_GPC(1)
#define SUNXI_SPI0_CLK_PIN SUNXI_GPC(2)
+#if defined(CONFIG_MACH_SUN9I)
+#define SUNXI_SPI0_CS0_PIN SUNXI_GPC(19)
+#define SUNXI_SPI0_CS1_PIN -1
+#define SUNXI_SPI0_CS0_VAL 3
+#define SUNXI_SPI0_CS1_VAL -1
+#else
#define SUNXI_SPI0_CS0_PIN SUNXI_GPC(27)
#define SUNXI_SPI0_CS1_PIN -1
+#define SUNXI_SPI0_CS0_VAL 3
+#define SUNXI_SPI0_CS1_VAL -1
+#endif
#define SUNXI_SPI0_MOSI_VAL 3
#define SUNXI_SPI0_MISO_VAL 3
#define SUNXI_SPI0_CLK_VAL 3
-#define SUNXI_SPI0_CS0_VAL 3
-#define SUNXI_SPI0_CS1_VAL -1
#define SUNXI_SPI1_MOSI_PIN SUNXI_GPG(15)
#define SUNXI_SPI1_MISO_PIN SUNXI_GPG(16)