diff options
| author | Simon Glass <sjg@chromium.org> | 2016-03-16 07:44:43 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-03-17 10:27:27 +0800 |
| commit | 374e78efb0c6739c8c700325acca769d7a9e47de (patch) | |
| tree | 4e626abc6d6bd43beec4b8bdad9025b4ef0e08e7 /configs | |
| parent | e5aa8a9b1593f524af07318d4e84352b06a53402 (diff) | |
x86: Add support for the samus chromebook
This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.
Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard
Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).
The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/chromebook_samus_defconfig | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig new file mode 100644 index 0000000000..448446d5cf --- /dev/null +++ b/configs/chromebook_samus_defconfig @@ -0,0 +1,51 @@ +CONFIG_X86=y +CONFIG_SYS_MALLOC_F_LEN=0x1800 +CONFIG_VENDOR_GOOGLE=y +CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus" +CONFIG_TARGET_CHROMEBOOK_SAMUS=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_HAVE_MRC=y +CONFIG_HAVE_REFCODE=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_TPM=y +CONFIG_CMD_TPM_TEST=y +CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_INTEL_BROADWELL_GPIO=y +CONFIG_CMD_CROS_EC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_LPC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_TPM_TIS_LPC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_VIDEO=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_VIDEO_BROADWELL_IGD=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_TPM=y |