diff options
| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2016-04-06 18:04:57 +0200 |
|---|---|---|
| committer | Klaus Goger <klaus.goger@theobroma-systems.com> | 2016-09-18 13:45:14 +0200 |
| commit | 5da39118172811a2fe32a4eeaee7193f8cb413ed (patch) | |
| tree | 5f942d4c7778b3de6f1e03da1338ac6811ff0010 /board | |
| parent | 6ed4d8a8686a0e8da9806a42dc90f1f0b7a0c160 (diff) | |
sunxi: Support GbE controller (GMAC) for sun9i (A80)
* board/sunxi/gmac.c(eth_init_board): Add support for configuring
sun9i (A80) for Ethernet support in RGMII mode.
* arch/arm/include/asm/arch-sunxi/gpio.h (SUN9I_GPA_GMAC): Define.
* arch/arm/include/asm/arch-sunxi/clock_sun9i.h: Add Ethernet support
for sun9i (A80), defining struct sunxi_sysctl_reg (which contains
the GMAC clock control on sun9i) and AHB_{GATE,RESET}_OFFSET_GMAC
* arch/arm/include/asm/arch-sunxi/cpu_sun9i.h(SUNXI_SYSCTL_BASE):
Define.
* arch/arm/dts/sun9i-a80.dtsi: add device-tree support for GMAC on
sun9i (A80).
Diffstat (limited to 'board')
| -rw-r--r-- | board/sunxi/gmac.c | 32 |
1 files changed, 27 insertions, 5 deletions
diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 69eb8ff2d9..976eefd8d3 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -11,9 +11,19 @@ void eth_init_board(void) int pin; struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; +#ifdef CONFIG_MACH_SUN9I + struct sunxi_sysctl_reg *const gethclk = + (struct sunxi_sysctl_reg *)SUNXI_SYSCTL_BASE; +#else + struct sunxi_ccm_reg *const gethclk = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; +#endif /* Set up clock gating */ -#ifdef CONFIG_SUNXI_GEN_SUN6I +#if defined(CONFIG_MACH_SUN9I) + setbits_le32(&ccm->ahb_reset1_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); + setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); +#elif defined(CONFIG_SUNXI_GEN_SUN6I) setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); #else @@ -22,16 +32,28 @@ void eth_init_board(void) /* Set MII clock */ #ifdef CONFIG_RGMII - setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | + setbits_le32(&gethclk->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | CCM_GMAC_CTRL_GPIT_RGMII); - setbits_le32(&ccm->gmac_clk_cfg, + setbits_le32(&gethclk->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); #else - setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | + setbits_le32(&gethclk->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | CCM_GMAC_CTRL_GPIT_MII); #endif -#ifndef CONFIG_MACH_SUN6I +#if defined(CONFIG_MACH_SUN9I) + /* Configure pin mux settings for GMAC. This is a temporary kludge + until we support reading the configuration from the device tree. */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(18); pin++) { +#ifdef CONFIG_RGMII + /* skip unused pins in RGMII mode */ + if (pin == SUNXI_GPA(6) || pin == SUNXI_GPA(11) || pin == SUNXI_GPA(14)) + continue; +#endif + sunxi_gpio_set_cfgpin(pin, SUN9I_GPA_GMAC); + sunxi_gpio_set_drv(pin, 3); + } +#elif !defined(CONFIG_MACH_SUN6I) /* Configure pin mux settings for GMAC */ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { #ifdef CONFIG_RGMII |