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authorSuresh Gupta <suresh.gupta@freescale.com>2013-03-25 07:40:13 +0000
committerAndy Fleming <afleming@freescale.com>2013-05-24 16:54:12 -0500
commit16d88f415ab799287672ae6cd08bf3ce975de2b5 (patch)
tree3d85efdf337bc48461c6610bf362f990e79b44da /board
parent49e946cb6ae0448492147ffcb9dcd7d0af1eab4d (diff)
Enable XAUI interface for B4860QDS
- Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/b4860qds/eth_b4860qds.c35
1 files changed, 35 insertions, 0 deletions
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
index 68e2725fce..3bcda6d13a 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -275,6 +275,24 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
break;
+ case 0x98:
+ /* XAUI in Slot1 and Slot2 */
+ debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n",
+ CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC1,
+ CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
+ debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+ CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2,
+ CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+ break;
+ case 0x9E:
+ /* XAUI in Slot2 */
+ debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
+ CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2,
+ CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
+ break;
default:
printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
serdes2_prtcl);
@@ -300,6 +318,23 @@ int board_eth_init(bd_t *bis)
}
}
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ int idx = i - FM1_10GEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
+ break;
+ default:
+ printf("Fman1: 10GSEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ fm_info_set_phy_address(i, 0);
+ break;
+ }
+ }
+
+
cpu_eth_init(bis);
#endif