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authorYork Sun <yorksun@freescale.com>2013-04-05 13:07:13 +0000
committerAndy Fleming <afleming@freescale.com>2013-05-24 16:54:14 -0500
commita71d45d706a5b51c348160163b6c159632273fed (patch)
tree00dadb437027b36bf73e0b3d30ae1851e4529cc5 /arch
parent39bdaff4f4dd75b578c9e1fe372e8d56e7d51526 (diff)
powerpc/mpc85xx: Clear L1 D-cache lock
dcbi instruction has been used to clear D-cache lock. However, the cache lock is persistent for e6500 core. Use dcblc to clear the lock explicitly. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index e413e4ae99..4f0480b768 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1906,6 +1906,7 @@ unlock_ram_in_cache:
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: dcbi r0,r3
+ dcblc r0,r3
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
sync