sun9i: improved clock setup for better boot reliability

2 files changed, 151 insertions, 10 deletions

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
index 3e6e2e06b4..b6f0afd9b9 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
@@ -16,43 +16,143 @@
 #include <asm/arch/prcm.h>
 #include <asm/arch/sys_proto.h>
 
-
 #ifdef CONFIG_SPL_BUILD
 
+#define DEBUG_CLK
+#if defined(DEBUG_CLK)
+static void clock_dbg_init(void)
+{
+	/* set up PE6..13 as outputs */
+        clrsetbits_le32(0x06000890, 0x77000000, 0x11000000);
+	clrsetbits_le32(0x06000894, 0x00777777, 0x00111111);
+}
+
+static void clock_dbg_set(unsigned char pattern)
+{
+	clrsetbits_le32(0x060008a0, 0xff << 6, (pattern & 0xff) << 6);
+	__asm__ __volatile__ ("dmb; isb;");
+}
+#else
+static void clock_dbg_init(void)
+{
+}
+
+static void clock_dbg_set(unsigned int pattern)
+{
+}
+#endif
+
+void clock_set_pllbias(void)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	clrsetbits_le32(&ccm->pll1_c0cpux_bias, 0x1f << 16, 0x04 << 16);
+	clrsetbits_le32(&ccm->pll2_c1cpux_bias, 0x1f << 16, 0x04 << 16);
+	clrsetbits_le32(&ccm->pll3_audio_bias, 0x1f << 16, 0x04 << 16);
+	clrsetbits_le32(&ccm->pll4_periph0_bias, 0x1f << 16, 0x04 << 16);
+	clrsetbits_le32(&ccm->pll5_ve_bias, 0x1f << 16, 0x04 << 16);
+	clrsetbits_le32(&ccm->pll6_ddr_bias, 0x1f << 16, 0x04 << 16);
+	clrsetbits_le32(&ccm->pll7_video0_bias, 0x1f << 16, 0x04 << 16);
+	clrsetbits_le32(&ccm->pll8_video1_bias, 0x1f << 16, 0x04 << 16);
+	clrsetbits_le32(&ccm->pll9_gpu_bias, 0x1f << 16, 0x04 << 16);
+	clrsetbits_le32(&ccm->pll10_de_bias, 0x1f << 16, 0x04 << 16);
+	clrsetbits_le32(&ccm->pll11_isp_bias, 0x1f << 16, 0x04 << 16);
+	clrsetbits_le32(&ccm->pll12_periph1_bias, 0x1f << 16, 0x04 << 16);
+}
+
+
 void clock_init_safe(void)
 {
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
+	clock_dbg_init();
+	clock_dbg_set(0x81);
+
+	sdelay(2000*1000);
+
+	/* Switch cluster 0 to 24MHz clock while changing PLL1 */
+	writel(0, &ccm->cpu_clk_source);
+
+	__asm__ __volatile__ ("dmb; isb;");
+
+	/* At high temperatures, our PLLs may take a while to become stable.
+	   Let's wait 10000us (10ms) for each. */
+	writel(10000, &ccm->pll_stable_time0);
+	writel(10000, &ccm->pll_stable_time1);
+
+	//	clock_set_pllbias();
+
 	/* Set up PLL12 (peripheral 1) */
 	clock_set_pll12(1200000000);
 
-	/* Set up PLL1 (cluster 0) and PLL2 (cluster 1) */
-	clock_set_pll1(408000000);
-	clock_set_pll2(408000000);
+	clock_dbg_set(0xF2);
+	sdelay(1000*1000);
+	clock_dbg_set(0x82);
 
 	/* Set up PLL4 (peripheral 0) */
 	clock_set_pll4(960000000);
 
+	clock_dbg_set(0x88);
+
 	/* Set up dividers for AXI0 and APB0 on cluster 0: PLL1 / 2 = 204MHz */
 	writel(C0_CFG_AXI0_CLK_DIV_RATIO(2) | C0_CFG_APB0_CLK_DIV_RATIO(2), &ccm->c0_cfg);
 
+	clock_dbg_set(0x90);
+
 	/* GTBUS: 400MHz (PERIPH1 div 3) */
 	writel(GTBUS_SRC_PLL_PERIPH1 | GTBUS_CLK_DIV_RATIO(3), &ccm->gtbus_cfg);
+
+	clock_dbg_set(0xa0);
+
+	__asm__ __volatile__ ("dmb; isb;");
+
+	writel(CCI400_CLK_DIV_RATIO(2), &ccm->cci400_cfg);
+	sdelay(100000);
 	/* CCI400: 600MHz (PERIPH1 div 2) */
 	writel(CCI400_SRC_PLL_PERIPH1 | CCI400_CLK_DIV_RATIO(2), &ccm->cci400_cfg);
 
+	__asm__ __volatile__ ("dmb; isb;");
+
+	clock_dbg_set(0xc0);
+
 	writel(AHB0_SRC_GTBUS_CLK   | AHBx_CLK_DIV_RATIO(2), &ccm->ahb0_cfg); /* AHB0: 200MHz */
+
+	clock_dbg_set(0xc1);
+
 	writel(AHB1_SRC_GTBUS_CLK   | AHBx_CLK_DIV_RATIO(2), &ccm->ahb1_cfg); /* AHB1: 200MHz */
+
+	clock_dbg_set(0xc2);
+
 	writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(8), &ccm->ahb2_cfg); /* AHB2: 120MHz */
+
+	clock_dbg_set(0xc4);
+
+	writel(APB0_CLK_DIV_RATIO(8), &ccm->apb0_cfg);
 	writel(APB0_SRC_PLL_PERIPH0 | APB0_CLK_DIV_RATIO(8), &ccm->apb0_cfg); /* APB0: 120MHz */
 
+	clock_dbg_set(0xc8);
+
+	/* Set up PLL1 (cluster 0) and PLL2 (cluster 1) */
+	clock_set_pll1(408000000);
+	clock_set_pll2(408000000);
+
+	clock_dbg_set(0x84);
+
 	/* Deassert DMA reset and open clock gating for DMA */
 	setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24));
 	setbits_le32(&ccm->apb1_gate, (1 << 24));
 
+	clock_dbg_set(0xd0);
+
 	/* set enable-bit in TSTAMP_CTRL_REG */
 	writel(1, 0x01720000);
+
+	clock_dbg_set(0xe0);
+
+	clock_set_pllbias();
+	clock_dbg_set(0xf0);
 }
 #endif
 
@@ -81,16 +181,22 @@ void clock_set_pll1(unsigned int clk)
 	/* Switch cluster 0 to 24MHz clock while changing PLL1 */
 	clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK, C0_CPUX_CLK_SRC_OSC24M);
 
+	__asm__ __volatile__ ("dmb; isb;");
+
 	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CCM_PLL1_CLOCK_TIME_2 |
 	       CCM_PLL1_CTRL_N(clk / 24000000),
 	       &ccm->pll1_c0_cfg);
 	/* Don't bother with the stable-time registers, as it doesn't wait until the PLL is
 	   stable.  Note, that even Allwinner just uses a delay loop (or rather the AVS timer)
 	   for this instead of the PLL_STABLE_STATUS register. */
-	sdelay(2000);
+	sdelay(200000);
+
+	__asm__ __volatile__ ("dmb; isb;");
 
 	/* Switch cluster 0 back to PLL1 */
 	clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK, C0_CPUX_CLK_SRC_PLL1);
+
+	__asm__ __volatile__ ("dmb; isb;");
 }
 
 void clock_set_pll2(unsigned int clk)
@@ -102,14 +208,18 @@ void clock_set_pll2(unsigned int clk)
 	/* Switch cluster 1 to 24MHz clock while changing PLL2 */
 	clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, C1_CPUX_CLK_SRC_OSC24M);
 
+	__asm__ __volatile__ ("dmb; isb;");
+
 	writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) | CCM_PLL2_CLOCK_TIME_2 |
 	       CCM_PLL2_CTRL_N(clk / 24000000),
 	       &ccm->pll2_c1_cfg);
 
-	sdelay(2000);
+	sdelay(200000);
+	__asm__ __volatile__ ("dmb; isb;");
 
 	/* Switch cluster 1 back to PLL2 */
 	clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, C1_CPUX_CLK_SRC_PLL2);
+	__asm__ __volatile__ ("dmb; isb;");
 }
 
 void clock_set_pll6(unsigned int clk)
@@ -130,12 +240,26 @@ void clock_set_pll12(unsigned int clk)
 {
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	unsigned int val;
 
 	if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN)
 	  return;
 
-	writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000),
-	       &ccm->pll12_periph1_cfg);
+	val = CCM_PLL12_CTRL_N(clk / 24000000);
+	writel(val, &ccm->pll12_periph1_cfg);
+
+	clock_dbg_set(0x55);
+
+	while (readl(&ccm->pll12_periph1_cfg) != val)
+		/* spin */ ;
+	setbits_le32(&ccm->pll12_periph1_cfg, CCM_PLL12_CTRL_EN);
+
+	clock_dbg_set(0xAA);
+
+	//	writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000),
+	//	       &ccm->pll12_periph1_cfg);
+
+	do { } while (!(readl(&ccm->pll_stable_status) & PLL_PERIPH1_STATUS));
 
 	sdelay(2000);
 }
@@ -146,6 +270,9 @@ void clock_set_pll4(unsigned int clk)
 	struct sunxi_ccm_reg * const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
+	if (readl(&ccm->pll4_periph0_cfg) & CCM_PLL4_CTRL_EN)
+		return;
+
 	writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000),
 	       &ccm->pll4_periph0_cfg);
 
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index b79eceaba2..f9ec294aea 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -37,9 +37,23 @@ struct sunxi_ccm_reg {
 	u8 reserved3[0x04];	/* 0x7c */
 	u32 ats_cfg;		/* 0x80 ats clock configuration */
 	u32 trace_cfg;		/* 0x84 trace clock configuration */
-	u8 reserved4[0x14];     /* 0x88 */
+	u8 reserved4[0xc];      /* 0x88 */
+        u32 pll_stable_time0;   /* 0x90 */
+        u32 pll_stable_time1;   /* 0x94 */
 	u32 pll_stable_status;  /* 0x9c */
-	u8 reserved5[0xe0];	/* 0xa0 */
+        u32 pll1_c0cpux_bias;   /* 0xa0 */
+        u32 pll2_c1cpux_bias;   /* 0xa4 */
+        u32 pll3_audio_bias;    /* 0xa8 */
+        u32 pll4_periph0_bias;  /* 0xac */
+        u32 pll5_ve_bias;       /* 0xb0 */
+        u32 pll6_ddr_bias;      /* 0xb4 */
+        u32 pll7_video0_bias;   /* 0xb8 */
+        u32 pll8_video1_bias;   /* 0xbc */
+        u32 pll9_gpu_bias;      /* 0xc0 */
+        u32 pll10_de_bias;      /* 0xc4 */
+        u32 pll11_isp_bias;     /* 0xc8 */
+        u32 pll12_periph1_bias; /* 0xcc */
+	u8 reserved5[0xb0];	/* 0xd0 */
 	u32 clk_output_a;	/* 0x180 clk_output_a */
 	u32 clk_output_b;	/* 0x184 clk_output_a */
 	u8 reserved6[0x278];	/* 0x188 */