From df02dd828c4ef2311c7c271f2c95384fc555961b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jul 2014 15:54:39 +0800 Subject: ARM: sun8i: Add PRCM clock and reset controller nodes to the DTSI With sun8i PRCM support available, we can add the PRCM clock and reset controller nodes to the DTSI. Also update R_UART's clock phandle and add it's reset control phandle. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23.dtsi | 47 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) (limited to 'arch/arm/boot/dts/sun8i-a23.dtsi') diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 886776d09c06..54ac0787216a 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -285,13 +285,58 @@ interrupts = <1 9 0xf04>; }; + prcm@01f01400 { + compatible = "allwinner,sun8i-a23-prcm"; + reg = <0x01f01400 0x200>; + + ar100: ar100_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "ar100"; + }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&ar100>; + clock-output-names = "ahb0"; + }; + + apb0: apb0_clk { + compatible = "allwinner,sun8i-a23-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: apb0_gates_clk { + compatible = "allwinner,sun8i-a23-apb0-gates-clk"; + #clock-cells = <1>; + clocks = <&apb0>; + clock-output-names = "apb0_pio", "apb0_timer", + "apb0_rsb", "apb0_uart", + "apb0_i2c"; + }; + + apb0_rst: apb0_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + }; + r_uart: serial@01f02800 { compatible = "snps,dw-apb-uart"; reg = <0x01f02800 0x400>; interrupts = <0 38 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb0_gates 4>; + resets = <&apb0_rst 4>; status = "disabled"; }; }; -- cgit v1.2.3