From c9cf996d854b8f96d450083d3e0aace457a5a46b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 8 May 2016 18:41:57 +0200 Subject: ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI The Exynos5410/542x/5800 are very similar designs. Create a new DTSI with common nodes to remove DTS duplication. Although currently only MCT and SysRAM are shared but in future more nodes will be added to the common file. The patch should not have functional impact. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5420.dtsi | 54 +++++---------------------------------- 1 file changed, 6 insertions(+), 48 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index fa8bda836cef..2d9f43b8cc15 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -13,9 +13,8 @@ * published by the Free Software Foundation. */ +#include "exynos54xx.dtsi" #include -#include "exynos5.dtsi" - #include / { @@ -181,24 +180,6 @@ }; }; - sysram@02020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x54000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x54000>; - - smp-sysram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sysram@53000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x53000 0x1000>; - }; - }; - clock: clock-controller@10010000 { compatible = "samsung,exynos5420-clock"; reg = <0x10010000 0x30000>; @@ -261,34 +242,6 @@ status = "disabled"; }; - mct: mct@101C0000 { - compatible = "samsung,exynos4210-mct"; - reg = <0x101C0000 0xB00>; - interrupt-parent = <&mct_map>; - interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, - <8>, <9>, <10>, <11>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - - mct_map: mct-map { - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = <0 &combiner 23 3>, - <1 &combiner 23 4>, - <2 &combiner 25 2>, - <3 &combiner 25 3>, - <4 &gic 0 120 0>, - <5 &gic 0 121 0>, - <6 &gic 0 122 0>, - <7 &gic 0 123 0>, - <8 &gic 0 128 0>, - <9 &gic 0 129 0>, - <10 &gic 0 130 0>, - <11 &gic 0 131 0>; - }; - }; - nocp_mem0_0: nocp@10CA1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -1570,6 +1523,11 @@ pinctrl-0 = <&i2c3_bus>; }; +&mct { + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; +}; + &pwm { clocks = <&clock CLK_PWM>; clock-names = "timers"; -- cgit v1.2.3