From b155e5ebb2bb51e8cb06cbabbaf5b1c42d2c1328 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Mon, 5 Sep 2016 15:29:05 +0200 Subject: ARM: dts: sun9i: Add DVFS infrastructure for sun9i To enable DVFS on the Allwinner A80, we need operating points for both the Cortex-A7 and Cortex-A15 cores and proper modelling of the C0CPUX and C1CPUX clocks. Signed-off-by: Philipp Tomsich --- arch/arm/boot/dts/sun9i-a80.dtsi | 172 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 164 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index db937aa67789..50a318260e5a 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -1,7 +1,9 @@ /* * Copyright 2014 Chen-Yu Tsai + * Copyright 2016 Theobroma Systems Design und Consulting GmbH * * Chen-Yu Tsai + * Dr. Philipp Tomsich * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -59,63 +61,87 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; + clocks = <&c0cpux>; + clock-frequency = <1200000000>; + operating-points-v2 = <&cluster_a7_opp_table>; reg = <0x0>; + + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; }; cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; + clocks = <&c0cpux>; cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; + clock-frequency = <1200000000>; + operating-points-v2 = <&cluster_a7_opp_table>; reg = <0x1>; }; cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; + clocks = <&c0cpux>; cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; + clock-frequency = <1200000000>; + operating-points-v2 = <&cluster_a7_opp_table>; reg = <0x2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; + clocks = <&c0cpux>; cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; + clock-frequency = <1200000000>; + operating-points-v2 = <&cluster_a7_opp_table>; reg = <0x3>; }; cpu4: cpu@100 { compatible = "arm,cortex-a15"; device_type = "cpu"; + clocks = <&c1cpux>; cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; + clock-frequency = <1800000000>; + operating-points-v2 = <&cluster_a15_opp_table>; reg = <0x100>; + + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <7>; }; cpu5: cpu@101 { compatible = "arm,cortex-a15"; device_type = "cpu"; + clocks = <&c1cpux>; cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; + clock-frequency = <1800000000>; + operating-points-v2 = <&cluster_a15_opp_table>; reg = <0x101>; }; cpu6: cpu@102 { compatible = "arm,cortex-a15"; device_type = "cpu"; + clocks = <&c1cpux>; cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; + clock-frequency = <1800000000>; + operating-points-v2 = <&cluster_a15_opp_table>; reg = <0x102>; }; cpu7: cpu@103 { compatible = "arm,cortex-a15"; device_type = "cpu"; + clocks = <&c1cpux>; cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; + clock-frequency = <1800000000>; + operating-points-v2 = <&cluster_a15_opp_table>; reg = <0x103>; }; }; @@ -162,6 +188,54 @@ clock-output-names = "osc24M"; }; + pllc0cpux: clk@06000000 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-pllc0cpux-clk"; + reg = <0x06000000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pllc0cpux"; + }; + + pllc1cpux: clk@06000004 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-pllc1cpux-clk"; + reg = <0x06000004 0x4>; + clocks = <&osc24M>; + clock-output-names = "pllc1cpux"; + }; + + axi0: c0cpux_clkcfg@06000054 { + compatible = "allwinner,sun9i-a80-c0clkcfg", "syscon"; + reg = <0x06000054 0x4>; + }; + + c0cpux: c0cpux@06000050 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-c0cpux-clk"; + reg = <0x06000050 0x4>; + clocks = <&osc24M>, <&pllc0cpux>; + clock-output-names = "c0cpux"; + + allwinner,sun9i-a80-clkcfg = <&axi0>; + allwinner,sun9i-a80-clkcfg-default = <0x102>; + }; + + axi1: c1cpux_clkcfg@06000058 { + compatible = "allwinner,sun9i-a80-c1clkcfg", "syscon"; + reg = <0x06000058 0x4>; + }; + + c1cpux: c1cpux@06000050 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-c1cpux-clk"; + reg = <0x06000050 0x4>; + clocks = <&osc24M>, <&pllc1cpux>; + clock-output-names = "c1cpux"; + + allwinner,sun9i-a80-clkcfg = <&axi1>; + allwinner,sun9i-a80-clkcfg-default = <0x102>; + }; + /* * The 32k clock is from an external source, normally the * AC100 codec/RTC chip. This clock is by default enabled @@ -847,6 +921,88 @@ allwinner,pull = ; }; + cluster_a15_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + opp@1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1020000>; + clock-latency-ns = <140000>; + }; + opp@1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <960000>; + clock-latency-ns = <140000>; + }; + opp@1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <940000>; + clock-latency-ns = <140000>; + }; + opp@1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <920000>; + clock-latency-ns = <140000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <900000>; + clock-latency-ns = <140000>; + }; + opp@1080000000 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <840000>; + clock-latency-ns = <140000>; + }; + opp@384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt = <840000>; + clock-latency-ns = <200000>; + }; + }; + + + cluster_a7_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp@1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-microvolt = <1060000>; + clock-latency-ns = <200000>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1020000>; + clock-latency-ns = <200000>; + }; + opp@1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <960000>; + clock-latency-ns = <200000>; + }; + opp@984000000 { + opp-hz = /bits/ 64 <984000000>; + opp-microvolt = <960000>; + clock-latency-ns = <200000>; + }; + opp@912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp@720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <840000>; + clock-latency-ns = <200000>; + }; + opp@480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <840000>; + clock-latency-ns = <200000>; + }; + }; + }; + }; uart0: serial@07000000 { -- cgit v1.2.3