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2016-09-18ARM: dts: sun9i: Add DVFS infrastructure for sun9iPhilipp Tomsich
To enable DVFS on the Allwinner A80, we need operating points for both the Cortex-A7 and Cortex-A15 cores and proper modelling of the C0CPUX and C1CPUX clocks. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2016-09-18ARM: dts: sun9i: Add PRCM device node for the A80 dtsiChen-Yu Tsai
The PRCM is a collection of clock controls, reset controls, and various power switches/gates. Some of these can be independently listed and supported, while a number of CPU related ones are used in tandem with CPUCFG for SMP bringup and CPU hotplugging. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2016-09-18ARM: dts: sun9i: Add CPUCFG device node for A80 dtsiChen-Yu Tsai
CPUCFG is a collection of registers that are mapped to the SoC's signals from each individual processor core and associated peripherals, such as resets for processors, L1/L2 cache and other things. These registers are used for SMP bringup and CPU hotplugging. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2016-09-18ARM: dts: sun9i: Add CCI-400 device nodes for A80Chen-Yu Tsai
The A80 includes an ARM CCI-400 interconnect to support multi-cluster CPU caches. Also add the maximum clock frequency for the CPUs, as listed in the A80 Optimus Board FEX file. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2016-09-18ARM: dts: sun9i: Add secure SRAM node used for MCPM SMP hotplugChen-Yu Tsai
The A80 stores some magic flags in a portion of the secure SRAM. The BROM jumps directly to the software entry point set by the SMP code if the flags are set. This is required for CPU0 hotplugging. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2016-09-18ARM: dts: sun9i: added uart5 pin definitionKlaus Goger
Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2016-09-18ARM: dts: sun9i: added GMACKlaus Goger
sun9i uses the same MAC as sun6i with a different base address. Also the clocking/gateing bits are in some differenet location and not documented in the user manual. This commit only adds the RGMII pin definitions Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2016-01-25ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pinsChen-Yu Tsai
mmc2_8bit_pins is used with eMMC chips, which also have a reset pin. The MMC controller also has a reset output that is supported. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-01-25ARM: dts: sun9i: Use sun9i specific mmc compatibleChen-Yu Tsai
sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA trigger levels can be increased. Also, the mmc module clock parent has a higher clock rate, and the sample and output delay phases are different. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-03ARM: dts: sun9i: Add NMI controller device nodeChen-Yu Tsai
The Allwinner A80 SoC has an NMI controller. NMI is an external interrupt pin exclusely used with PMICs and other system critical peripherals (such as RTC) in Allwinner's reference designs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-01ARM: dts: sun9i: Add Reduced Serial Bus controller device node to A80 dtsiChen-Yu Tsai
This patch adds a device node for the Reduced Serial Bus (RSB) controller and the defacto pinmux setting to the A80 dtsi. Since there is only one possible pinmux setting for RSB, just set it in the dtsi. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-01ARM: dts: sun9i: Add consumer IR receiver device node and pinmux settingsChen-Yu Tsai
The Allwinner A80 SoC has a consumer IR receiver, which is the same as older SoCs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-01ARM: dts: sun9i: Add A80 R_PIO pin controller device nodeChen-Yu Tsai
The A80 has a secondary pin controller. Add a device node for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-01ARM: dts: sun9i: Add TODO comments for the main and low power clocksChen-Yu Tsai
The main (24MHz) clock on the A80 is configurable via the PRCM address space. The low power/speed (32kHz) clock is from an external chip, the AC100. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-01ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodesChen-Yu Tsai
This adds the supported PRCM clocks and reset controls to the A80 dtsi. The DAUDIO module clocks are not supported yet. Also update clock and reset phandles for r_uart. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-10-17ARM: dts: sunxi: Fix interrupt-cells for [r]pio on A23/A31/A33/A80Hans de Goede
When the gpio interrupt bindings where changed to add a bank to the specifier list, the r_pio nodes of A23/A31/A33 where not updated to match and neither was the pio node of the A80, this fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-08-12ARM: sun9i: Wrap the clock-indicesMaxime Ripard
Wrap the clock-indices to match the wrapping of the clock-output-names in order to make it easier to match indices to names. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-06-01ARM: dts: sun9i: Add device node for watchdogChen-Yu Tsai
On A80 there are 2 watchdogs, one in the main block, and one in the R (special) block. We do not have information on the R block watchdog, other than the register layout is the same, and the interrupt number. Both are able to reset the whole system. Add the main watchdog, in case the R block is used for special purposes like running an RTOS. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-05-10ARM: sunxi: DT: Fix lines over 80 charactersMaxime Ripard
A few lines in our DTSIs are over the 80 characters limit, making checkpatch complain about that. If possible (and relevant), wrap these lines to 80 characters. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-05-10ARM: sunxi: dt: Remove the FSF addressMaxime Ripard
The FSF address triggers a warning on checkpatch, saying that the FSF license is already present in the Linux source code, and that it has already changed in the past. Remove it from our DT, as suggested. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-04-27ARM: dts: sun9i: Enable ARM architected timer on A80Chen-Yu Tsai
The A80 SoC has the architected timer, but the existing firmware from Allwinner does not set CNTFRQ at all. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-04-27ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodesHans de Goede
Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-04-27ARM: dts: sun9i: Add USB host controller nodes to a80 dtsiChen-Yu Tsai
The A80 has 3 EHCI/OHCI USB controllers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-04-27ARM: dts: sun9i: Add usb phy nodes to a80 dtsiChen-Yu Tsai
On sun9i, there are 3 independent usb phys for EHCI/OHCI. Add device nodes for them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-04-27ARM: dts: sun9i: Add usb clock nodes to a80 dtsiChen-Yu Tsai
The USB controller and phy clocks and resets have a separate address block and driver. Add the nodes to represent them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-02-17Merge tag 'dt-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Olof Johansson: "DT changes continue to be the bulk of our merge window contents. We continue to have a large set of changes across the board as new platforms and drivers are added. Some of the new platforms are: - Alphascale ASM9260 - Marvell Armada 388 - CSR Atlas7 - TI Davinci DM816x - Hisilicon HiP01 - ST STiH418 There have also been some sweeping changes, including relicensing of DTS contents from GPL to GPLv2+/X11 so that the same files can be reused in other non-GPL projects more easily. There's also been changes to the DT Makefile to make it a little less conflict-ridden and churny down the road" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits) ARM: dts: Add PPMU node for exynos4412-trats2 ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato ARM: dts: Add PPMU dt node for exynos4 and exynos4210 ARM: dts: Add PPMU dt node for exynos3250 ARM: dts: add mipi dsi device node for exynos4415 ARM: dts: add fimd device node for exynos4415 ARM: dts: Add syscon phandle to the video-phy node for Exynos4 ARM: dts: Add sound nodes for exynos4412-trats2 ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2 ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi ARM: dts: Add max77693 charger node for exynos4412-trats2 ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2 ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2 ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2 ARM: dts: am57xx-beagle-x15: Fix USB2 mode ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB ARM: dts: dra72-evm: Add extcon nodes for USB ARM: dts: dra7-evm: Add extcon nodes for USB ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb ...
2015-01-25ARM: sunxi: dt: Fix aliasesMaxime Ripard
Commit f77d55a3b56a ("serial: 8250_dw: get index of serial line from DT aliases") made the serial driver now use the serial aliases to get the tty number, pointing out that our aliases have been wrong all along. Remove them from the DTSI and add custom ones in the relevant boards. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21ARM: dts: sun9i: Add 8 bit mmc pinmux setting for mmc2Chen-Yu Tsai
mmc2 is available on port C. Add a pinmux setting for 8 bit wide eMMC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21ARM: dts: sun9i: Add mmc controller nodes to the A80 dtsiChen-Yu Tsai
The A80 has 4 mmc controllers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21ARM: dts: sun9i: Add mmc config clock nodesChen-Yu Tsai
Add the device tree nodes for the mmc config clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21ARM: dts: sun9i: Add pinmux setting for mmc0Chen-Yu Tsai
mmc0 is only available on port F, and is always used with a 4 bit wide bus for the onboard micro-sd slot. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21ARM: dts: sun9i: Add clock-indices property for bus gate clocksChen-Yu Tsai
of_clk_get_parent_name() uses the clock-indices property to resolve clock phandle arguments in case that the argument index does not match the clock-output-names sequence. This is the case on sunxi, where we use the actual bit index as the argument to the phandle. Add the clock-indices property so that of_clk_get_parent_name() resolves the names correctly. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21ARM: dts: sun9i: Add mmc module clock nodes for A80Chen-Yu Tsai
The mmc module clocks are A80 specific module 0 (storage) type clocks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21ARM: sunxi: DT: Convert the DTs to use the GIC headersMaxime Ripard
The GIC requires some extra opaque arguments to set the IRQ type and flags. Convert the DTs to using the common defines. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21ARM: sunxi: DT: Convert the DTs to use a header for the pinctrl nodesMaxime Ripard
The pinctrl nodes require some extra opaque arguments for the pull up and drive strength values. Introduce a new header file and convert the device trees to replace these opaque numbers by defines. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21ARM: sunxi: DT: Convert to device tree includesMaxime Ripard
Prepare the device trees to use the C preprocessor. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-31ARM: dts: sun9i: Add uart4 pinmux setting for A80 SoCChen-Yu Tsai
uart4 only has one possible pinmux setting on the A80 SoC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-31ARM: dts: sun9i: Add i2c3 pinmux setting for A80 SoCChen-Yu Tsai
i2c3 has only one possible pinmux setting on the A80 SoC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-31ARM: dts: sun9i: Add i2c controller nodes to a80 dtsiChen-Yu Tsai
The A80 has 5 i2c controllers in the main processor block. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-30ARM: sun9i: optimus: Set UART0 muxingMaxime Ripard
Enable the UART0 muxing, as set up by the bootloader. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-30ARM: sun9i: Enable the A80 pinctrl driverMaxime Ripard
The A80 pinctrl driver is just as usual our pinctrl/gpio/external interrupt controller. Nothing really out of the extraordinary here... Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-27ARM: sunxi: Fix GPLv2 wordingMaxime Ripard
During the GPL to GPL/X11 licensing migration, the GPL notice introduced mentionned the device trees as a library, which is not really accurate. It began to spread by copy and paste. Fix all these library mentions to reflect the file that it's actually just a file. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-21ARM: dts: sun9i: Add basic clocks and reset controlsChen-Yu Tsai
Now that we have driver support for the basic clocks, add them to the dtsi and update existing peripherals. Also add reset controls to match. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-20ARM: dts: sunxi: Add Allwinner A80 dtsiChen-Yu Tsai
The Allwinner A80 is a new multi-purpose SoC with 4 Cortex-A7 and 4 Cortex-A15 cores in a big.LITTLE architecture, and a 64-core PowerVR G6230 GPU. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Andreas Färber <afaerber@suse.de>
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