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authorKlaus Goger <klaus.goger@theobroma-systems.com>2016-08-19 22:53:58 +0200
committerKlaus Goger <klaus.goger@theobroma-systems.com>2016-09-18 15:44:23 +0200
commit5b09708972bafb7cc4aa64a52528bf4b553aeb7e (patch)
tree93e0d682bfb27fbd4ee6e510100eda5e3e027436
parentd38a46b26a2711c0f5676dd4d6481f0a446645ba (diff)
ARM: dts: sun9i: added GMAC
sun9i uses the same MAC as sun6i with a different base address. Also the clocking/gateing bits are in some differenet location and not documented in the user manual. This commit only adds the RGMII pin definitions Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
-rw-r--r--arch/arm/boot/dts/sun9i-a80.dtsi61
1 files changed, 61 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index f68b3242b33a..a7f8d8a02a15 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -438,6 +438,37 @@
clocks = <&osc32k>, <&osc24M>;
clock-output-names = "r_ir";
};
+
+ /*
+ * The following two are dummy clocks, placeholders
+ * used in the gmac_tx clock. The gmac driver will
+ * choose one parent depending on the PHY interface
+ * mode, using clk_set_rate auto-reparenting.
+ *
+ * The actual TX clock rate is not controlled by the
+ * gmac_tx clock.
+ */
+ mii_phy_tx_clk: clk@1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "mii_phy_tx";
+ };
+
+ gmac_int_tx_clk: clk@2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_int_tx";
+ };
+
+ gmac_tx_clk: clk@00800030 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-gmac-clk";
+ reg = <0x00800030 0x4>;
+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+ clock-output-names = "gmac_tx";
+ };
};
soc {
@@ -686,6 +717,19 @@
#size-cells = <0>;
#gpio-cells = <3>;
+ gmac_pins_rgmii_a: gmac_rgmii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA4", "PA5", "PA7", "PA8", "PA9",
+ "PA10", "PA12", "PA13", "PA16", "PA17" ;
+ allwinner,function = "gmac";
+ /*
+ * data lines in RGMII mode use DDR mode
+ * and need a higher signal drive strength
+ * /
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
i2c3_pins_a: i2c3@0 {
allwinner,pins = "PG10", "PG11";
allwinner,function = "i2c3";
@@ -931,5 +975,22 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ gmac: ethernet@00830000 {
+ compatible = "allwinner,sun7i-a20-gmac";
+ reg = <0x00830000 0x1054>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
+ clock-names = "stmmaceth", "allwinner_gmac_tx";
+ resets = <&ahb1_resets 17>;
+ reset-names = "stmmaceth";
+ snps,pbl = <2>;
+ snps,fixed-burst;
+ snps,force_sf_dma_mode;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
};