From d71e6d83612df896774ec4c03d49500312d2c324 Mon Sep 17 00:00:00 2001 From: Jakob Unterwurzacher Date: Tue, 3 Oct 2017 11:15:54 +0200 Subject: puma: fix gpio reset pin muxing and polarity This change is Puma RK3399-Q7 specific. Do not merge upstream. On the Puma RK3399-Q7, the Linux kernel muxes the overtemp output to the reset pin. Restore GPIO functionality. Additionally, the Puma RK3399-Q7 needs a polarity of 1 instead of the default 0. This currently cannot be set through the FDT, so hardcode it here for now. --- plat/rockchip/rk3399/drivers/pmu/pmu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index 9c0a29c1..84558d19 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -1210,6 +1210,13 @@ void __dead2 rockchip_soc_soft_reset(void) rst_gpio = plat_get_rockchip_gpio_reset(); if (rst_gpio) { + // On the Puma RK3399-Q7, the Linux kernel muxes the overtemp output to the reset + // pin. Restore GPIO functionality. + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX, GPIO1A6_IOMUX); + // Additionally, the Puma RK3399-Q7 needs a polarity of 1 instead of the + // default 0. This currently cannot be set through the FDT, so fix it here. + rst_gpio->polarity = 1; + gpio_set_direction(rst_gpio->index, GPIO_DIR_OUT); gpio_set_value(rst_gpio->index, rst_gpio->polarity); } else { -- cgit v1.2.3