From 85750091ba6227428f2eb3422356708e8e88b7e9 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Wed, 31 May 2017 18:42:37 +0200 Subject: [WIP] RK3399-Q7 --- bl31/bl31.ld.S | 1 + plat/rockchip/common/aarch64/platform_common.c | 26 +++++ plat/rockchip/common/bl31_plat_setup.c | 128 ++++++++++++++++++++++++- plat/rockchip/common/pmusram/pmu_sram.c | 2 +- plat/rockchip/rk3399/drivers/pmu/m0_ctl.h | 2 +- plat/rockchip/rk3399/include/plat.ld.S | 4 +- plat/rockchip/rk3399/include/platform_def.h | 2 +- plat/rockchip/rk3399/platform.mk | 1 - 8 files changed, 160 insertions(+), 6 deletions(-) diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 48861f40..c14595cc 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -36,6 +36,7 @@ SECTIONS } >RAM .rodata . : { + . = ALIGN(4096); __RODATA_START__ = .; *(.rodata*) diff --git a/plat/rockchip/common/aarch64/platform_common.c b/plat/rockchip/common/aarch64/platform_common.c index 9c68b3bc..da2fb974 100644 --- a/plat/rockchip/common/aarch64/platform_common.c +++ b/plat/rockchip/common/aarch64/platform_common.c @@ -26,6 +26,8 @@ static const int cci_map[] = { * Macro generating the code for the function setting up the pagetables as per * the platform memory map & initialize the mmu, for the given exception level ******************************************************************************/ +#if 0 + #define DEFINE_CONFIGURE_MMU_EL(_el) \ void plat_configure_mmu_el ## _el(unsigned long total_base, \ unsigned long total_size, \ @@ -50,6 +52,30 @@ static const int cci_map[] = { enable_mmu_el ## _el(0); \ } +#else +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void plat_configure_mmu_el ## _el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit, \ + unsigned long coh_start, \ + unsigned long coh_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(coh_start, coh_start, \ + coh_limit - coh_start, \ + MT_DEVICE | MT_RW | MT_SECURE); \ + mmap_add(plat_rk_mmap); \ + rockchip_plat_sram_mmu_el##_el(); \ + init_xlat_tables(); \ + \ + enable_mmu_el ## _el(0); \ + } + +#endif + /* Define EL3 variants of the function initialising the MMU */ DEFINE_CONFIGURE_MMU_EL(3) diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index 71d66c97..65aea75d 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -31,7 +31,12 @@ unsigned long __RO_END__; #define BL31_RO_BASE (unsigned long)(&__RO_START__) #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) -static entry_point_info_t bl32_ep_info; +#define BL31_TEXT_START (unsigned long)(&__TEXT_START__) +#define BL31_RO_END (unsigned long)(&__RODATA_END__) + +#define BL31_END (uintptr_t)(&__BL31_END__) + +//static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; /******************************************************************************* @@ -42,6 +47,12 @@ static entry_point_info_t bl33_ep_info; ******************************************************************************/ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) { +#if 1 + assert(sec_state_is_valid(type)); + assert(type == NON_SECURE); + + return &bl33_ep_info; +#else entry_point_info_t *next_image_info; next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; @@ -51,6 +62,7 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) return next_image_info; else return NULL; +#endif } #pragma weak params_early_setup @@ -66,6 +78,9 @@ void params_early_setup(void *plat_param_from_bl2) * BL2 has flushed this information to memory, so we are guaranteed to pick up * good data. ******************************************************************************/ +#include +#include + void bl31_early_platform_setup(bl31_params_t *from_bl2, void *plat_params_from_bl2) { @@ -77,16 +92,29 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, /* Passing a NULL context is a critical programming error */ assert(from_bl2); +#if 0 assert(from_bl2->h.type == PARAM_BL31); assert(from_bl2->h.version >= VERSION_1); bl32_ep_info = *from_bl2->bl32_ep_info; bl33_ep_info = *from_bl2->bl33_ep_info; +#endif + + /* + * Tell BL31 where the non-trusted software image + * is located and the entry state information + */ + bl33_ep_info.pc = 0x00200000; + bl33_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + SET_SECURITY_STATE(bl33_ep_info.h.attr, NON_SECURE); plat_rockchip_pmusram_prepare(); +#if 0 /* there may have some board sepcific message need to initialize */ params_early_setup(plat_params_from_bl2); +#endif } /******************************************************************************* @@ -107,14 +135,112 @@ void bl31_platform_setup(void) * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the mmu in a quick and dirty way. ******************************************************************************/ +/* + * Set up the page tables for the generic and platform-specific memory regions. + * The extents of the generic memory regions are specified by the function + * arguments and consist of: + * - Trusted SRAM seen by the BL image; + * - Code section; + * - Read-only data section; + * - Coherent memory region, if applicable. + */ + +#if 0 +const mmap_region_t plat_arm_mmap[] = { + { UART0_BASE, UART0_BASE, 0x10000, MT_DEVICE | MT_RW | MT_SECURE }, + { 0 } +}; +#endif + +const mmap_region_t *plat_arm_get_mmap(void) +{ + return plat_rk_mmap; +} + +void arm_setup_page_tables(uintptr_t total_base, + size_t total_size, + uintptr_t code_start, + uintptr_t code_limit, + uintptr_t rodata_start, + uintptr_t rodata_limit +#if USE_COHERENT_MEM + , + uintptr_t coh_start, + uintptr_t coh_limit +#endif + ) +{ + /* + * Map the Trusted SRAM with appropriate memory attributes. + * Subsequent mappings will adjust the attributes for specific regions. + */ + VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", + (void *) total_base, (void *) (total_base + total_size)); + mmap_add_region(total_base, total_base, + total_size, + MT_MEMORY | MT_RW | MT_SECURE); + + /* Re-map the code section */ + VERBOSE("Code region: %p - %p\n", + (void *) code_start, (void *) code_limit); + mmap_add_region(code_start, code_start, + code_limit - code_start, + MT_CODE | MT_SECURE); + + /* Re-map the read-only data section */ + VERBOSE("Read-only data region: %p - %p\n", + (void *) rodata_start, (void *) rodata_limit); + mmap_add_region(rodata_start, rodata_start, + rodata_limit - rodata_start, + MT_RO_DATA | MT_SECURE); + +#if USE_COHERENT_MEM + /* Re-map the coherent memory region */ + VERBOSE("Coherent region: %p - %p\n", + (void *) coh_start, (void *) coh_limit); + mmap_add_region(coh_start, coh_start, + coh_limit - coh_start, + MT_DEVICE | MT_RW | MT_SECURE); +#endif + + /* Now (re-)map the platform-specific memory regions */ + mmap_add(plat_arm_get_mmap()); + + /* Create the page tables to reflect the above mappings */ + init_xlat_tables(); +} + void bl31_plat_arch_setup(void) { plat_cci_init(); plat_cci_enable(); + + tf_printf("BL31_RO_BASE: %lx\n", BL31_RO_BASE); + tf_printf("BL31_RO_LIMIT: %lx\n", BL31_RO_LIMIT); + tf_printf("BL_COHERENT_RAM_BASE: %lx\n", BL_COHERENT_RAM_BASE); + tf_printf("BL_COHERENT_RAM_END: %lx\n", BL_COHERENT_RAM_END); + +#if 0 plat_configure_mmu_el3(BL31_RO_BASE, BL_COHERENT_RAM_END - BL31_RO_BASE, BL31_RO_BASE, BL31_RO_LIMIT, BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); +#else + arm_setup_page_tables(BL31_BASE, + BL31_END - BL31_BASE, + BL_CODE_BASE, + BL_CODE_END, + BL_RO_DATA_BASE, + BL_RO_DATA_END +#if USE_COHERENT_MEM + , BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END +#endif + ); + enable_mmu_el3(0); +#endif + + tf_printf("%s: still alive\n", __func__); } diff --git a/plat/rockchip/common/pmusram/pmu_sram.c b/plat/rockchip/common/pmusram/pmu_sram.c index 05ee762e..a2c35443 100644 --- a/plat/rockchip/common/pmusram/pmu_sram.c +++ b/plat/rockchip/common/pmusram/pmu_sram.c @@ -22,7 +22,7 @@ void u32_align_cpy(uint32_t *dst, const uint32_t *src, size_t bytes) void rockchip_plat_sram_mmu_el3(void) { -#ifdef PLAT_EXTRA_LD_SCRIPT +#if 0 /* def PLAT_EXTRA_LD_SCRIPT */ size_t sram_size; /* sram.text size */ diff --git a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.h b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.h index b313ec6a..5613c8e9 100644 --- a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.h +++ b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.h @@ -9,7 +9,7 @@ #include -#define M0_BINCODE_BASE ((uintptr_t)rk3399m0_bin) +#define M0_BINCODE_BASE ((uint32_t)0xff8c0000UL) /* (rk3399m0_bin) */ #define M0_PARAM_ADDR (M0_BINCODE_BASE + PARAM_ADDR) /* pmu_fw.c */ diff --git a/plat/rockchip/rk3399/include/plat.ld.S b/plat/rockchip/rk3399/include/plat.ld.S index 49206bea..957dcc10 100644 --- a/plat/rockchip/rk3399/include/plat.ld.S +++ b/plat/rockchip/rk3399/include/plat.ld.S @@ -6,6 +6,7 @@ #ifndef __ROCKCHIP_PLAT_LD_S__ #define __ROCKCHIP_PLAT_LD_S__ +/* MEMORY { SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE } @@ -25,7 +26,7 @@ SECTIONS * ---------------- * | sram data * ---------------- - */ + * / .incbin_sram : ALIGN(4096) { __sram_incbin_start = .; *(.sram.incbin) @@ -48,5 +49,6 @@ SECTIONS __bl31_sram_data_end = .; } >SRAM } +*/ #endif /* __ROCKCHIP_PLAT_LD_S__ */ diff --git a/plat/rockchip/rk3399/include/platform_def.h b/plat/rockchip/rk3399/include/platform_def.h index f4427d01..18e6daf5 100644 --- a/plat/rockchip/rk3399/include/platform_def.h +++ b/plat/rockchip/rk3399/include/platform_def.h @@ -99,7 +99,7 @@ #define PLAT_RK_G1S_IRQS RK3399_G1S_IRQS #define PLAT_RK_G0_IRQS RK3399_G0_IRQS -#define PLAT_RK_UART_BASE UART2_BASE +#define PLAT_RK_UART_BASE UART0_BASE #define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK #define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk index be3e11b9..84ec988f 100644 --- a/plat/rockchip/rk3399/platform.mk +++ b/plat/rockchip/rk3399/platform.mk @@ -52,7 +52,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_SOC}/plat_sip_calls.c \ ${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \ ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ - ${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c \ ${RK_PLAT_SOC}/drivers/pmu/m0_ctl.c \ ${RK_PLAT_SOC}/drivers/pwm/pwm.c \ ${RK_PLAT_SOC}/drivers/secure/secure.c \ -- cgit v1.2.3