From 239b085caab4cfd38708d5d1a7de8eb14bb952c7 Mon Sep 17 00:00:00 2001 From: Antonio Nino Diaz Date: Tue, 28 Feb 2017 10:58:25 +0000 Subject: TZC: rename included C file to a header C files shouldn't be included into others. This file only contains some macros and functions that can be made `static inline`, so it is ok to convert it into a header file. This is the only occurrence of a C file being included in another one in the codebase instead of using a header, other occurrences are a way of achieving backwards-compatibility. Functions therein have been qualified as `inline`. Change-Id: I88fe300f6d85a7f0740ef14c9cb8fa54849218e6 Signed-off-by: Antonio Nino Diaz --- drivers/arm/tzc/tzc400.c | 4 +- drivers/arm/tzc/tzc_common_private.c | 235 ---------------------------------- drivers/arm/tzc/tzc_common_private.h | 240 +++++++++++++++++++++++++++++++++++ drivers/arm/tzc/tzc_dmc500.c | 4 +- 4 files changed, 244 insertions(+), 239 deletions(-) delete mode 100644 drivers/arm/tzc/tzc_common_private.c create mode 100644 drivers/arm/tzc/tzc_common_private.h diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c index ca088c32..8c6f8ba6 100644 --- a/drivers/arm/tzc/tzc400.c +++ b/drivers/arm/tzc/tzc400.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ #include #include #include -#include "tzc_common_private.c" +#include "tzc_common_private.h" /* * Macros which will be used by common core functions. diff --git a/drivers/arm/tzc/tzc_common_private.c b/drivers/arm/tzc/tzc_common_private.c deleted file mode 100644 index 8b1ddf49..00000000 --- a/drivers/arm/tzc/tzc_common_private.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include - -#define DEFINE_TZC_COMMON_WRITE_ACTION(fn_name, macro_name) \ - static inline void _tzc##fn_name##_write_action( \ - uintptr_t base, \ - tzc_action_t action) \ - { \ - mmio_write_32(base + TZC_##macro_name##_ACTION_OFF, \ - action); \ - } - -#define DEFINE_TZC_COMMON_WRITE_REGION_BASE(fn_name, macro_name) \ - static inline void _tzc##fn_name##_write_region_base( \ - uintptr_t base, \ - int region_no, \ - unsigned long long region_base) \ - { \ - mmio_write_32(base + \ - TZC_REGION_OFFSET( \ - TZC_##macro_name##_REGION_SIZE, \ - region_no) + \ - TZC_##macro_name##_REGION_BASE_LOW_0_OFFSET, \ - (uint32_t)region_base); \ - mmio_write_32(base + \ - TZC_REGION_OFFSET( \ - TZC_##macro_name##_REGION_SIZE, \ - region_no) + \ - TZC_##macro_name##_REGION_BASE_HIGH_0_OFFSET, \ - (uint32_t)(region_base >> 32)); \ - } - -#define DEFINE_TZC_COMMON_WRITE_REGION_TOP(fn_name, macro_name) \ - static inline void _tzc##fn_name##_write_region_top( \ - uintptr_t base, \ - int region_no, \ - unsigned long long region_top) \ - { \ - mmio_write_32(base + \ - TZC_REGION_OFFSET \ - (TZC_##macro_name##_REGION_SIZE, \ - region_no) + \ - TZC_##macro_name##_REGION_TOP_LOW_0_OFFSET, \ - (uint32_t)region_top); \ - mmio_write_32(base + \ - TZC_REGION_OFFSET( \ - TZC_##macro_name##_REGION_SIZE, \ - region_no) + \ - TZC_##macro_name##_REGION_TOP_HIGH_0_OFFSET, \ - (uint32_t)(region_top >> 32)); \ - } - -#define DEFINE_TZC_COMMON_WRITE_REGION_ATTRIBUTES(fn_name, macro_name) \ - static inline void _tzc##fn_name##_write_region_attributes( \ - uintptr_t base, \ - int region_no, \ - unsigned int attr) \ - { \ - mmio_write_32(base + \ - TZC_REGION_OFFSET( \ - TZC_##macro_name##_REGION_SIZE, \ - region_no) + \ - TZC_##macro_name##_REGION_ATTR_0_OFFSET, \ - attr); \ - } - -#define DEFINE_TZC_COMMON_WRITE_REGION_ID_ACCESS(fn_name, macro_name) \ - static inline void _tzc##fn_name##_write_region_id_access( \ - uintptr_t base, \ - int region_no, \ - unsigned int val) \ - { \ - mmio_write_32(base + \ - TZC_REGION_OFFSET( \ - TZC_##macro_name##_REGION_SIZE, \ - region_no) + \ - TZC_##macro_name##_REGION_ID_ACCESS_0_OFFSET, \ - val); \ - } - -/* - * It is used to program region 0 ATTRIBUTES and ACCESS register. - */ -#define DEFINE_TZC_COMMON_CONFIGURE_REGION0(fn_name) \ - void _tzc##fn_name##_configure_region0(uintptr_t base, \ - tzc_region_attributes_t sec_attr, \ - unsigned int ns_device_access) \ - { \ - assert(base); \ - VERBOSE("TrustZone : Configuring region 0 " \ - "(TZC Interface Base=%p sec_attr=0x%x," \ - " ns_devs=0x%x)\n", (void *)base, \ - sec_attr, ns_device_access); \ - \ - /* Set secure attributes on region 0 */ \ - _tzc##fn_name##_write_region_attributes(base, 0, \ - sec_attr << TZC_REGION_ATTR_SEC_SHIFT); \ - \ - /***************************************************/ \ - /* Specify which non-secure devices have permission*/ \ - /* to access region 0. */ \ - /***************************************************/ \ - _tzc##fn_name##_write_region_id_access(base, \ - 0, \ - ns_device_access); \ - } - -/* - * It is used to program a region from 1 to 8 in the TrustZone controller. - * NOTE: - * Region 0 is special; it is preferable to use - * ##fn_name##_configure_region0 for this region (see comment for - * that function). - */ -#define DEFINE_TZC_COMMON_CONFIGURE_REGION(fn_name) \ - void _tzc##fn_name##_configure_region(uintptr_t base, \ - unsigned int filters, \ - int region_no, \ - unsigned long long region_base, \ - unsigned long long region_top, \ - tzc_region_attributes_t sec_attr, \ - unsigned int nsaid_permissions) \ - { \ - assert(base); \ - VERBOSE("TrustZone : Configuring region " \ - "(TZC Interface Base: %p, region_no = %d)" \ - "...\n", (void *)base, region_no); \ - VERBOSE("TrustZone : ... base = %llx, top = %llx," \ - "\n", region_base, region_top);\ - VERBOSE("TrustZone : ... sec_attr = 0x%x," \ - " ns_devs = 0x%x)\n", \ - sec_attr, nsaid_permissions); \ - \ - /***************************************************/ \ - /* Inputs look ok, start programming registers. */ \ - /* All the address registers are 32 bits wide and */ \ - /* have a LOW and HIGH */ \ - /* component used to construct an address up to a */ \ - /* 64bit. */ \ - /***************************************************/ \ - _tzc##fn_name##_write_region_base(base, \ - region_no, region_base); \ - _tzc##fn_name##_write_region_top(base, \ - region_no, region_top); \ - \ - /* Enable filter to the region and set secure attributes */\ - _tzc##fn_name##_write_region_attributes(base, \ - region_no, \ - (sec_attr << TZC_REGION_ATTR_SEC_SHIFT) |\ - (filters << TZC_REGION_ATTR_F_EN_SHIFT));\ - \ - /***************************************************/ \ - /* Specify which non-secure devices have permission*/ \ - /* to access this region. */ \ - /***************************************************/ \ - _tzc##fn_name##_write_region_id_access(base, \ - region_no, \ - nsaid_permissions); \ - } - -#if DEBUG -static unsigned int _tzc_read_peripheral_id(uintptr_t base) -{ - unsigned int id; - - id = mmio_read_32(base + PID0_OFF); - /* Masks DESC part in PID1 */ - id |= ((mmio_read_32(base + PID1_OFF) & 0xF) << 8); - - return id; -} - -#ifdef AARCH32 -static unsigned long long _tzc_get_max_top_addr(int addr_width) -{ - /* - * Assume at least 32 bit wide address and initialize the max. - * This function doesn't use 64-bit integer arithmetic to avoid - * having to implement additional compiler library functions. - */ - unsigned long long addr_mask = 0xFFFFFFFF; - uint32_t *addr_ptr = (uint32_t *)&addr_mask; - - assert(addr_width >= 32); - - /* This logic works only on little - endian platforms */ - assert((read_sctlr() & SCTLR_EE_BIT) == 0); - - /* - * If required address width is greater than 32, populate the higher - * 32 bits of the 64 bit field with the max address. - */ - if (addr_width > 32) - *(addr_ptr + 1) = ((1 << (addr_width - 32)) - 1); - - return addr_mask; -} -#else -#define _tzc_get_max_top_addr(addr_width)\ - (UINT64_MAX >> (64 - (addr_width))) -#endif /* AARCH32 */ - -#endif diff --git a/drivers/arm/tzc/tzc_common_private.h b/drivers/arm/tzc/tzc_common_private.h new file mode 100644 index 00000000..df10a1ee --- /dev/null +++ b/drivers/arm/tzc/tzc_common_private.h @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TZC_COMMON_PRIVATE_H__ +#define __TZC_COMMON_PRIVATE_H__ + +#include +#include +#include +#include + +#define DEFINE_TZC_COMMON_WRITE_ACTION(fn_name, macro_name) \ + static inline void _tzc##fn_name##_write_action( \ + uintptr_t base, \ + tzc_action_t action) \ + { \ + mmio_write_32(base + TZC_##macro_name##_ACTION_OFF, \ + action); \ + } + +#define DEFINE_TZC_COMMON_WRITE_REGION_BASE(fn_name, macro_name) \ + static inline void _tzc##fn_name##_write_region_base( \ + uintptr_t base, \ + int region_no, \ + unsigned long long region_base) \ + { \ + mmio_write_32(base + \ + TZC_REGION_OFFSET( \ + TZC_##macro_name##_REGION_SIZE, \ + region_no) + \ + TZC_##macro_name##_REGION_BASE_LOW_0_OFFSET, \ + (uint32_t)region_base); \ + mmio_write_32(base + \ + TZC_REGION_OFFSET( \ + TZC_##macro_name##_REGION_SIZE, \ + region_no) + \ + TZC_##macro_name##_REGION_BASE_HIGH_0_OFFSET, \ + (uint32_t)(region_base >> 32)); \ + } + +#define DEFINE_TZC_COMMON_WRITE_REGION_TOP(fn_name, macro_name) \ + static inline void _tzc##fn_name##_write_region_top( \ + uintptr_t base, \ + int region_no, \ + unsigned long long region_top) \ + { \ + mmio_write_32(base + \ + TZC_REGION_OFFSET \ + (TZC_##macro_name##_REGION_SIZE, \ + region_no) + \ + TZC_##macro_name##_REGION_TOP_LOW_0_OFFSET, \ + (uint32_t)region_top); \ + mmio_write_32(base + \ + TZC_REGION_OFFSET( \ + TZC_##macro_name##_REGION_SIZE, \ + region_no) + \ + TZC_##macro_name##_REGION_TOP_HIGH_0_OFFSET, \ + (uint32_t)(region_top >> 32)); \ + } + +#define DEFINE_TZC_COMMON_WRITE_REGION_ATTRIBUTES(fn_name, macro_name) \ + static inline void _tzc##fn_name##_write_region_attributes( \ + uintptr_t base, \ + int region_no, \ + unsigned int attr) \ + { \ + mmio_write_32(base + \ + TZC_REGION_OFFSET( \ + TZC_##macro_name##_REGION_SIZE, \ + region_no) + \ + TZC_##macro_name##_REGION_ATTR_0_OFFSET, \ + attr); \ + } + +#define DEFINE_TZC_COMMON_WRITE_REGION_ID_ACCESS(fn_name, macro_name) \ + static inline void _tzc##fn_name##_write_region_id_access( \ + uintptr_t base, \ + int region_no, \ + unsigned int val) \ + { \ + mmio_write_32(base + \ + TZC_REGION_OFFSET( \ + TZC_##macro_name##_REGION_SIZE, \ + region_no) + \ + TZC_##macro_name##_REGION_ID_ACCESS_0_OFFSET, \ + val); \ + } + +/* + * It is used to program region 0 ATTRIBUTES and ACCESS register. + */ +#define DEFINE_TZC_COMMON_CONFIGURE_REGION0(fn_name) \ + void _tzc##fn_name##_configure_region0(uintptr_t base, \ + tzc_region_attributes_t sec_attr, \ + unsigned int ns_device_access) \ + { \ + assert(base); \ + VERBOSE("TrustZone : Configuring region 0 " \ + "(TZC Interface Base=%p sec_attr=0x%x," \ + " ns_devs=0x%x)\n", (void *)base, \ + sec_attr, ns_device_access); \ + \ + /* Set secure attributes on region 0 */ \ + _tzc##fn_name##_write_region_attributes(base, 0, \ + sec_attr << TZC_REGION_ATTR_SEC_SHIFT); \ + \ + /***************************************************/ \ + /* Specify which non-secure devices have permission*/ \ + /* to access region 0. */ \ + /***************************************************/ \ + _tzc##fn_name##_write_region_id_access(base, \ + 0, \ + ns_device_access); \ + } + +/* + * It is used to program a region from 1 to 8 in the TrustZone controller. + * NOTE: + * Region 0 is special; it is preferable to use + * ##fn_name##_configure_region0 for this region (see comment for + * that function). + */ +#define DEFINE_TZC_COMMON_CONFIGURE_REGION(fn_name) \ + void _tzc##fn_name##_configure_region(uintptr_t base, \ + unsigned int filters, \ + int region_no, \ + unsigned long long region_base, \ + unsigned long long region_top, \ + tzc_region_attributes_t sec_attr, \ + unsigned int nsaid_permissions) \ + { \ + assert(base); \ + VERBOSE("TrustZone : Configuring region " \ + "(TZC Interface Base: %p, region_no = %d)" \ + "...\n", (void *)base, region_no); \ + VERBOSE("TrustZone : ... base = %llx, top = %llx," \ + "\n", region_base, region_top);\ + VERBOSE("TrustZone : ... sec_attr = 0x%x," \ + " ns_devs = 0x%x)\n", \ + sec_attr, nsaid_permissions); \ + \ + /***************************************************/ \ + /* Inputs look ok, start programming registers. */ \ + /* All the address registers are 32 bits wide and */ \ + /* have a LOW and HIGH */ \ + /* component used to construct an address up to a */ \ + /* 64bit. */ \ + /***************************************************/ \ + _tzc##fn_name##_write_region_base(base, \ + region_no, region_base); \ + _tzc##fn_name##_write_region_top(base, \ + region_no, region_top); \ + \ + /* Enable filter to the region and set secure attributes */\ + _tzc##fn_name##_write_region_attributes(base, \ + region_no, \ + (sec_attr << TZC_REGION_ATTR_SEC_SHIFT) |\ + (filters << TZC_REGION_ATTR_F_EN_SHIFT));\ + \ + /***************************************************/ \ + /* Specify which non-secure devices have permission*/ \ + /* to access this region. */ \ + /***************************************************/ \ + _tzc##fn_name##_write_region_id_access(base, \ + region_no, \ + nsaid_permissions); \ + } + +#if DEBUG +static inline unsigned int _tzc_read_peripheral_id(uintptr_t base) +{ + unsigned int id; + + id = mmio_read_32(base + PID0_OFF); + /* Masks DESC part in PID1 */ + id |= ((mmio_read_32(base + PID1_OFF) & 0xF) << 8); + + return id; +} + +#ifdef AARCH32 +static inline unsigned long long _tzc_get_max_top_addr(int addr_width) +{ + /* + * Assume at least 32 bit wide address and initialize the max. + * This function doesn't use 64-bit integer arithmetic to avoid + * having to implement additional compiler library functions. + */ + unsigned long long addr_mask = 0xFFFFFFFF; + uint32_t *addr_ptr = (uint32_t *)&addr_mask; + + assert(addr_width >= 32); + + /* This logic works only on little - endian platforms */ + assert((read_sctlr() & SCTLR_EE_BIT) == 0); + + /* + * If required address width is greater than 32, populate the higher + * 32 bits of the 64 bit field with the max address. + */ + if (addr_width > 32) + *(addr_ptr + 1) = ((1 << (addr_width - 32)) - 1); + + return addr_mask; +} +#else +#define _tzc_get_max_top_addr(addr_width)\ + (UINT64_MAX >> (64 - (addr_width))) +#endif /* AARCH32 */ + +#endif + +#endif /* __TZC_COMMON_PRIVATE_H__ */ diff --git a/drivers/arm/tzc/tzc_dmc500.c b/drivers/arm/tzc/tzc_dmc500.c index 24e587c1..93ae9202 100644 --- a/drivers/arm/tzc/tzc_dmc500.c +++ b/drivers/arm/tzc/tzc_dmc500.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ #include #include #include "tzc_common.h" -#include "tzc_common_private.c" +#include "tzc_common_private.h" /* * Macros which will be used by common core functions. -- cgit v1.2.3 From cc8b56322bb04569a5adf944774b16862782c95b Mon Sep 17 00:00:00 2001 From: Antonio Nino Diaz Date: Tue, 18 Apr 2017 15:16:05 +0100 Subject: Add `ENABLE_ASSERTIONS` build option Add the new build option `ENABLE_ASSERTIONS` that controls whether or not assert functions are compiled out. It defaults to 1 for debug builds and to 0 for release builds. Additionally, a following patch will be done to allow this build option to hide auxiliary code used for the checks done in an `assert()`. This code is is currently under the DEBUG build flag. Assert messages are now only printed if LOG_LEVEL >= LOG_LEVEL_INFO, which is the default for debug builds. This patch also updates the User Guide. Change-Id: I1401530b56bab25561bb0f274529f1d12c5263bc Signed-off-by: Antonio Nino Diaz --- Makefile | 5 ++++- common/aarch32/debug.S | 6 ++++++ common/aarch64/debug.S | 6 ++++++ docs/user-guide.md | 8 ++++++++ include/lib/stdlib/assert.h | 27 ++++++++++++--------------- lib/stdlib/assert.c | 11 +++++++---- 6 files changed, 43 insertions(+), 20 deletions(-) diff --git a/Makefile b/Makefile index 02aa50e3..d03c2bf2 100644 --- a/Makefile +++ b/Makefile @@ -52,8 +52,9 @@ include ${MAKE_HELPERS_DIRECTORY}build_env.mk include ${MAKE_HELPERS_DIRECTORY}defaults.mk -# ASM_ASSERTION enabled for DEBUG builds only +# Assertions enabled for DEBUG builds by default ASM_ASSERTION := ${DEBUG} +ENABLE_ASSERTIONS := ${DEBUG} ENABLE_PMF := ${ENABLE_RUNTIME_INSTRUMENTATION} PLAT := ${DEFAULT_PLAT} @@ -446,6 +447,7 @@ $(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS)) $(eval $(call assert_boolean,CTX_INCLUDE_FPREGS)) $(eval $(call assert_boolean,DEBUG)) $(eval $(call assert_boolean,DISABLE_PEDANTIC)) +$(eval $(call assert_boolean,ENABLE_ASSERTIONS)) $(eval $(call assert_boolean,ENABLE_PLAT_COMPAT)) $(eval $(call assert_boolean,ENABLE_PMF)) $(eval $(call assert_boolean,ENABLE_PSCI_STAT)) @@ -482,6 +484,7 @@ $(eval $(call add_define,ASM_ASSERTION)) $(eval $(call add_define,COLD_BOOT_SINGLE_CPU)) $(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS)) $(eval $(call add_define,CTX_INCLUDE_FPREGS)) +$(eval $(call add_define,ENABLE_ASSERTIONS)) $(eval $(call add_define,ENABLE_PLAT_COMPAT)) $(eval $(call add_define,ENABLE_PMF)) $(eval $(call add_define,ENABLE_PSCI_STAT)) diff --git a/common/aarch32/debug.S b/common/aarch32/debug.S index 77298a12..bafce7ce 100644 --- a/common/aarch32/debug.S +++ b/common/aarch32/debug.S @@ -107,6 +107,11 @@ assert_msg2: * --------------------------------------------------------------------------- */ func asm_assert +#if LOG_LEVEL >= LOG_LEVEL_INFO + /* + * Only print the output if LOG_LEVEL is higher or equal to + * LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1. + */ /* Stash the parameters already in r0 and r1 */ mov r5, r0 mov r6, r1 @@ -147,6 +152,7 @@ dec_print_loop: bl plat_crash_console_flush 1: +#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */ no_ret plat_panic_handler endfunc asm_assert #endif diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S index fb6924ea..3d8e0f41 100644 --- a/common/aarch64/debug.S +++ b/common/aarch64/debug.S @@ -78,6 +78,11 @@ dec_print_loop: * --------------------------------------------------------------------------- */ func asm_assert +#if LOG_LEVEL >= LOG_LEVEL_INFO + /* + * Only print the output if LOG_LEVEL is higher or equal to + * LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1. + */ mov x5, x0 mov x6, x1 /* Ensure the console is initialized */ @@ -98,6 +103,7 @@ func asm_assert asm_print_line_dec bl plat_crash_console_flush _assert_loop: +#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */ no_ret plat_panic_handler endfunc asm_assert #endif diff --git a/docs/user-guide.md b/docs/user-guide.md index a1df9652..af083605 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -286,6 +286,14 @@ performed. payload. Please refer to the "Booting an EL3 payload" section for more details. +* `ENABLE_ASSERTIONS`: This option controls whether or not calls to `assert()` + are compiled out. For debug builds, this option defaults to 1, and calls to + `assert()` are left in place. For release builds, this option defaults to 0 + and calls to `assert()` function are compiled out. This option can be set + independently of `DEBUG`. It can also be used to hide any auxiliary code + that is only required for the assertion and does not fit in the assertion + itself. + * `ENABLE_PMF`: Boolean option to enable support for optional Performance Measurement Framework(PMF). Default is 0. diff --git a/include/lib/stdlib/assert.h b/include/lib/stdlib/assert.h index 5621f8ca..1bcd1ead 100644 --- a/include/lib/stdlib/assert.h +++ b/include/lib/stdlib/assert.h @@ -34,30 +34,27 @@ * @(#)assert.h 8.2 (Berkeley) 1/21/94 * $FreeBSD$ */ - -#include - /* - * Unlike other ANSI header files, may usefully be included - * multiple times, with and without NDEBUG defined. + * Portions copyright (c) 2017, ARM Limited and Contributors. + * All rights reserved. */ -#undef assert -#undef _assert +#ifndef _ASSERT_H_ +#define _ASSERT_H_ -#ifdef NDEBUG -#define assert(e) ((void)0) -#define _assert(e) ((void)0) -#else -#define _assert(e) assert(e) +#include +#if ENABLE_ASSERTIONS +#define _assert(e) assert(e) #define assert(e) ((e) ? (void)0 : __assert(__func__, __FILE__, \ __LINE__, #e)) -#endif /* NDEBUG */ +#else +#define assert(e) ((void)0) +#define _assert(e) ((void)0) +#endif /* ENABLE_ASSERTIONS */ -#ifndef _ASSERT_H_ -#define _ASSERT_H_ __BEGIN_DECLS void __assert(const char *, const char *, int, const char *) __dead2; __END_DECLS + #endif /* !_ASSERT_H_ */ diff --git a/lib/stdlib/assert.c b/lib/stdlib/assert.c index 3486e50b..3c0bd166 100644 --- a/lib/stdlib/assert.c +++ b/lib/stdlib/assert.c @@ -32,15 +32,18 @@ #include #include -/* - * This is a basic implementation. This could be improved. - */ -void __assert (const char *function, const char *file, unsigned int line, +void __assert(const char *function, const char *file, unsigned int line, const char *assertion) { +#if LOG_LEVEL >= LOG_LEVEL_INFO + /* + * Only print the output if LOG_LEVEL is higher or equal to + * LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1. + */ tf_printf("ASSERT: %s <%d> : %s\n", function, line, assertion); console_flush(); +#endif plat_panic_handler(); } -- cgit v1.2.3 From 044bb2faabd7981af4ef419e1037fec28e5b3f8b Mon Sep 17 00:00:00 2001 From: Antonio Nino Diaz Date: Thu, 20 Apr 2017 09:58:28 +0100 Subject: Remove build option `ASM_ASSERTION` The build option `ENABLE_ASSERTIONS` should be used instead. That way both C and ASM assertions can be enabled or disabled together. All occurrences of `ASM_ASSERTION` in common code and ARM platforms have been replaced by `ENABLE_ASSERTIONS`. ASM_ASSERTION has been removed from the user guide. Change-Id: I51f1991f11b9b7ff83e787c9a3270c274748ec6f Signed-off-by: Antonio Nino Diaz --- Makefile | 7 ++++--- common/aarch32/debug.S | 4 ++-- common/aarch64/debug.S | 4 ++-- docs/user-guide.md | 5 ----- include/common/aarch32/el3_common_macros.S | 2 +- lib/aarch32/misc_helpers.S | 2 +- lib/aarch64/misc_helpers.S | 8 ++++---- lib/cpus/aarch32/aem_generic.S | 6 +++--- lib/cpus/aarch32/cortex_a32.S | 6 +++--- lib/cpus/aarch32/cpu_helpers.S | 6 +++--- lib/cpus/aarch64/cpu_helpers.S | 6 +++--- plat/common/aarch64/platform_mp_stack.S | 6 +++--- 12 files changed, 29 insertions(+), 33 deletions(-) diff --git a/Makefile b/Makefile index d03c2bf2..31460d4c 100644 --- a/Makefile +++ b/Makefile @@ -50,10 +50,13 @@ include ${MAKE_HELPERS_DIRECTORY}build_env.mk # Default values for build configurations, and their dependencies ################################################################################ +ifdef ASM_ASSERTION + $(warning ASM_ASSERTION is removed, use ENABLE_ASSERTIONS instead.) +endif + include ${MAKE_HELPERS_DIRECTORY}defaults.mk # Assertions enabled for DEBUG builds by default -ASM_ASSERTION := ${DEBUG} ENABLE_ASSERTIONS := ${DEBUG} ENABLE_PMF := ${ENABLE_RUNTIME_INSTRUMENTATION} PLAT := ${DEFAULT_PLAT} @@ -440,7 +443,6 @@ endif # Build options checks ################################################################################ -$(eval $(call assert_boolean,ASM_ASSERTION)) $(eval $(call assert_boolean,COLD_BOOT_SINGLE_CPU)) $(eval $(call assert_boolean,CREATE_KEYS)) $(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS)) @@ -480,7 +482,6 @@ $(eval $(call add_define,ARM_CCI_PRODUCT_ID)) $(eval $(call add_define,ARM_ARCH_MAJOR)) $(eval $(call add_define,ARM_ARCH_MINOR)) $(eval $(call add_define,ARM_GIC_ARCH)) -$(eval $(call add_define,ASM_ASSERTION)) $(eval $(call add_define,COLD_BOOT_SINGLE_CPU)) $(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS)) $(eval $(call add_define,CTX_INCLUDE_FPREGS)) diff --git a/common/aarch32/debug.S b/common/aarch32/debug.S index bafce7ce..adb6dc3e 100644 --- a/common/aarch32/debug.S +++ b/common/aarch32/debug.S @@ -90,7 +90,7 @@ func report_exception no_ret plat_panic_handler endfunc report_exception -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS .section .rodata.assert_str, "aS" assert_msg1: .asciz "ASSERT: File " @@ -155,7 +155,7 @@ dec_print_loop: #endif /* LOG_LEVEL >= LOG_LEVEL_INFO */ no_ret plat_panic_handler endfunc asm_assert -#endif +#endif /* ENABLE_ASSERTIONS */ /* * This function prints a string from address in r4 diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S index 3d8e0f41..cdb4ec6c 100644 --- a/common/aarch64/debug.S +++ b/common/aarch64/debug.S @@ -41,7 +41,7 @@ /* The offset to add to get ascii for numerals '0 - 9' */ #define ASCII_OFFSET_NUM 0x30 -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS .section .rodata.assert_str, "aS" assert_msg1: .asciz "ASSERT: File " @@ -106,7 +106,7 @@ _assert_loop: #endif /* LOG_LEVEL >= LOG_LEVEL_INFO */ no_ret plat_panic_handler endfunc asm_assert -#endif +#endif /* ENABLE_ASSERTIONS */ /* * This function prints a string from address in x4. diff --git a/docs/user-guide.md b/docs/user-guide.md index af083605..a69c1223 100644 --- a/docs/user-guide.md +++ b/docs/user-guide.md @@ -203,11 +203,6 @@ performed. in MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of this flag is 0. -* `ASM_ASSERTION`: This flag determines whether the assertion checks within - assembly source files are enabled or not. This option defaults to the - value of `DEBUG` - that is, by default this is only enabled for a debug - build of the firmware. - * `BL2`: This is an optional build option which specifies the path to BL2 image for the `fip` target. In this case, the BL2 in the ARM Trusted Firmware will not be built. diff --git a/include/common/aarch32/el3_common_macros.S b/include/common/aarch32/el3_common_macros.S index d7e0b3f5..91582035 100644 --- a/include/common/aarch32/el3_common_macros.S +++ b/include/common/aarch32/el3_common_macros.S @@ -148,7 +148,7 @@ _init_memory, _init_c_runtime, _exception_vectors /* Make sure we are in Secure Mode */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCR tst r0, #SCR_NS_BIT ASM_ASSERT(eq) diff --git a/lib/aarch32/misc_helpers.S b/lib/aarch32/misc_helpers.S index 5b17c21c..03b47eae 100644 --- a/lib/aarch32/misc_helpers.S +++ b/lib/aarch32/misc_helpers.S @@ -162,7 +162,7 @@ endfunc zeromem * -------------------------------------------------------------------------- */ func memcpy4 -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS orr r3, r0, r1 tst r3, #0x3 ASM_ASSERT(eq) diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S index 84265e0b..74550aa2 100644 --- a/lib/aarch64/misc_helpers.S +++ b/lib/aarch64/misc_helpers.S @@ -215,7 +215,7 @@ func zeromem_dczva tmp1 .req x4 tmp2 .req x5 -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS /* * Check for M bit (MMU enabled) of the current SCTLR_EL(1|3) * register value and panic if the MMU is disabled. @@ -228,7 +228,7 @@ func zeromem_dczva tst tmp1, #SCTLR_M_BIT ASM_ASSERT(ne) -#endif /* ASM_ASSERTION */ +#endif /* ENABLE_ASSERTIONS */ /* stop_address is the address past the last to zero */ add stop_address, cursor, length @@ -247,7 +247,7 @@ func zeromem_dczva mov tmp2, #(1 << 2) lsl block_size, tmp2, block_size -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS /* * Assumes block size is at least 16 bytes to avoid manual realignment * of the cursor at the end of the DCZVA loop. @@ -444,7 +444,7 @@ endfunc zeromem_dczva * -------------------------------------------------------------------------- */ func memcpy16 -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS orr x3, x0, x1 tst x3, #0xf ASM_ASSERT(eq) diff --git a/lib/cpus/aarch32/aem_generic.S b/lib/cpus/aarch32/aem_generic.S index 3d6064c9..7374e250 100644 --- a/lib/cpus/aarch32/aem_generic.S +++ b/lib/cpus/aarch32/aem_generic.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -35,7 +35,7 @@ func aem_generic_core_pwr_dwn /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) @@ -51,7 +51,7 @@ endfunc aem_generic_core_pwr_dwn func aem_generic_cluster_pwr_dwn /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) diff --git a/lib/cpus/aarch32/cortex_a32.S b/lib/cpus/aarch32/cortex_a32.S index f631c4cf..8cd79330 100644 --- a/lib/cpus/aarch32/cortex_a32.S +++ b/lib/cpus/aarch32/cortex_a32.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -76,7 +76,7 @@ func cortex_a32_core_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) @@ -107,7 +107,7 @@ func cortex_a32_cluster_pwr_dwn push {r12, lr} /* Assert if cache is enabled */ -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS ldcopr r0, SCTLR tst r0, #SCTLR_C_BIT ASM_ASSERT(eq) diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S index dc1b6e61..7606b8e2 100644 --- a/lib/cpus/aarch32/cpu_helpers.S +++ b/lib/cpus/aarch32/cpu_helpers.S @@ -53,7 +53,7 @@ func reset_handler /* Get the matching cpu_ops pointer (clobbers: r0 - r5) */ bl get_cpu_ops_ptr -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS cmp r0, #0 ASM_ASSERT(ne) #endif @@ -92,7 +92,7 @@ func prepare_cpu_pwr_dwn pop {r2, lr} ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR] -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS cmp r0, #0 ASM_ASSERT(ne) #endif @@ -118,7 +118,7 @@ func init_cpu_ops cmp r1, #0 bne 1f bl get_cpu_ops_ptr -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS cmp r0, #0 ASM_ASSERT(ne) #endif diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index 47cb6a2d..6a399167 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -55,7 +55,7 @@ func reset_handler /* Get the matching cpu_ops pointer */ bl get_cpu_ops_ptr -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS cmp x0, #0 ASM_ASSERT(ne) #endif @@ -94,7 +94,7 @@ func prepare_cpu_pwr_dwn mrs x1, tpidr_el3 ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS cmp x0, #0 ASM_ASSERT(ne) #endif @@ -120,7 +120,7 @@ func init_cpu_ops cbnz x0, 1f mov x10, x30 bl get_cpu_ops_ptr -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS cmp x0, #0 ASM_ASSERT(ne) #endif diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S index e3063d14..322e3bb7 100644 --- a/plat/common/aarch64/platform_mp_stack.S +++ b/plat/common/aarch64/platform_mp_stack.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -131,7 +131,7 @@ endfunc platform_set_stack * ------------------------------------------------------- */ func_deprecated platform_get_stack -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS mrs x1, mpidr_el1 cmp x0, x1 ASM_ASSERT(eq) @@ -150,7 +150,7 @@ endfunc_deprecated platform_get_stack * ----------------------------------------------------- */ func_deprecated platform_set_stack -#if ASM_ASSERTION +#if ENABLE_ASSERTIONS mrs x1, mpidr_el1 cmp x0, x1 ASM_ASSERT(eq) -- cgit v1.2.3 From aa61368eb554e9910c503f78560153805a2d6859 Mon Sep 17 00:00:00 2001 From: Antonio Nino Diaz Date: Wed, 22 Mar 2017 15:48:51 +0000 Subject: Control inclusion of helper code used for asserts Many asserts depend on code that is conditionally compiled based on the DEBUG define. This patch modifies the conditional inclusion of such code so that it is based on the ENABLE_ASSERTIONS build option. Change-Id: I6406674788aa7e1ad7c23d86ce94482ad3c382bd Signed-off-by: Antonio Nino Diaz --- bl1/bl1_main.c | 4 ++-- drivers/arm/cci/cci.c | 6 +++--- drivers/arm/ccn/ccn.c | 6 +++--- drivers/arm/tzc/tzc_common_private.h | 5 +++-- drivers/arm/tzc/tzc_dmc500.c | 4 ++-- drivers/io/io_storage.c | 9 +++++---- include/lib/el3_runtime/context_mgmt.h | 4 ++-- lib/xlat_tables/aarch32/xlat_tables.c | 6 +++--- lib/xlat_tables/aarch64/xlat_tables.c | 4 ++-- lib/xlat_tables/xlat_tables_common.c | 6 +++--- lib/xlat_tables_v2/aarch32/xlat_tables_arch.c | 4 ++-- lib/xlat_tables_v2/aarch64/xlat_tables_arch.c | 4 ++-- 12 files changed, 32 insertions(+), 30 deletions(-) diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index 89664cd0..ebeb39ea 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -114,7 +114,7 @@ void bl1_main(void) print_errata_status(); -#if DEBUG +#if ENABLE_ASSERTIONS u_register_t val; /* * Ensure that MMU/Caches and coherency are turned on @@ -141,7 +141,7 @@ void bl1_main(void) assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); else assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); -#endif +#endif /* ENABLE_ASSERTIONS */ /* Perform remaining generic architectural setup from EL3 */ bl1_arch_setup(); diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c index 2e773a98..dd39051f 100644 --- a/drivers/arm/cci/cci.c +++ b/drivers/arm/cci/cci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -39,7 +39,7 @@ static uintptr_t g_cci_base; static unsigned int g_max_master_id; static const int *g_cci_slave_if_map; -#if DEBUG +#if ENABLE_ASSERTIONS static int validate_cci_map(const int *map) { unsigned int valid_cci_map = 0; @@ -73,7 +73,7 @@ static int validate_cci_map(const int *map) return 1; } -#endif /* DEBUG */ +#endif /* ENABLE_ASSERTIONS */ void cci_init(uintptr_t cci_base, const int *map, diff --git a/drivers/arm/ccn/ccn.c b/drivers/arm/ccn/ccn.c index ca061827..16c8f607 100644 --- a/drivers/arm/ccn/ccn.c +++ b/drivers/arm/ccn/ccn.c @@ -81,7 +81,7 @@ static inline void ccn_reg_write(uintptr_t periphbase, mmio_write_64(region_base + register_offset, value); } -#if DEBUG +#if ENABLE_ASSERTIONS typedef struct rn_info { unsigned char node_desc[MAX_RN_NODES]; @@ -224,7 +224,7 @@ static void ccn_validate_plat_params(const ccn_desc_t *plat_desc) info.node_desc[node_id]--; } } -#endif /* DEBUG */ +#endif /* ENABLE_ASSERTIONS */ /******************************************************************************* * This function validates parameters passed by the platform (in a debug build) @@ -234,7 +234,7 @@ static void ccn_validate_plat_params(const ccn_desc_t *plat_desc) ******************************************************************************/ void ccn_init(const ccn_desc_t *plat_desc) { -#if DEBUG +#if ENABLE_ASSERTIONS ccn_validate_plat_params(plat_desc); #endif diff --git a/drivers/arm/tzc/tzc_common_private.h b/drivers/arm/tzc/tzc_common_private.h index df10a1ee..ee278ec9 100644 --- a/drivers/arm/tzc/tzc_common_private.h +++ b/drivers/arm/tzc/tzc_common_private.h @@ -193,7 +193,8 @@ nsaid_permissions); \ } -#if DEBUG +#if ENABLE_ASSERTIONS + static inline unsigned int _tzc_read_peripheral_id(uintptr_t base) { unsigned int id; @@ -235,6 +236,6 @@ static inline unsigned long long _tzc_get_max_top_addr(int addr_width) (UINT64_MAX >> (64 - (addr_width))) #endif /* AARCH32 */ -#endif +#endif /* ENABLE_ASSERTIONS */ #endif /* __TZC_COMMON_PRIVATE_H__ */ diff --git a/drivers/arm/tzc/tzc_dmc500.c b/drivers/arm/tzc/tzc_dmc500.c index 93ae9202..d696dfd9 100644 --- a/drivers/arm/tzc/tzc_dmc500.c +++ b/drivers/arm/tzc/tzc_dmc500.c @@ -257,7 +257,7 @@ void tzc_dmc500_set_action(tzc_action_t action) static void validate_plat_driver_data( const tzc_dmc500_driver_data_t *plat_driver_data) { -#if DEBUG +#if ENABLE_ASSERTIONS int i; unsigned int dmc_id; uintptr_t dmc_base; @@ -273,7 +273,7 @@ static void validate_plat_driver_data( dmc_id = _tzc_read_peripheral_id(dmc_base); assert(dmc_id == DMC500_PERIPHERAL_ID); } -#endif /* DEBUG */ +#endif /* ENABLE_ASSERTIONS */ } diff --git a/drivers/io/io_storage.c b/drivers/io/io_storage.c index 7cb1a6aa..de8c3bf6 100644 --- a/drivers/io/io_storage.c +++ b/drivers/io/io_storage.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -51,8 +51,8 @@ static const io_dev_info_t *devices[MAX_IO_DEVICES]; /* Number of currently registered devices */ static unsigned int dev_count; - -#if DEBUG /* Extra validation functions only used in debug builds */ +/* Extra validation functions only used when asserts are enabled */ +#if ENABLE_ASSERTIONS /* Return a boolean value indicating whether a device connector is valid */ static int is_valid_dev_connector(const io_dev_connector_t *dev_con) @@ -89,7 +89,8 @@ static int is_valid_seek_mode(io_seek_mode_t mode) return ((mode != IO_SEEK_INVALID) && (mode < IO_SEEK_MAX)); } -#endif /* End of debug-only validation functions */ +#endif /* ENABLE_ASSERTIONS */ +/* End of extra validation functions only used when asserts are enabled */ /* Open a connection to a specific device */ diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h index ca868ddb..31bf6816 100644 --- a/include/lib/el3_runtime/context_mgmt.h +++ b/include/lib/el3_runtime/context_mgmt.h @@ -87,7 +87,7 @@ void cm_set_context_by_mpidr(uint64_t mpidr, ******************************************************************************/ static inline void cm_set_next_context(void *context) { -#if DEBUG +#if ENABLE_ASSERTIONS uint64_t sp_mode; /* @@ -98,7 +98,7 @@ static inline void cm_set_next_context(void *context) : "=r" (sp_mode)); assert(sp_mode == MODE_SP_EL0); -#endif +#endif /* ENABLE_ASSERTIONS */ __asm__ volatile("msr spsel, #1\n" "mov sp, %0\n" diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c index 316a60e7..4fe5bf91 100644 --- a/lib/xlat_tables/aarch32/xlat_tables.c +++ b/lib/xlat_tables/aarch32/xlat_tables.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -85,13 +85,13 @@ static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES] __aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t)); -#if DEBUG +#if ENABLE_ASSERTIONS static unsigned long long get_max_supported_pa(void) { /* Physical address space size for long descriptor format. */ return (1ULL << 40) - 1ULL; } -#endif +#endif /* ENABLE_ASSERTIONS */ void init_xlat_tables(void) { diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c index ecb12022..4f237936 100644 --- a/lib/xlat_tables/aarch64/xlat_tables.c +++ b/lib/xlat_tables/aarch64/xlat_tables.c @@ -127,7 +127,7 @@ static unsigned long long calc_physical_addr_size_bits( return TCR_PS_BITS_4GB; } -#if DEBUG +#if ENABLE_ASSERTIONS /* Physical Address ranges supported in the AArch64 Memory Model */ static const unsigned int pa_range_bits_arr[] = { PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, @@ -144,7 +144,7 @@ static unsigned long long get_max_supported_pa(void) return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL; } -#endif +#endif /* ENABLE_ASSERTIONS */ void init_xlat_tables(void) { diff --git a/lib/xlat_tables/xlat_tables_common.c b/lib/xlat_tables/xlat_tables_common.c index 81c4dc68..4b25d0e8 100644 --- a/lib/xlat_tables/xlat_tables_common.c +++ b/lib/xlat_tables/xlat_tables_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -109,7 +109,7 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, assert((base_pa + (unsigned long long)size - 1ULL) <= (PLAT_PHY_ADDR_SPACE_SIZE - 1)); -#if DEBUG +#if ENABLE_ASSERTIONS /* Check for PAs and VAs overlaps with all other regions */ for (mm = mmap; mm->size; ++mm) { @@ -154,7 +154,7 @@ void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, mm = mmap; /* Restore pointer to the start of the array */ -#endif /* DEBUG */ +#endif /* ENABLE_ASSERTIONS */ /* Find correct place in mmap to insert new region */ while (mm->base_va < base_va && mm->size) diff --git a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c index ba0e53d6..cd7aad8f 100644 --- a/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch32/xlat_tables_arch.c @@ -37,13 +37,13 @@ #include #include "../xlat_tables_private.h" -#if DEBUG +#if ENABLE_ASSERTIONS static unsigned long long xlat_arch_get_max_supported_pa(void) { /* Physical address space size for long descriptor format. */ return (1ull << 40) - 1ull; } -#endif /* DEBUG*/ +#endif /* ENABLE_ASSERTIONS*/ int is_mmu_enabled(void) { diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c index 575ac71c..24266b2d 100644 --- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c +++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c @@ -77,7 +77,7 @@ static unsigned long long calc_physical_addr_size_bits( return TCR_PS_BITS_4GB; } -#if DEBUG +#if ENABLE_ASSERTIONS /* Physical Address ranges supported in the AArch64 Memory Model */ static const unsigned int pa_range_bits_arr[] = { PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, @@ -94,7 +94,7 @@ unsigned long long xlat_arch_get_max_supported_pa(void) return (1ull << pa_range_bits_arr[pa_range]) - 1ull; } -#endif /* DEBUG*/ +#endif /* ENABLE_ASSERTIONS*/ int is_mmu_enabled(void) { -- cgit v1.2.3