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2017-05-15Align tf_printf implementation between AArch32 and AArch64dp-arm
No need for these wrapper functions anymore. The compiler-rt builtins provide runtime support for 64-bit division and modulo operations. Change-Id: Ib785d37c86f0c82ebd34c35023a4c1822c03e7df Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-15AArch32: Add BL2U supportYatharth Kochar
Add support for firmware upgrade on AArch32. This patch has been tested on the FVP models. NOTE: Firmware upgrade on Juno AArch32 is not currently supported. Change-Id: I1ca8078214eaf86b46463edd14740120af930aec Signed-off-by: dp-arm <dimitris.papastamos@arm.com> Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>
2017-05-15AArch32: Add `TRUSTED_BOARD_BOOT` supportdp-arm
This patch adds `TRUSTED_BOARD_BOOT` support for AArch32 mode. To build this patch the "mbedtls/include/mbedtls/bignum.h" needs to be modified to remove `#define MBEDTLS_HAVE_UDBL` when `MBEDTLS_HAVE_INT32` is defined. This is a workaround for "https://github.com/ARMmbed/mbedtls/issues/708" NOTE: TBBR support on Juno AArch32 is not currently supported. Change-Id: I86d80e30b9139adc4d9663f112801ece42deafcf Signed-off-by: dp-arm <dimitris.papastamos@arm.com> Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>
2017-05-15rockchip: rk3328: Add assert check in pmu.ctony.xie
Add assert() check for cpuson_flags[] and cpuson_entry_point[]. Change-Id: I971fe54c2baa3b4514a3979042341220f5e20901 Signed-off-by: tony.xie <tony.xie@rock-chips.com>
2017-05-12Merge pull request #930 from antonio-nino-diaz-arm/an/fixes-xlat-v2davidcunado-arm
Minor fixes to the xlat tables lib v2
2017-05-12Migrate ARM platforms to use TF_MBEDTLS_KEY_ALGDavid Cunado
A previous patch superseded the MBEDTLS_KEY_ALG. This patch updates the ARM platforms to use the new TF_MBEDTLS_KEY_ALG define. Change-Id: Ie0e1bc272e127e879ac58e7cfcbe268751d7688e Signed-off-by: David Cunado <david.cunado@arm.com>
2017-05-12mbedtls: Complete namespace for TF specific macrosDavid Cunado
This patch renames MBEDTLS_KEY_ALG to TF_MBEDTLS_KEY_ALG. This completes the migration of TF specific macros so that they do not have the MBEDTLS_ suffix (see arm-trusted-firmware#874). Change-Id: Iad7632477e220b0af987c4db3cf52229fb127d00 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-05-12mbedtls: Namespace for TF specific macrosDavid Cunado
An earlier patch (arm-trusted-firmware#874) migrated MBEDTLS_ suffixed macros to have a TBBR_ suffix to avoid any potential clash with future mbedtls macros. But on reflection the TBBR_ suffix could be confusing as the macros are used to drive TF-specific configuration of mbedtls. As such this patch migrates these macros from TBBR_suffix to TF_MBEDTLS_ suffix which more accurately conveys their use. Change-Id: Ic87642b653ceeaa03d62f724976abd5e12e867d4 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-05-12AArch32: Rework SMC context save and restore mechanismSoby Mathew
The current SMC context data structure `smc_ctx_t` and related helpers are optimized for case when SMC call does not result in world switch. This was the case for SP_MIN and BL1 cold boot flow. But the firmware update usecase requires world switch as a result of SMC and the current SMC context helpers were not helping very much in this regard. Therefore this patch does the following changes to improve this: 1. Add monitor stack pointer, `spmon` to `smc_ctx_t` The C Runtime stack pointer in monitor mode, `sp_mon` is added to the SMC context, and the `smc_ctx_t` pointer is cached in `sp_mon` prior to exit from Monitor mode. This makes is easier to retrieve the context when the next SMC call happens. As a result of this change, the SMC context helpers no longer depend on the stack to save and restore the register. This aligns it with the context save and restore mechanism in AArch64. 2. Add SCR in `smc_ctx_t` Adding the SCR register to `smc_ctx_t` makes it easier to manage this register state when switching between non secure and secure world as a result of an SMC call. Change-Id: I5e12a7056107c1701b457b8f7363fdbf892230bf Signed-off-by: Soby Mathew <soby.mathew@arm.com> Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-12Hook up LLVM compiler-rt in the build systemdp-arm
This patch enables compiler-rt for the AArch32 target. The code is not used for AArch64 as the architecture supports the 64-bit division and modulo operations natively. Change-Id: I1703a92872b0bb56ac0b98c67193830683963b13 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-12Import builtins from LLVM compiler-rt projectdp-arm
These are needed to provide division and modulo operations for the AArch32 target. This code is entirely unmodified. Imported from compiler-rt master branch as of May 4 2017. Change-Id: I001e1809f2afd4bf8d4cc3d2296798809f607144 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-12Tegra: Break circular dependency in platform header filesSandrine Bailleux
For SoCs T132 and T210, the header file 'platform_def.h' used to include 'tegra_def.h' and vice versa. This patch breaks this circular dependency by making 'tegra_def.h' independent. Change-Id: I45a00a84e6ab8b93d5e9242a9ff65f03e9102a96 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2017-05-12FVP: Break circular dependency in platform header filesSandrine Bailleux
We used to have the following circular dependency in the FVP platform header files: +-> arm_def.h ---> platform_def.h ---> fvp_def.h --+ |__________________________________________________| This patch breaks it by not including 'arm_def.h' from 'fvp_def.h'. Change-Id: I280d906559e3343dd38764029e77c0ea768b4fec Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2017-05-11Merge pull request #933 from davidcunado-arm/dc/add_spdxdavidcunado-arm
Add missing SPDX header
2017-05-11Add missing SPDX headerDavid Cunado
A new file added as part of arm-trusted-firmware#927 was missing the SPDX license identifier - this patch adds the missing identifier. Change-Id: Id1355f2bdca930b7e65bb54eff7e6c764ebb0d96 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-05-11Merge pull request #928 from davidcunado-arm/dc/update_userguidedavidcunado-arm
Update AEM and Cortex Models versions
2017-05-11Merge pull request #927 from jeenu-arm/state-switchdavidcunado-arm
Execution state switch
2017-05-11Merge pull request #932 from dp-arm/dp/spdx-rockchipdavidcunado-arm
Use SPDX license identifiers for remaining files
2017-05-10Use SPDX license identifiers for remaining filesdp-arm
Change-Id: I7f54f45db65f32481cc05e1bd2c9c683b756e19a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-10Merge pull request #918 from rockchip-linux/rk3328davidcunado-arm
rockchip: rk3328: support rk3328
2017-05-10Merge pull request #931 from antonio-nino-diaz-arm/an/revert-rockchipdavidcunado-arm
Revert "rockchip: Remove unused rockchip_pd_pwr_down_wfi function"
2017-05-10Revert "rockchip: Remove unused rockchip_pd_pwr_down_wfi function"Antonio Nino Diaz
This reverts commit b6dcbf588af442fa87721dc707ff9e54d04ff504. This function wasn't used when it was removed, but it is needed to compile the new changes proposed for Rockchip platforms. Change-Id: Ia5bfe1f8398e08431f96923e2f059a83e5cb78d4 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-10rockchip: rk3328: Add a missing paragraph for copyright notice.tony.xie
Change-Id: I78c7e304d3070f66e2ca3bf838c76ee6a2ae3430 Signed-off-by: tony.xie <tony.xie@rock-chips.com>
2017-05-09Minor fixes to the xlat tables lib v2Antonio Nino Diaz
- Fix some comments. - Remove duplicated definition. - Make xlat_arch_get_max_supported_pa() private in aarch64. Change-Id: I629237209cfb2ce7b0c4bd539d63dd81d45b2edd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-08Merge pull request #926 from EvanLloyd/win_make_4davidcunado-arm
Minor makefile fixes
2017-05-08Merge pull request #922 from davidcunado-arm/dc/smc_yielding_spdsdavidcunado-arm
Migrate secure payload dispatchers to new SMC terminology
2017-05-05Update AEM and Cortex Models versionsDavid Cunado
AEMv8-A Model release v8.4 has been made available and Trusted Firmware has been tested against these versions as part of its CI system. This patch updates the user guide documentation to reflect the version of AEM and Cortex Models that Trusted Firmware has been tested against. Additionally, ARM FVPs FVP_Base_Cortex-A57x1-A53x1 and FVP_Base_Cortex-A57x2-A53x4 are removed from the list of tested FVPs as they are currently not being tested with the latest version of ARM Trusted Firmware. Also, documentation and links to Linaro pages have been updated to reflect the changes in the ARM community document hosting. Change-Id: Idae97303ce0929c82b137017de84ce94678f6f2b Signed-off-by: David Cunado <david.cunado@arm.com>
2017-05-05Merge pull request #924 from antonio-nino-diaz-arm/an/fix-xn-bitdavidcunado-arm
Fix execute-never permissions in xlat tables libs
2017-05-04Migrate secure payload dispatchers to new SMC terminologyDavid Cunado
Since Issue B (November 2016) of the SMC Calling Convention document standard SMC calls are renamed to yielding SMC calls to help avoid confusion with the standard service SMC range, which remains unchanged. http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pd A previous patch introduced a new define for yielding SMC call type. This patch updates the secure payload dispatchers (except the TSPD) to use this new define and also migrates the code to use the new terminology. Change-Id: I3d2437c04e3b21fdbd32019f55c066c87679a5bf Signed-off-by: David Cunado <david.cunado@arm.com>
2017-05-04Merge pull request #925 from dp-arm/dp/spdxdavidcunado-arm
Use SPDX license identifiers
2017-05-04Introduce ARM SiP service to switch execution stateJeenu Viswambharan
In AArch64, privileged exception levels control the execution state (a.k.a. register width) of the immediate lower Exception Level; i.e. whether the lower exception level executes in AArch64 or AArch32 state. For an exception level to have its execution state changed at run time, it must request the change by raising a synchronous exception to the higher exception level. This patch implements and adds such a provision to the ARM SiP service, by which an immediate lower exception level can request to switch its execution state. The execution state is switched if the request is: - raised from non-secure world; - raised on the primary CPU, before any secondaries are brought online with CPU_ON PSCI call; - raised from an exception level immediately below EL3: EL2, if implemented; otherwise NS EL1. If successful, the SMC doesn't return to the caller, but to the entry point supplied with the call. Otherwise, the caller will observe the SMC returning with STATE_SW_E_DENIED code. If ARM Trusted Firmware is built for AArch32, the feature is not supported, and the call will always fail. For the ARM SiP service: - Add SMC function IDs for both AArch32 and AArch64; - Increment the SiP service minor version to 2; - Adjust the number of supported SiP service calls. Add documentation for ARM SiP service. Fixes ARM-software/tf-issues#436 Change-Id: I4347f2d6232e69fbfbe333b340fcd0caed0a4cea Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-02Build: Correct Unix specific echo commandsEvan Lloyd
Some recent changes have added direct use of the echo command without parameters. This fails on a Windows shell, because echo without parameters reports the mode ("ECHO is on"). This is corrected using the ECHO_BLANK_LINE macro already provided for that purpose. Change-Id: I5fd7192861b4496f6f46b4f096e80a752cd135d6 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
2017-05-02Build: Fix parallel buildEvan Lloyd
2 problems were found, but are in one change to avoid submitting a patch that might fail to build. The problems were: 1. The macro MAKE_PREREQ_DIR has a minor bug, in that it is capable of generating recursive dependencies. 2. The inclusion of BUILD_DIR in TEMP_OBJ_DIRS left no explicit dependency, BUILD_DIR might not exist when subdirectories are created by a thread on another CPU. This fix corrects these with the following changes: 1. MAKE_PREREQ_DIR does nothing for a direct self dependency. 2. BUILD_DIR is built using MAKE_PREREQ_DIR. 3. BUILD_DIR is an explicit prerequisite of all OBJ_DIRS. Change-Id: I938cddea4a006df225c02a47b9cf759212f27fb7 Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
2017-05-02Merge pull request #919 from davidcunado-arm/dc/smc_yielding_genericdavidcunado-arm
Update terminology: standard SMC to yielding SMC
2017-05-02Add macro to check whether the CPU implements an ELJeenu Viswambharan
Replace all instances of checks with the new macro. Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-02Fix execute-never permissions in xlat tables libsAntonio Nino Diaz
Translation regimes that only support one virtual address space (such as the ones for EL2 and EL3) can flag memory regions as execute-never by setting to 1 the XN bit in the Upper Attributes field in the translation tables descriptors. Translation regimes that support two different virtual address spaces (such as the one shared by EL1 and EL0) use bits PXN and UXN instead. The Trusted Firmware runs at EL3 and EL1, it has to handle translation tables of both translation regimes, but the previous code handled both regimes the same way, as if both had only 1 VA range. When trying to set a descriptor as execute-never it would set the XN bit correctly in EL3, but it would set the XN bit in EL1 as well. XN is at the same bit position as UXN, which means that EL0 was being prevented from executing code at this region, not EL1 as the code intended. Therefore, the PXN bit was unset to 0 all the time. The result is that, in AArch64 mode, read-only data sections of BL2 weren't protected from being executed. This patch adds support of translation regimes with two virtual address spaces to both versions of the translation tables library, fixing the execute-never permissions for translation tables in EL1. The library currently does not support initializing translation tables for EL0 software, therefore it does not set/unset the UXN bit. If EL1 software needs to initialize translation tables for EL0 software, it should use a different library instead. Change-Id: If27588f9820ff42988851d90dc92801c8ecbe0c9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-02Merge pull request #923 from nmenon/fix_xlat_1davidcunado-arm
xlat lib: Don't set mmap_attr_t enum to be -1
2017-05-02xlat lib: Don't set mmap_attr_t enum to be -1Nishanth Menon
-1 is not a defined mmap_attr_t type. Instead of using invalid enum types, we can either choose to define a INVALID type OR handle the condition specifically. Since the usage of mmap_region_attr is limited, it is easier to just handle the error condition specifically and return 0 or -1 depending on success or fail. Fixes: ARM-Software/tf-issues#473 Fixes: 28fa2e9ee8f4 ("xlat lib: Use mmap_attr_t type consistently") Signed-off-by: Nishanth Menon <nm@ti.com>
2017-05-02Merge pull request #896 from sbranden/tf_issue_461davidcunado-arm
Move defines in utils.h to utils_def.h to fix shared header compile i…
2017-05-02Merge pull request #913 from vwadekar/tegra-fixes-from-downstreamdavidcunado-arm
Tegra fixes from downstream
2017-05-01Tegra210: implement 'get_target_pwr_state' handlerVarun Wadekar
This patch implements the handler to calculate the cluster and system power states for the Tegra210 SoC. The power states returned by this handler are used by the PSCI library to decide cache maintenance operations - cluster v cpu. Change-Id: I93e4139d4cd8a086b51f328e9a76e91428ebcdab Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra: fix the NS DRAM address calculation logicVarun Wadekar
This patch fixes the logic used to calculate the end of NS memory aperture. The functions allows zero sized NS apertures as that is a valid requirement for some use cases. e.g. VPR resize. Change-Id: Ie966e0ea2f9c6888d21c38e734003704094b3720 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra: memctrl_v2: zero out NS Video memory carveout regionVarun Wadekar
The video memory carveout has to be re-sized depending on the Video content. This requires the NS world to send us new base/size values. Before setting up the new region, we must zero out the previous memory region, so that the video frames are not leaked to the outside world. This patch adds the logic to zero out the previous memory carveout region. Change-Id: I471167ef7747154440df5c1a5e015fbeb69d9043 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra186: calculate proper power state for cluster/system power downVarun Wadekar
Earlier, we were setting "System Suspend" as the power state for all system states. This caused incorrect system state during a cluster power down. This patch fixes this anomaly and sets the correct power state during a cluster/system power down. Change-Id: Ibd002930e0ae103e381e0a19670c3c4d057e7cb7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra186: mce: max retries for ARI requestsSteven Kao
This patch adds max retries for all ARI requests and asserts if the ARI request is still busy. Change-Id: I454ad9b557bb59e513e4c0c6f071275c87d0e07a Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra: memmap Tegra micro-seconds timer controllerSteven Kao
This patch adds the Tegra micro-seconds controller to the memory map. This allows us to use the delay_timer functionality. Change-Id: Ia8b148a871949bfede539974cacbe0e93ec7e77c Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-05-01Tegra: early init the delay timerSteven Kao
This patch moves the platform delay timer init to early BL31 platform setup, so that platforms can use the udelay/mdelay routines in the early init code. Change-Id: I6fe20b76176ea22589539c180c5b6f9d09eda8de Signed-off-by: Steven Kao <skao@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-04-29Merge branch 'integration' into tf_issue_461Scott Branden
2017-04-29Move defines in utils.h to utils_def.h to fix shared header compile issuesScott Branden
utils.h is included in various header files for the defines in it. Some of the other header files only contain defines. This allows the header files to be shared between host and target builds for shared defines. Recently types.h has been included in utils.h as well as some function prototypes. Because of the inclusion of types.h conflicts exist building host tools abd these header files now. To solve this problem, move the defines to utils_def.h and have this included by utils.h and change header files to only include utils_def.h and not pick up the new types.h being introduced. Fixes ARM-software/tf-issues#461 Signed-off-by: Scott Branden <scott.branden@broadcom.com> Remove utils_def.h from utils.h This patch removes utils_def.h from utils.h as it is not required. And also makes a minor change to ensure Juno platform compiles. Change-Id: I10cf1fb51e44a8fa6dcec02980354eb9ecc9fa29