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2018-09-21Merge pull request #1585 from sandrine-bailleux-arm/sb/doc-fixesv1.6Soby Mathew
Minor documentation fixes
2018-09-21Merge pull request #1581 from satheesbalya-arm/sb1_update_minor_versionSoby Mathew
Update release minor version string
2018-09-21Merge pull request #1580 from joannafarley-arm/jf/release-1.6-changelogs-ReadmeSoby Mathew
Readme and Change-log updates for v1.6 release
2018-09-21Merge pull request #1578 from Yann-lms/par_addr_mask_64Soby Mathew
aarch32: PAR_ADDR_MASK should explicitly use BIT_64
2018-09-21Update release minor version stringSathees Balya
Change-Id: I67382383fc9d18ab57c7e51f793145cb14c6fec5 Signed-off-by: Sathees Balya <sathees.balya@arm.com>
2018-09-21Readme and Change-log updates for v1.6 releaseJoanna Farley
Change-Id: I7855c9d3de104975bf3249bdf291c428f001d07a Signed-off-by: Joanna Farley <joanna.farley@arm.com>
2018-09-20aarch32: PAR_ADDR_MASK should explicitly use BIT_64Yann Gautier
PAR register used here is a 64 bit register. On AARCH32 BIT macro is BIT_32. PAR_ADDR_MASK should then use BIT_64 to avoid overflow. Signed-off-by: Yann Gautier <yann.gautier@st.com>
2018-09-20User guide: Document ENABLE_SPM build flagSandrine Bailleux
Change-Id: Ib9a045200de4fcd00387b114cbbd006e46ad6a8b Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-09-20User guide: Fix link to Linux master treeSandrine Bailleux
Change-Id: Ia67a4786350c1c2ef55125cd6a318ae6d918c08e Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-09-19Merge pull request #1570 from Andre-ARM/allwinner/pmic-fixesSoby Mathew
Allwinner PMIC fixes
2018-09-19drivers: i2c: mentor: move platform code into header filesAndre Przywara
At the moment we have two I2C stub drivers (for the Allwinner and the Marvell platform), which #include the actual .c driver file. Change this into the more usual design, by renaming and moving the stub drivers into platform specific header files and including these from the actual driver file. The platform specific include directories make sure the driver picks up the right header automatically. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-09-18Merge pull request #1577 from antonio-nino-diaz-arm/an/trustyv1.6-rc1Soby Mathew
trusty: Fix return value of trusty_init()
2018-09-18Merge pull request #1576 from antonio-nino-diaz-arm/an/fix-bl32-initSoby Mathew
BL31: Fix warning about BL32 init function
2018-09-18Merge pull request #1575 from soby-mathew/sm/fix_cryptocell_memSoby Mathew
ARM platforms: Reintroduce coherent memory for BL1 and BL2
2018-09-18trusty: Fix return value of trusty_init()Antonio Nino Diaz
The value used to signal failure is 0. It is needed to return a different value on success. Change-Id: I2186aa7dfbfc825bfe7b3d5ae3c4de7af10ee44f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-18ARM platforms: Reintroduce coherent memory for BL1 and BL2Soby Mathew
The patch d323af9 removed the support for coherent memory in BL1 and BL2 for ARM platforms. But the CryptoCell SBROM integration depends on use of coherent buffers for passing data from the AP CPU to the CryptoCell. Hence this patch reintroduces support for coherent memory in BL1 and BL2 if ARM_CRYPTOCELL_INTEG=1. Change-Id: I011482dda7f7a3ec9e3e79bfb3f4fa03796f7e02 Signed-Off-by: Soby Mathew <soby.mathew@arm.com>
2018-09-18BL31: Fix warning about BL32 init functionAntonio Nino Diaz
The expected value for failure is 0, so the warning only has to be shown in that case. This is the way the TSPD has done it since it was introduced, and the way SPM and OP-TEE do it. Trusty wrongly returns 0 on success. In the case of TLK, the return value of tlkd_init() is passed from the secure world in register X1 when calling the SMC TLK_ENTRY_DONE. Change-Id: I39106d67631ee57f109619f8830bf4b9d96155e6 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-09-17allwinner: sun50i_h6: initialise I2C just before powering downAndre Przywara
Even though we initialise the platform part and the I2C controller itself at boot time, we actually only access the bus on power down. Meanwhile a rich OS might have configured the I2C pins differently or even disabled the controller. So repeat the platform setup and controller initialisation just before we actually access the bus to power off the system. This is safe, because at this point the rich OS should no longer be running. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-09-17allwinner: sun50i_h6: improve I2C setupAndre Przywara
Drop the unnecessary check for the I2C pins being already configured as I2C pins (we actually don't care). Also avoid resetting *every* peripheral that is covered by the PRCM reset controller, instead just clear the one line connected to the I2C controller. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-09-12Merge pull request #1572 from iq250vip/tf_logDimitris Papastamos
Allow setting log level back to compile time value
2018-09-11Allow setting log level back to compile time valueJunhan Zhou
When using the tf_log_set_max_level() function, one can dynamically set the log level to a value smaller than then compile time specified one, but not equal. This means that when the log level have been lowered, it can't be reset to the previous value. This commit modifies this function to allow setting the log level back to the compile time value. Fixes ARM-software/tf-issues#624 Change-Id: Ib157715c8835982ce4977ba67a48e18ff23d5a61 Signed-off-by: Junhan Zhou <Junhan@mellanox.com>
2018-09-11Merge pull request #1571 from jeenu-arm/depsDimitris Papastamos
Update dependencies for ARM TF
2018-09-11Update dependencies for ARM TFDavid Cunado
- Linaro binaries: 18.04 - mbed TLS library: 2.12.0 - FVP model versions: 11.4 build 37 This patch updates the user guide documentation to reflect these changes to the dependencies. Change-Id: I454782ca43a0db43aeeef2ab3622f4dea9dfec55 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-09-10Merge pull request #1569 from soby-mathew/sm/cov_fix_scmiv1.6-rc0Soby Mathew
CSS: Fix overrun if system power level is not available
2018-09-10Merge pull request #1568 from soby-mathew/sm/fix_ares_err_reportSoby Mathew
Fix the Cortex-ares errata reporting function name
2018-09-10Fix the Cortex-ares errata reporting function nameSoby Mathew
This patch fixes the name of the Cortex-ares errata function which was previously named `cortex_a72_errata_report` which was an error. Change-Id: Ia124df4628261021baa8d9a30308bc286d45712b Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-09-10CSS: Fix overrun if system power level is not availableSoby Mathew
This patch fixes an array overrun in CSS scmi driver if the system power domain level is less than 2. This was reported from https://scan.coverity.com/projects/arm-software-arm-trusted-firmware CID 308492 Change-Id: I3a59c700490816718d20c71141281f19b2b7e7f7 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-09-10Merge pull request #1555 from theopolis/tbb-hikey960Soby Mathew
hikey960: Add development TBB support
2018-09-10Merge pull request #1534 from Icenowy/sun50i_h6_pmicSoby Mathew
Add support for Allwinner H6 + X-Powers AXP805 PMIC combination
2018-09-09hikey960: Add development TBB supportTeddy Reed
This patch adds experimental support for TBB to the HiKey960 board. To build and test with TBB modify the uefi-tools project platforms.config +ATF_BUILDFLAGS=TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 SAVE_KEYS=1 \ MBEDTLS_DIR=./mbedtls Signed-off-by: Teddy Reed <teddy@casualhacking.io>
2018-09-09Merge pull request #1567 from jeenu-arm/ras-fixDimitris Papastamos
RAS: Fix assert condition
2018-09-07RAS: Fix assert conditionJeenu Viswambharan
Change-Id: Ia02a2dbfd4e25547776e78bed40a91f3452553d7 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-09-07Merge pull request #1566 from EvanLloyd/non_secure_uartSoby Mathew
ARM Platforms:Enable non-secure access to UART1
2018-09-07allwinner: implement system power down on H6 w/ AXP805Icenowy Zheng
The AXP805 PMIC used with H6 is capable of shutting down the system. Add support for using it to shut down the system power. The original placeholder power off code is moved to A64 code, as it's still TODO to implement PMIC operations for A64. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-09-07allwinner: sun50i_h6: add initial AXP805 PMIC codeIcenowy Zheng
The OTT reference design of Allwinner H6 SoC uses an X-Powers AXP805 PMIC. Add initial code for it. Currently it's only detected. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-09-07Merge pull request #1565 from satheesbalya-arm/sb1_2332_fwu_sds_registerDimitris Papastamos
juno: Revert FWU update detect mechanism
2018-09-07allwinner: add I2C glue driverIcenowy Zheng
Allwinner 64-bit SoCs all use the Mentor Graphics MI2CV I2C controller core, with inverted clear quirk. Add a glue driver for this. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-09-07drivers: mentor: mi2cv: add inverted interrupt clear flag quirkIcenowy Zheng
The I2C controller on Allwinner SoCs after A31 has a inverted interrupt clear flag, which needs to be written 1 (rather than 0 on Marvell SoCs and old Allwinner SoCs) to clear. Add such a quirk to mi2cv driver common code. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-09-07allwinner: call PMIC setup codeIcenowy Zheng
As the ATF may need to do some power initialization on Allwinner platform with AXP PMICs, call the PMIC setup code in BL31. Stub of PMIC setup code is added, to prevent undefined reference. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2018-09-07Merge pull request #1563 from jts-arm/mbedDimitris Papastamos
Improvements to Mbed TLS shared heap code
2018-09-07Merge pull request #1564 from jeenu-arm/sdei-suspendDimitris Papastamos
SDEI: Mask events after CPU wakeup
2018-09-07juno: Revert FWU update detect mechanismSathees Balya
The patch 7b56928 unified the FWU mechanism on FVP and Juno platforms due to issues with MCC firmware not preserving the NVFLAGS. With MCCv150 firmware, this issue is resolved. Also writing to the NOR flash while executing from the same flash in Bypass mode had some stability issues. Hence, since the MCC firmware issue is resolved, this patch reverts to the NVFLAGS mechanism to detect FWU. Also, with the introduction of SDS (Shared Data Structure) by the SCP, the reset syndrome needs to queried from the appropriate SDS field. Change-Id: If9c08f1afaaa4fcf197f3186887068103855f554 Signed-off-by: Sathees Balya <sathees.balya@arm.com> Signed-off-by: Soby Mathew <Soby.Mathew@arm.com>
2018-09-07Readjust BL2 size after sharing Mbed TLS heapJohn Tsichritzis
After introducing the Mbed TLS shared heap optimisation, reducing BL2 size by 3 pages didn't leave enough space for growth. We give 1 page back to maximum BL2 size. Change-Id: I4f05432f00b923693160f69a4e4ec310a37a2b16 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-09-07ARM Platforms:Enable non-secure access to UART1Alexei Fedorov
Adds an undocumented build option that enables non-secure access to the PL011 UART1. This allows a custom build where the UART can be used as a serial debug port for WinDbg (or other debugger) connection. This option is not documented in the user guide, as it is provided as a convenience for Windows debugging, and not intended for general use. In particular, enabling non-secure access to the UART might allow a denial of service attack! Change-Id: I4cd7d59c2cac897cc654ab5e1188ff031114ed3c Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
2018-09-07Add cache flush after BL1 writes heap info to DTBJohn Tsichritzis
A cache flush is added in BL1, in Mbed TLS shared heap code. Thus, we ensure that the heap info written to the DTB always gets written back to memory. Hence, sharing this info with other images is guaranteed. Change-Id: I0faada31fe7a83854cd5e2cf277ba519e3f050d5 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-09-07Additional runtime check for DTB presence in BL2John Tsichritzis
In Mbed TLS shared heap code, an additional sanity check is introduced in BL2. Currently, when BL2 shares heap with BL1, it expects the heap info to be found in the DTB. If for any reason the DTB is missing, BL2 cannot have the heap address and, hence, Mbed TLS cannot proceed. So, BL2 cannot continue executing and it will eventually crash. With this change we ensure that if the DTB is missing BL2 will panic() instead of having an unpredictable crash. Change-Id: I3045ae43e54b7fe53f23e7c2d4d00e3477b6a446 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-09-07Slight improvements in Mbed TLS shared heap helpersJohn Tsichritzis
This patch, firstly, makes the error messages consistent to how printed strings are usually formatted. Secondly, it removes an unnecessary #if directive. Change-Id: Idbb8ef0070562634766b683ac65f8160c9d109e6 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2018-09-07Merge pull request #1562 from antonio-nino-diaz-arm/an/bl31-warnDimitris Papastamos
Convert BL31 error message into warning
2018-09-07SDEI: Mask events after CPU wakeupJeenu Viswambharan
The specification requires that, after wakeup from a CPU suspend, the dispatcher must mask all events on the CPU. This patch adds the feature to the SDEI dispatcher by subscribing to the PSCI suspend to power down event, and masking all events on the PE. Change-Id: I9fe1d1bc2a58379ba7bba953a8d8b275fc18902c Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-09-06Convert BL31 error message into warningAntonio Nino Diaz
If BL32 isn't present or it fails to initialize the current code prints an error message in both debug and release builds. This is too verbose for release builds, so it has been converted into a warning. Also, it was missing a newline at the end of the message. Change-Id: I91e18d5d5864dbb19d47ecd54f174d2d8c06296c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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