diff options
Diffstat (limited to 'lib')
-rw-r--r-- | lib/cpus/aarch32/cortex_a53.S | 12 | ||||
-rw-r--r-- | lib/cpus/aarch32/cortex_a57.S | 22 | ||||
-rw-r--r-- | lib/cpus/aarch32/cortex_a72.S | 28 | ||||
-rw-r--r-- | lib/cpus/aarch64/cortex_a53.S | 40 | ||||
-rw-r--r-- | lib/cpus/aarch64/cortex_a57.S | 79 | ||||
-rw-r--r-- | lib/cpus/aarch64/cortex_a72.S | 34 | ||||
-rw-r--r-- | lib/cpus/errata_report.c | 2 | ||||
-rw-r--r-- | lib/psci/psci_common.c | 4 | ||||
-rw-r--r-- | lib/psci/psci_main.c | 2 | ||||
-rw-r--r-- | lib/psci/psci_off.c | 2 | ||||
-rw-r--r-- | lib/xlat_tables_v2/xlat_tables_internal.c | 14 | ||||
-rw-r--r-- | lib/xlat_tables_v2/xlat_tables_private.h | 12 |
12 files changed, 126 insertions, 125 deletions
diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S index cdc8cacb..3d5f833a 100644 --- a/lib/cpus/aarch32/cortex_a53.S +++ b/lib/cpus/aarch32/cortex_a53.S @@ -15,9 +15,9 @@ * --------------------------------------------- */ func cortex_a53_disable_smp - ldcopr16 r0, r1, CPUECTLR - bic64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A53_ECTLR + bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A53_ECTLR isb dsb sy bx lr @@ -32,9 +32,9 @@ func cortex_a53_reset_func * Enable the SMP bit. * --------------------------------------------- */ - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A53_ECTLR + orr64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A53_ECTLR isb bx lr endfunc cortex_a53_reset_func diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S index 3fc0a6d1..ed478463 100644 --- a/lib/cpus/aarch32/cortex_a57.S +++ b/lib/cpus/aarch32/cortex_a57.S @@ -16,9 +16,9 @@ * --------------------------------------------- */ func cortex_a57_disable_smp - ldcopr16 r0, r1, CPUECTLR - bic64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A57_ECTLR + bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A57_ECTLR bx lr endfunc cortex_a57_disable_smp @@ -28,11 +28,11 @@ endfunc cortex_a57_disable_smp * --------------------------------------------- */ func cortex_a57_disable_l2_prefetch - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT - bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \ - CPUECTLR_L2_DPFTCH_DIST_MASK) - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A57_ECTLR + orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT + bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \ + CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK) + stcopr16 r0, r1, CORTEX_A57_ECTLR isb dsb ish bx lr @@ -59,9 +59,9 @@ func cortex_a57_reset_func * Enable the SMP bit. * --------------------------------------------- */ - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A57_ECTLR + orr64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A57_ECTLR isb bx lr endfunc cortex_a57_reset_func diff --git a/lib/cpus/aarch32/cortex_a72.S b/lib/cpus/aarch32/cortex_a72.S index 9d39a538..cdd83adf 100644 --- a/lib/cpus/aarch32/cortex_a72.S +++ b/lib/cpus/aarch32/cortex_a72.S @@ -15,11 +15,11 @@ * --------------------------------------------- */ func cortex_a72_disable_l2_prefetch - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT - bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \ - CPUECTLR_L2_DPFTCH_DIST_MASK) - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A72_ECTLR + orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT + bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \ + CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK) + stcopr16 r0, r1, CORTEX_A72_ECTLR isb bx lr endfunc cortex_a72_disable_l2_prefetch @@ -29,9 +29,9 @@ endfunc cortex_a72_disable_l2_prefetch * --------------------------------------------- */ func cortex_a72_disable_hw_prefetcher - ldcopr16 r0, r1, CPUACTLR - orr64_imm r0, r1, CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH - stcopr16 r0, r1, CPUACTLR + ldcopr16 r0, r1, CORTEX_A72_ACTLR + orr64_imm r0, r1, CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH + stcopr16 r0, r1, CORTEX_A72_ACTLR isb dsb ish bx lr @@ -43,9 +43,9 @@ endfunc cortex_a72_disable_hw_prefetcher * --------------------------------------------- */ func cortex_a72_disable_smp - ldcopr16 r0, r1, CPUECTLR - bic64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A72_ECTLR + bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A72_ECTLR bx lr endfunc cortex_a72_disable_smp @@ -70,9 +70,9 @@ func cortex_a72_reset_func * Enable the SMP bit. * --------------------------------------------- */ - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A72_ECTLR + orr64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A72_ECTLR isb bx lr endfunc cortex_a72_reset_func diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index 77c564ae..d369c6db 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -33,9 +33,9 @@ endfunc cortex_a53_disable_dcache * --------------------------------------------- */ func cortex_a53_disable_smp - mrs x0, CPUECTLR_EL1 - bic x0, x0, #CPUECTLR_SMP_BIT - msr CPUECTLR_EL1, x0 + mrs x0, CORTEX_A53_ECTLR_EL1 + bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT + msr CORTEX_A53_ECTLR_EL1, x0 isb dsb sy ret @@ -56,10 +56,10 @@ func errata_a53_826319_wa mov x17, x30 bl check_errata_826319 cbz x0, 1f - mrs x1, L2ACTLR_EL1 - bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN - orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH - msr L2ACTLR_EL1, x1 + mrs x1, CORTEX_A53_L2ACTLR_EL1 + bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN + orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH + msr CORTEX_A53_L2ACTLR_EL1, x1 1: ret x17 endfunc errata_a53_826319_wa @@ -93,9 +93,9 @@ func a53_disable_non_temporal_hint mov x17, x30 bl check_errata_disable_non_temporal_hint cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_DTAH - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A53_ACTLR_EL1 + orr x1, x1, #CORTEX_A53_ACTLR_DTAH + msr CORTEX_A53_ACTLR_EL1, x1 1: ret x17 endfunc a53_disable_non_temporal_hint @@ -126,9 +126,9 @@ func errata_a53_855873_wa bl check_errata_855873 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_ENDCCASCI - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A53_ACTLR_EL1 + orr x1, x1, #CORTEX_A53_ACTLR_ENDCCASCI + msr CORTEX_A53_ACTLR_EL1, x1 1: ret x17 endfunc errata_a53_855873_wa @@ -168,9 +168,9 @@ func cortex_a53_reset_func * Enable the SMP bit. * --------------------------------------------- */ - mrs x0, CPUECTLR_EL1 - orr x0, x0, #CPUECTLR_SMP_BIT - msr CPUECTLR_EL1, x0 + mrs x0, CORTEX_A53_ECTLR_EL1 + orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT + msr CORTEX_A53_ECTLR_EL1, x0 isb ret x19 endfunc cortex_a53_reset_func @@ -275,10 +275,10 @@ cortex_a53_regs: /* The ascii list of register names to be reported */ func cortex_a53_cpu_reg_dump adr x6, cortex_a53_regs - mrs x8, CPUECTLR_EL1 - mrs x9, CPUMERRSR_EL1 - mrs x10, L2MERRSR_EL1 - mrs x11, CPUACTLR_EL1 + mrs x8, CORTEX_A53_ECTLR_EL1 + mrs x9, CORTEX_A53_MERRSR_EL1 + mrs x10, CORTEX_A53_L2MERRSR_EL1 + mrs x11, CORTEX_A53_ACTLR_EL1 ret endfunc cortex_a53_cpu_reg_dump diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index ffaf44e5..9e8480a3 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -29,12 +29,12 @@ endfunc cortex_a57_disable_dcache * --------------------------------------------- */ func cortex_a57_disable_l2_prefetch - mrs x0, CPUECTLR_EL1 - orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT - mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK - orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK + mrs x0, CORTEX_A57_ECTLR_EL1 + orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT + mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK + orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK bic x0, x0, x1 - msr CPUECTLR_EL1, x0 + msr CORTEX_A57_ECTLR_EL1, x0 isb dsb ish ret @@ -45,9 +45,9 @@ endfunc cortex_a57_disable_l2_prefetch * --------------------------------------------- */ func cortex_a57_disable_smp - mrs x0, CPUECTLR_EL1 - bic x0, x0, #CPUECTLR_SMP_BIT - msr CPUECTLR_EL1, x0 + mrs x0, CORTEX_A57_ECTLR_EL1 + bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT + msr CORTEX_A57_ECTLR_EL1, x0 ret endfunc cortex_a57_disable_smp @@ -78,9 +78,9 @@ func errata_a57_806969_wa mov x17, x30 bl check_errata_806969 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_806969_wa @@ -120,9 +120,9 @@ func errata_a57_813420_wa mov x17, x30 bl check_errata_813420 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_DCC_AS_DCCI - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_DCC_AS_DCCI + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_813420_wa @@ -150,9 +150,9 @@ func a57_disable_ldnp_overread mov x17, x30 bl check_errata_disable_ldnp_overread cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_DIS_OVERREAD - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_DIS_OVERREAD + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc a57_disable_ldnp_overread @@ -177,9 +177,9 @@ func errata_a57_826974_wa mov x17, x30 bl check_errata_826974 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_826974_wa @@ -204,9 +204,9 @@ func errata_a57_826977_wa mov x17, x30 bl check_errata_826977 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_826977_wa @@ -231,15 +231,16 @@ func errata_a57_828024_wa mov x17, x30 bl check_errata_828024 cbz x0, 1f - mrs x1, CPUACTLR_EL1 + mrs x1, CORTEX_A57_ACTLR_EL1 /* * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 * instructions here because the resulting bitmask doesn't fit in a * 16-bit value so it cannot be encoded in a single instruction. */ - orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA - orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING) - msr CPUACTLR_EL1, x1 + orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA + orr x1, x1, #(CORTEX_A57_ACTLR_DIS_L1_STREAMING | \ + CORTEX_A57_ACTLR_DIS_STREAMING) + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_828024_wa @@ -264,9 +265,9 @@ func errata_a57_829520_wa mov x17, x30 bl check_errata_829520 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_829520_wa @@ -291,9 +292,9 @@ func errata_a57_833471_wa mov x17, x30 bl check_errata_833471 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_833471_wa @@ -357,9 +358,9 @@ func cortex_a57_reset_func * Enable the SMP bit. * --------------------------------------------- */ - mrs x0, CPUECTLR_EL1 - orr x0, x0, #CPUECTLR_SMP_BIT - msr CPUECTLR_EL1, x0 + mrs x0, CORTEX_A57_ECTLR_EL1 + orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT + msr CORTEX_A57_ECTLR_EL1, x0 isb ret x19 endfunc cortex_a57_reset_func @@ -503,9 +504,9 @@ cortex_a57_regs: /* The ascii list of register names to be reported */ func cortex_a57_cpu_reg_dump adr x6, cortex_a57_regs - mrs x8, CPUECTLR_EL1 - mrs x9, CPUMERRSR_EL1 - mrs x10, L2MERRSR_EL1 + mrs x8, CORTEX_A57_ECTLR_EL1 + mrs x9, CORTEX_A57_MERRSR_EL1 + mrs x10, CORTEX_A57_L2MERRSR_EL1 ret endfunc cortex_a57_cpu_reg_dump diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S index acd2d965..0307627c 100644 --- a/lib/cpus/aarch64/cortex_a72.S +++ b/lib/cpus/aarch64/cortex_a72.S @@ -27,12 +27,12 @@ endfunc cortex_a72_disable_dcache * --------------------------------------------- */ func cortex_a72_disable_l2_prefetch - mrs x0, CPUECTLR_EL1 - orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT - mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK - orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK + mrs x0, CORTEX_A72_ECTLR_EL1 + orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT + mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK + orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK bic x0, x0, x1 - msr CPUECTLR_EL1, x0 + msr CORTEX_A72_ECTLR_EL1, x0 isb ret endfunc cortex_a72_disable_l2_prefetch @@ -42,9 +42,9 @@ endfunc cortex_a72_disable_l2_prefetch * --------------------------------------------- */ func cortex_a72_disable_hw_prefetcher - mrs x0, CPUACTLR_EL1 - orr x0, x0, #CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH - msr CPUACTLR_EL1, x0 + mrs x0, CORTEX_A72_ACTLR_EL1 + orr x0, x0, #CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH + msr CORTEX_A72_ACTLR_EL1, x0 isb dsb ish ret @@ -55,9 +55,9 @@ endfunc cortex_a72_disable_hw_prefetcher * --------------------------------------------- */ func cortex_a72_disable_smp - mrs x0, CPUECTLR_EL1 - bic x0, x0, #CPUECTLR_SMP_BIT - msr CPUECTLR_EL1, x0 + mrs x0, CORTEX_A72_ECTLR_EL1 + bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT + msr CORTEX_A72_ECTLR_EL1, x0 ret endfunc cortex_a72_disable_smp @@ -82,9 +82,9 @@ func cortex_a72_reset_func * As a bare minimum enable the SMP bit. * --------------------------------------------- */ - mrs x0, CPUECTLR_EL1 - orr x0, x0, #CPUECTLR_SMP_BIT - msr CPUECTLR_EL1, x0 + mrs x0, CORTEX_A72_ECTLR_EL1 + orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT + msr CORTEX_A72_ECTLR_EL1, x0 isb ret endfunc cortex_a72_reset_func @@ -211,9 +211,9 @@ cortex_a72_regs: /* The ascii list of register names to be reported */ func cortex_a72_cpu_reg_dump adr x6, cortex_a72_regs - mrs x8, CPUECTLR_EL1 - mrs x9, CPUMERRSR_EL1 - mrs x10, L2MERRSR_EL1 + mrs x8, CORTEX_A72_ECTLR_EL1 + mrs x9, CORTEX_A72_MERRSR_EL1 + mrs x10, CORTEX_A72_L2MERRSR_EL1 ret endfunc cortex_a72_cpu_reg_dump diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c index 4d9757e0..1e1fc786 100644 --- a/lib/cpus/errata_report.c +++ b/lib/cpus/errata_report.c @@ -60,7 +60,7 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported) * Applied: INFO * Not applied: VERBOSE */ -void errata_print_msg(int status, const char *cpu, const char *id) +void errata_print_msg(unsigned int status, const char *cpu, const char *id) { /* Errata status strings */ static const char *const errata_status_str[] = { diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 763de046..f31b3238 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -332,7 +332,7 @@ void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, unsigned int node_index[]) { unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node; - int i; + unsigned int i; for (i = PSCI_CPU_PWR_LVL + 1; i <= end_lvl; i++) { *node_index++ = parent_node; @@ -901,7 +901,7 @@ void psci_print_power_domain_map(void) *****************************************************************************/ int psci_secondaries_brought_up(void) { - int idx, n_valid = 0; + unsigned int idx, n_valid = 0; for (idx = 0; idx < ARRAY_SIZE(psci_cpu_pd_nodes); idx++) { if (psci_cpu_pd_nodes[idx].mpidr != PSCI_INVALID_MPIDR) diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c index 2a6644b6..257479aa 100644 --- a/lib/psci/psci_main.c +++ b/lib/psci/psci_main.c @@ -209,7 +209,7 @@ int psci_cpu_off(void) int psci_affinity_info(u_register_t target_affinity, unsigned int lowest_affinity_level) { - unsigned int target_idx; + int target_idx; /* We dont support level higher than PSCI_CPU_PWR_LVL */ if (lowest_affinity_level > PSCI_CPU_PWR_LVL) diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c index 8be44c31..e7fb6532 100644 --- a/lib/psci/psci_off.c +++ b/lib/psci/psci_off.c @@ -19,7 +19,7 @@ ******************************************************************************/ static void psci_set_power_off_state(psci_power_state_t *state_info) { - int lvl; + unsigned int lvl; for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) state_info->pwr_domain_state[lvl] = PLAT_MAX_OFF_STATE; diff --git a/lib/xlat_tables_v2/xlat_tables_internal.c b/lib/xlat_tables_v2/xlat_tables_internal.c index 2d556e65..e1a252be 100644 --- a/lib/xlat_tables_v2/xlat_tables_internal.c +++ b/lib/xlat_tables_v2/xlat_tables_internal.c @@ -37,7 +37,7 @@ */ static int xlat_table_get_index(xlat_ctx_t *ctx, const uint64_t *table) { - for (int i = 0; i < ctx->tables_num; i++) + for (unsigned int i = 0; i < ctx->tables_num; i++) if (ctx->tables[i] == table) return i; @@ -53,7 +53,7 @@ static int xlat_table_get_index(xlat_ctx_t *ctx, const uint64_t *table) /* Returns a pointer to an empty translation table. */ static uint64_t *xlat_table_get_empty(xlat_ctx_t *ctx) { - for (int i = 0; i < ctx->tables_num; i++) + for (unsigned int i = 0; i < ctx->tables_num; i++) if (ctx->tables_mapped_regions[i] == 0) return ctx->tables[i]; @@ -203,7 +203,7 @@ static void xlat_tables_unmap_region(xlat_ctx_t *ctx, mmap_region_t *mm, const uintptr_t table_base_va, uint64_t *const table_base, const int table_entries, - const int level) + const unsigned int level) { assert(level >= ctx->base_level && level <= XLAT_TABLE_LEVEL_MAX); @@ -468,7 +468,7 @@ static uintptr_t xlat_tables_map_region(xlat_ctx_t *ctx, mmap_region_t *mm, const uintptr_t table_base_va, uint64_t *const table_base, const int table_entries, - const int level) + const unsigned int level) { assert(level >= ctx->base_level && level <= XLAT_TABLE_LEVEL_MAX); @@ -1053,14 +1053,14 @@ void init_xlation_table(xlat_ctx_t *ctx) /* All tables must be zeroed before mapping any region. */ - for (int i = 0; i < ctx->base_table_entries; i++) + for (unsigned int i = 0; i < ctx->base_table_entries; i++) ctx->base_table[i] = INVALID_DESC; - for (int j = 0; j < ctx->tables_num; j++) { + for (unsigned int j = 0; j < ctx->tables_num; j++) { #if PLAT_XLAT_TABLES_DYNAMIC ctx->tables_mapped_regions[j] = 0; #endif - for (int i = 0; i < XLAT_TABLE_ENTRIES; i++) + for (unsigned int i = 0; i < XLAT_TABLE_ENTRIES; i++) ctx->tables[j][i] = INVALID_DESC; } diff --git a/lib/xlat_tables_v2/xlat_tables_private.h b/lib/xlat_tables_v2/xlat_tables_private.h index 7b3e555e..83e0b6ea 100644 --- a/lib/xlat_tables_v2/xlat_tables_private.h +++ b/lib/xlat_tables_v2/xlat_tables_private.h @@ -52,7 +52,7 @@ typedef struct { * null entry. */ mmap_region_t *mmap; - int mmap_num; + unsigned int mmap_num; /* * Array of finer-grain translation tables. @@ -60,7 +60,7 @@ typedef struct { * contain both level-2 and level-3 entries. */ uint64_t (*tables)[XLAT_TABLE_ENTRIES]; - int tables_num; + unsigned int tables_num; /* * Keep track of how many regions are mapped in each table. The base * table can't be unmapped so it isn't needed to keep track of it. @@ -69,14 +69,14 @@ typedef struct { int *tables_mapped_regions; #endif /* PLAT_XLAT_TABLES_DYNAMIC */ - int next_table; + unsigned int next_table; /* * Base translation table. It doesn't need to have the same amount of * entries as the ones used for other levels. */ uint64_t *base_table; - int base_table_entries; + unsigned int base_table_entries; /* * Max Physical and Virtual addresses currently in use by the @@ -87,10 +87,10 @@ typedef struct { uintptr_t max_va; /* Level of the base translation table. */ - int base_level; + unsigned int base_level; /* Set to 1 when the translation tables are initialized. */ - int initialized; + unsigned int initialized; /* * Bit mask that has to be ORed to the rest of a translation table |