diff options
Diffstat (limited to 'include/lib/cpus/aarch32')
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a53.h | 34 | ||||
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a57.h | 56 | ||||
| -rw-r--r-- | include/lib/cpus/aarch32/cortex_a72.h | 34 |
3 files changed, 62 insertions, 62 deletions
diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h index 7f4c88ae..265cb158 100644 --- a/include/lib/cpus/aarch32/cortex_a53.h +++ b/include/lib/cpus/aarch32/cortex_a53.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,47 +22,47 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CPUECTLR p15, 1, c15 /* Instruction def. */ +#define CORTEX_A53_ECTLR p15, 1, c15 -#define CPUECTLR_SMP_BIT (1 << 6) +#define CORTEX_A53_ECTLR_SMP_BIT (1 << 6) -#define CPUECTLR_CPU_RET_CTRL_SHIFT 0 -#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT 0 +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) -#define CPUECTLR_FPU_RET_CTRL_SHIFT 3 -#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT 3 +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CPUMERRSR p15, 2, c15 /* Instruction def. */ +#define CORTEX_A53_MERRSR p15, 2, c15 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CPUACTLR p15, 0, c15 /* Instruction def. */ +#define CORTEX_A53_ACTLR p15, 0, c15 -#define CPUACTLR_DTAH (1 << 24) +#define CORTEX_A53_ACTLR_DTAH (1 << 24) /******************************************************************************* * L2 Auxiliary Control register specific definitions. ******************************************************************************/ -#define L2ACTLR p15, 1, c15, c0, 0 /* Instruction def. */ +#define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0 -#define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) -#define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) +#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) +#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) /******************************************************************************* * L2 Extended Control register specific definitions. ******************************************************************************/ -#define L2ECTLR p15, 1, c9, c0, 3 /* Instruction def. */ +#define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3 -#define L2ECTLR_RET_CTRL_SHIFT 0 -#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT 0 +#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define L2MERRSR p15, 3, c15 /* Instruction def. */ +#define CORTEX_A53_L2MERRSR p15, 3, c15 #endif /* __CORTEX_A53_H__ */ diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index 94e5c8a4..1c3fa25c 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h @@ -22,58 +22,58 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CPUECTLR p15, 1, c15 /* Instruction def. */ +#define CORTEX_A57_ECTLR p15, 1, c15 -#define CPUECTLR_SMP_BIT (1 << 6) -#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A57_ECTLR_SMP_BIT (1 << 6) +#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) +#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) +#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) -#define CPUECTLR_CPU_RET_CTRL_SHIFT 0 -#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0 +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CPUMERRSR p15, 2, c15 /* Instruction def. */ +#define CORTEX_A57_CPUMERRSR p15, 2, c15 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CPUACTLR p15, 0, c15 /* Instruction def. */ - -#define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59) -#define CPUACTLR_GRE_NGRE_AS_NGNRE (1 << 54) -#define CPUACTLR_DIS_OVERREAD (1 << 52) -#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) -#define CPUACTLR_DCC_AS_DCCI (1 << 44) -#define CPUACTLR_FORCE_FPSCR_FLUSH (1 << 38) -#define CPUACTLR_DIS_STREAMING (3 << 27) -#define CPUACTLR_DIS_L1_STREAMING (3 << 25) -#define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) +#define CORTEX_A57_ACTLR p15, 0, c15 + +#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (1 << 59) +#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (1 << 54) +#define CORTEX_A57_ACTLR_DIS_OVERREAD (1 << 52) +#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (1 << 49) +#define CORTEX_A57_ACTLR_DCC_AS_DCCI (1 << 44) +#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (1 << 38) +#define CORTEX_A57_ACTLR_DIS_STREAMING (3 << 27) +#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (3 << 25) +#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define L2CTLR p15, 1, c9, c0, 3 /* Instruction def. */ +#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 3 -#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 -#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 /******************************************************************************* * L2 Extended Control register specific definitions. ******************************************************************************/ -#define L2ECTLR p15, 1, c9, c0, 3 /* Instruction def. */ +#define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3 -#define L2ECTLR_RET_CTRL_SHIFT 0 -#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0 +#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (0x7 << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define L2MERRSR p15, 3, c15 /* Instruction def. */ +#define CORTEX_A57_L2MERRSR p15, 3, c15 #endif /* __CORTEX_A57_H__ */ diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index e734b571..a550192c 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h @@ -13,42 +13,42 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CPUECTLR p15, 1, c15 /* Instruction def. */ +#define CORTEX_A72_ECTLR p15, 1, c15 -#define CPUECTLR_SMP_BIT (1 << 6) -#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6) +#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) +#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) +#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CPUMERRSR p15, 2, c15 /* Instruction def. */ +#define CORTEX_A72_MERRSR p15, 2, c15 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CPUACTLR p15, 0, c15 /* Instruction def. */ +#define CORTEX_A72_ACTLR p15, 0, c15 -#define CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) -#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) -#define CPUACTLR_DCC_AS_DCCI (1 << 44) +#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) +#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49) +#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define L2CTLR p15, 1, c9, c0, 3 /* Instruction def. */ +#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 3 -#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 -#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define L2_TAG_RAM_LATENCY_2_CYCLES 0x1 -#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define L2MERRSR p15, 3, c15 /* Instruction def. */ +#define CORTEX_A72_L2MERRSR p15, 3, c15 #endif /* __CORTEX_A72_H__ */ |