diff options
| author | davidcunado-arm <david.cunado@arm.com> | 2017-06-16 12:06:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-06-16 12:06:24 +0100 |
| commit | 6de8b24f52cf2bd74adefbaa86dd2a0676c3eaa2 (patch) | |
| tree | f7b88c25ab174e201cdc67a35fcb205b94f04363 /plat/nvidia/tegra/include/platform_def.h | |
| parent | 0dc3c353054896722b7cbfbd04a4d845619485e7 (diff) | |
| parent | ab712fd86b4790f171f355508895de198330cfb9 (diff) | |
Merge pull request #953 from vwadekar/tegra-misra-fixes-v1
Tegra misra fixes v1
Diffstat (limited to 'plat/nvidia/tegra/include/platform_def.h')
| -rw-r--r-- | plat/nvidia/tegra/include/platform_def.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index 41d771c0..4894442a 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -10,6 +10,7 @@ #include <arch.h> #include <common_def.h> #include <tegra_def.h> +#include <utils_def.h> /******************************************************************************* * Generic platform constants @@ -17,10 +18,10 @@ /* Size of cacheable stacks */ #ifdef IMAGE_BL31 -#define PLATFORM_STACK_SIZE 0x400 +#define PLATFORM_STACK_SIZE U(0x400) #endif -#define TEGRA_PRIMARY_CPU 0x0 +#define TEGRA_PRIMARY_CPU U(0x0) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ @@ -31,20 +32,20 @@ /******************************************************************************* * Platform console related constants ******************************************************************************/ -#define TEGRA_CONSOLE_BAUDRATE 115200 -#define TEGRA_BOOT_UART_CLK_IN_HZ 408000000 +#define TEGRA_CONSOLE_BAUDRATE U(115200) +#define TEGRA_BOOT_UART_CLK_IN_HZ U(408000000) /******************************************************************************* * Platform memory map related constants ******************************************************************************/ /* Size of trusted dram */ -#define TZDRAM_SIZE 0x00400000 +#define TZDRAM_SIZE U(0x00400000) #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) /******************************************************************************* * BL31 specific defines. ******************************************************************************/ -#define BL31_SIZE 0x40000 +#define BL31_SIZE U(0x40000) #define BL31_BASE TZDRAM_BASE #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) @@ -53,8 +54,8 @@ /******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 35) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 35) +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) /******************************************************************************* * Some data must be aligned on the biggest cache line size in the platform. @@ -62,6 +63,6 @@ * integrated and external caches. ******************************************************************************/ #define CACHE_WRITEBACK_SHIFT 6 -#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) #endif /* __PLATFORM_DEF_H__ */ |