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| author | davidcunado-arm <david.cunado@arm.com> | 2017-06-16 12:06:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-06-16 12:06:24 +0100 |
| commit | 6de8b24f52cf2bd74adefbaa86dd2a0676c3eaa2 (patch) | |
| tree | f7b88c25ab174e201cdc67a35fcb205b94f04363 /plat/nvidia/tegra/common/aarch64/tegra_helpers.S | |
| parent | 0dc3c353054896722b7cbfbd04a4d845619485e7 (diff) | |
| parent | ab712fd86b4790f171f355508895de198330cfb9 (diff) | |
Merge pull request #953 from vwadekar/tegra-misra-fixes-v1
Tegra misra fixes v1
Diffstat (limited to 'plat/nvidia/tegra/common/aarch64/tegra_helpers.S')
| -rw-r--r-- | plat/nvidia/tegra/common/aarch64/tegra_helpers.S | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index 1a4236fd..22389f27 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -68,18 +68,18 @@ * Enable processor retention * --------------------------- */ - mrs x0, L2ECTLR_EL1 - mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT - bic x0, x0, #L2ECTLR_RET_CTRL_MASK + mrs x0, CORTEX_A57_L2ECTLR_EL1 + mov x1, #RETENTION_ENTRY_TICKS_512 + bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK orr x0, x0, x1 - msr L2ECTLR_EL1, x0 + msr CORTEX_A57_L2ECTLR_EL1, x0 isb - mrs x0, CPUECTLR_EL1 - mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT - bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK + mrs x0, CORTEX_A57_ECTLR_EL1 + mov x1, #RETENTION_ENTRY_TICKS_512 + bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK orr x0, x0, x1 - msr CPUECTLR_EL1, x0 + msr CORTEX_A57_ECTLR_EL1, x0 isb /* ------------------------------------------------------- @@ -98,11 +98,11 @@ adr x0, tegra_enable_l2_ecc_parity_prot ldr x0, [x0] cbz x0, 1f - mrs x0, L2CTLR_EL1 - and x1, x0, #L2_ECC_PARITY_PROTECTION_BIT + mrs x0, CORTEX_A57_L2CTLR_EL1 + and x1, x0, #CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT cbnz x1, 1f - orr x0, x0, #L2_ECC_PARITY_PROTECTION_BIT - msr L2CTLR_EL1, x0 + orr x0, x0, #CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT + msr CORTEX_A57_L2CTLR_EL1, x0 isb /* -------------------------------- @@ -317,18 +317,18 @@ func tegra_secure_entrypoint * entries from the branch predictor array. * ------------------------------------------------------- */ - mrs x0, CPUACTLR_EL1 + mrs x0, CORTEX_A57_ACTLR_EL1 orr x0, x0, #1 - msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ + msr CORTEX_A57_ACTLR_EL1, x0 /* invalidate BTB and I$ together */ dsb sy isb ic iallu /* actual invalidate */ dsb sy isb - mrs x0, CPUACTLR_EL1 + mrs x0, CORTEX_A57_ACTLR_EL1 bic x0, x0, #1 - msr CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ + msr CORTEX_A57_ACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ dsb sy isb @@ -352,7 +352,7 @@ func tegra_secure_entrypoint msr oslar_el1, x0 /* os lock stays 0 across warm reset */ mov x3, #3 movz x4, #0x8000, lsl #48 - msr CPUACTLR_EL1, x4 /* turn off RCG */ + msr CORTEX_A57_ACTLR_EL1, x4 /* turn off RCG */ isb msr rmr_el3, x3 /* request warm reset */ isb |