diff options
| author | Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> | 2017-10-03 11:15:54 +0200 |
|---|---|---|
| committer | Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> | 2017-10-03 11:16:35 +0200 |
| commit | d71e6d83612df896774ec4c03d49500312d2c324 (patch) | |
| tree | 2bf49e837dce0f80993dc912d08bcd0c4ffb416c | |
| parent | 28c7b2134a43c3ed8eea83eda1aefcd4bfdf34ca (diff) | |
puma: fix gpio reset pin muxing and polarity
This change is Puma RK3399-Q7 specific. Do not merge upstream.
On the Puma RK3399-Q7, the Linux kernel muxes the overtemp output to the reset
pin. Restore GPIO functionality.
Additionally, the Puma RK3399-Q7 needs a polarity of 1 instead of the
default 0. This currently cannot be set through the FDT, so hardcode it
here for now.
| -rw-r--r-- | plat/rockchip/rk3399/drivers/pmu/pmu.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index 9c0a29c1..84558d19 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -1210,6 +1210,13 @@ void __dead2 rockchip_soc_soft_reset(void) rst_gpio = plat_get_rockchip_gpio_reset(); if (rst_gpio) { + // On the Puma RK3399-Q7, the Linux kernel muxes the overtemp output to the reset + // pin. Restore GPIO functionality. + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX, GPIO1A6_IOMUX); + // Additionally, the Puma RK3399-Q7 needs a polarity of 1 instead of the + // default 0. This currently cannot be set through the FDT, so fix it here. + rst_gpio->polarity = 1; + gpio_set_direction(rst_gpio->index, GPIO_DIR_OUT); gpio_set_value(rst_gpio->index, rst_gpio->polarity); } else { |