diff options
| author | davidcunado-arm <david.cunado@arm.com> | 2017-06-16 12:06:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-06-16 12:06:24 +0100 |
| commit | 6de8b24f52cf2bd74adefbaa86dd2a0676c3eaa2 (patch) | |
| tree | f7b88c25ab174e201cdc67a35fcb205b94f04363 | |
| parent | 0dc3c353054896722b7cbfbd04a4d845619485e7 (diff) | |
| parent | ab712fd86b4790f171f355508895de198330cfb9 (diff) | |
Merge pull request #953 from vwadekar/tegra-misra-fixes-v1
Tegra misra fixes v1
61 files changed, 2025 insertions, 1985 deletions
diff --git a/common/runtime_svc.c b/common/runtime_svc.c index 7b38847b..0ea4cd09 100644 --- a/common/runtime_svc.c +++ b/common/runtime_svc.c @@ -36,15 +36,16 @@ uintptr_t handle_runtime_svc(uint32_t smc_fid, unsigned int flags) { u_register_t x1, x2, x3, x4; - int index, idx; + int index; + unsigned int idx; const rt_svc_desc_t *rt_svc_descs; assert(handle); idx = get_unique_oen_from_smc_fid(smc_fid); - assert(idx >= 0 && idx < MAX_RT_SVCS); + assert(idx < MAX_RT_SVCS); index = rt_svc_descs_indices[idx]; - if (index < 0 || index >= RT_SVC_DECS_NUM) + if (index < 0 || index >= (int)RT_SVC_DECS_NUM) SMC_RET1(handle, SMC_UNK); rt_svc_descs = (rt_svc_desc_t *) RT_SVC_DESCS_START; @@ -89,7 +90,8 @@ static int32_t validate_rt_svc_desc(const rt_svc_desc_t *desc) ******************************************************************************/ void runtime_svc_init(void) { - int rc = 0, index, start_idx, end_idx; + int rc = 0; + unsigned int index, start_idx, end_idx; /* Assert the number of descriptors detected are less than maximum indices */ assert((RT_SVC_DESCS_END >= RT_SVC_DESCS_START) && diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h index e0bf2db0..9a6a7faa 100644 --- a/include/bl31/interrupt_mgmt.h +++ b/include/bl31/interrupt_mgmt.h @@ -12,16 +12,16 @@ /******************************************************************************* * Constants for the types of interrupts recognised by the IM framework ******************************************************************************/ -#define INTR_TYPE_S_EL1 0 -#define INTR_TYPE_EL3 1 -#define INTR_TYPE_NS 2 -#define MAX_INTR_TYPES 3 +#define INTR_TYPE_S_EL1 U(0) +#define INTR_TYPE_EL3 U(1) +#define INTR_TYPE_NS U(2) +#define MAX_INTR_TYPES U(3) #define INTR_TYPE_INVAL MAX_INTR_TYPES /* * Constant passed to the interrupt handler in the 'id' field when the * framework does not read the gic registers to determine the interrupt id. */ -#define INTR_ID_UNAVAILABLE 0xFFFFFFFF +#define INTR_ID_UNAVAILABLE U(0xFFFFFFFF) /******************************************************************************* @@ -29,37 +29,37 @@ * constants to define the valid routing models for each supported interrupt * type ******************************************************************************/ -#define INTR_RM_FLAGS_SHIFT 0x0 -#define INTR_RM_FLAGS_MASK 0x3 +#define INTR_RM_FLAGS_SHIFT U(0x0) +#define INTR_RM_FLAGS_MASK U(0x3) /* Routed to EL3 from NS. Taken to S-EL1 from Secure */ -#define INTR_SEL1_VALID_RM0 0x2 +#define INTR_SEL1_VALID_RM0 U(0x2) /* Routed to EL3 from NS and Secure */ -#define INTR_SEL1_VALID_RM1 0x3 +#define INTR_SEL1_VALID_RM1 U(0x3) /* Routed to EL1/EL2 from NS and to S-EL1 from Secure */ -#define INTR_NS_VALID_RM0 0x0 +#define INTR_NS_VALID_RM0 U(0x0) /* Routed to EL1/EL2 from NS and to EL3 from Secure */ -#define INTR_NS_VALID_RM1 0x1 +#define INTR_NS_VALID_RM1 U(0x1) /* Routed to EL3 from NS. Taken to S-EL1 from Secure and handed over to EL3 */ -#define INTR_EL3_VALID_RM0 0x2 +#define INTR_EL3_VALID_RM0 U(0x2) /* Routed to EL3 from NS and Secure */ -#define INTR_EL3_VALID_RM1 0x3 +#define INTR_EL3_VALID_RM1 U(0x3) /* This is the default routing model */ -#define INTR_DEFAULT_RM 0x0 +#define INTR_DEFAULT_RM U(0x0) /******************************************************************************* * Constants for the _individual_ routing model bits in the 'flags' field for * each interrupt type and mask to validate the 'flags' parameter while * registering an interrupt handler ******************************************************************************/ -#define INTR_TYPE_FLAGS_MASK 0xFFFFFFFC +#define INTR_TYPE_FLAGS_MASK U(0xFFFFFFFC) #define INTR_RM_FROM_SEC_SHIFT SECURE /* BIT[0] */ #define INTR_RM_FROM_NS_SHIFT NON_SECURE /* BIT[1] */ -#define INTR_RM_FROM_FLAG_MASK 1 +#define INTR_RM_FROM_FLAG_MASK U(1) #define get_interrupt_rm_flag(flag, ss) (((flag >> INTR_RM_FLAGS_SHIFT) >> ss) \ & INTR_RM_FROM_FLAG_MASK) -#define set_interrupt_rm_flag(flag, ss) (flag |= 1 << ss) -#define clr_interrupt_rm_flag(flag, ss) (flag &= ~(1 << ss)) +#define set_interrupt_rm_flag(flag, ss) (flag |= U(1) << ss) +#define clr_interrupt_rm_flag(flag, ss) (flag &= ~(U(1) << ss)) /******************************************************************************* @@ -84,10 +84,10 @@ * the flag to indicate the security state when the exception was generated is * supported. ******************************************************************************/ -#define INTR_SRC_SS_FLAG_SHIFT 0 /* BIT[0] */ -#define INTR_SRC_SS_FLAG_MASK 1 +#define INTR_SRC_SS_FLAG_SHIFT U(0) /* BIT[0] */ +#define INTR_SRC_SS_FLAG_MASK U(1) #define set_interrupt_src_ss(flag, val) (flag |= val << INTR_SRC_SS_FLAG_SHIFT) -#define clr_interrupt_src_ss(flag) (flag &= ~(1 << INTR_SRC_SS_FLAG_SHIFT)) +#define clr_interrupt_src_ss(flag) (flag &= ~(U(1) << INTR_SRC_SS_FLAG_SHIFT)) #define get_interrupt_src_ss(flag) ((flag >> INTR_SRC_SS_FLAG_SHIFT) & \ INTR_SRC_SS_FLAG_MASK) diff --git a/include/common/ep_info.h b/include/common/ep_info.h index 7f545232..23d27c4b 100644 --- a/include/common/ep_info.h +++ b/include/common/ep_info.h @@ -8,49 +8,50 @@ #define __EP_INFO_H__ #include <param_header.h> +#include <utils_def.h> -#define SECURE 0x0 -#define NON_SECURE 0x1 +#define SECURE U(0x0) +#define NON_SECURE U(0x1) #define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE)) /******************************************************************************* * Constants that allow assembler code to access members of and the * 'entry_point_info' structure at their correct offsets. ******************************************************************************/ -#define ENTRY_POINT_INFO_PC_OFFSET 0x08 +#define ENTRY_POINT_INFO_PC_OFFSET U(0x08) #ifdef AARCH32 -#define ENTRY_POINT_INFO_ARGS_OFFSET 0x10 +#define ENTRY_POINT_INFO_ARGS_OFFSET U(0x10) #else -#define ENTRY_POINT_INFO_ARGS_OFFSET 0x18 +#define ENTRY_POINT_INFO_ARGS_OFFSET U(0x18) #endif /* The following are used to set/get image attributes. */ -#define PARAM_EP_SECURITY_MASK (0x1) +#define PARAM_EP_SECURITY_MASK U(0x1) #define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK) #define SET_SECURITY_STATE(x, security) \ ((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security)) -#define EP_EE_MASK 0x2 -#define EP_EE_LITTLE 0x0 -#define EP_EE_BIG 0x2 +#define EP_EE_MASK U(0x2) +#define EP_EE_LITTLE U(0x0) +#define EP_EE_BIG U(0x2) #define EP_GET_EE(x) (x & EP_EE_MASK) #define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) -#define EP_ST_MASK 0x4 -#define EP_ST_DISABLE 0x0 -#define EP_ST_ENABLE 0x4 +#define EP_ST_MASK U(0x4) +#define EP_ST_DISABLE U(0x0) +#define EP_ST_ENABLE U(0x4) #define EP_GET_ST(x) (x & EP_ST_MASK) #define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) -#define EP_EXE_MASK 0x8 -#define NON_EXECUTABLE 0x0 -#define EXECUTABLE 0x8 +#define EP_EXE_MASK U(0x8) +#define NON_EXECUTABLE U(0x0) +#define EXECUTABLE U(0x8) #define EP_GET_EXE(x) (x & EP_EXE_MASK) #define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) -#define EP_FIRST_EXE_MASK 0x10 -#define EP_FIRST_EXE 0x10 +#define EP_FIRST_EXE_MASK U(0x10) +#define EP_FIRST_EXE U(0x10) #define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK) #define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee)) diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h index 7959bb78..3a3d7aaa 100644 --- a/include/drivers/arm/gic_v2.h +++ b/include/drivers/arm/gic_v2.h @@ -15,115 +15,115 @@ #error " The legacy ARM GIC driver is deprecated." #endif -#define GIC400_NUM_SPIS 480 -#define MAX_PPIS 14 -#define MAX_SGIS 16 - -#define MIN_SGI_ID 0 -#define MIN_PPI_ID 16 -#define MIN_SPI_ID 32 - -#define GRP0 0 -#define GRP1 1 -#define GIC_PRI_MASK 0xff -#define GIC_HIGHEST_SEC_PRIORITY 0 -#define GIC_LOWEST_SEC_PRIORITY 127 -#define GIC_HIGHEST_NS_PRIORITY 128 -#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ -#define GIC_SPURIOUS_INTERRUPT 1023 -#define GIC_TARGET_CPU_MASK 0xff - -#define ENABLE_GRP0 (1 << 0) -#define ENABLE_GRP1 (1 << 1) +#define GIC400_NUM_SPIS U(480) +#define MAX_PPIS U(14) +#define MAX_SGIS U(16) + +#define MIN_SGI_ID U(0) +#define MIN_PPI_ID U(16) +#define MIN_SPI_ID U(32) + +#define GRP0 U(0) +#define GRP1 U(1) +#define GIC_PRI_MASK U(0xff) +#define GIC_HIGHEST_SEC_PRIORITY U(0) +#define GIC_LOWEST_SEC_PRIORITY U(127) +#define GIC_HIGHEST_NS_PRIORITY U(128) +#define GIC_LOWEST_NS_PRIORITY U(254) /* 255 would disable an interrupt */ +#define GIC_SPURIOUS_INTERRUPT U(1023) +#define GIC_TARGET_CPU_MASK U(0xff) + +#define ENABLE_GRP0 (U(1) << 0) +#define ENABLE_GRP1 (U(1) << 1) /* Distributor interface definitions */ -#define GICD_CTLR 0x0 -#define GICD_TYPER 0x4 -#define GICD_IGROUPR 0x80 -#define GICD_ISENABLER 0x100 -#define GICD_ICENABLER 0x180 -#define GICD_ISPENDR 0x200 -#define GICD_ICPENDR 0x280 -#define GICD_ISACTIVER 0x300 -#define GICD_ICACTIVER 0x380 -#define GICD_IPRIORITYR 0x400 -#define GICD_ITARGETSR 0x800 -#define GICD_ICFGR 0xC00 -#define GICD_SGIR 0xF00 -#define GICD_CPENDSGIR 0xF10 -#define GICD_SPENDSGIR 0xF20 - -#define IGROUPR_SHIFT 5 -#define ISENABLER_SHIFT 5 +#define GICD_CTLR U(0x0) +#define GICD_TYPER U(0x4) +#define GICD_IGROUPR U(0x80) +#define GICD_ISENABLER U(0x100) +#define GICD_ICENABLER U(0x180) +#define GICD_ISPENDR U(0x200) +#define GICD_ICPENDR U(0x280) +#define GICD_ISACTIVER U(0x300) +#define GICD_ICACTIVER U(0x380) +#define GICD_IPRIORITYR U(0x400) +#define GICD_ITARGETSR U(0x800) +#define GICD_ICFGR U(0xC00) +#define GICD_SGIR U(0xF00) +#define GICD_CPENDSGIR U(0xF10) +#define GICD_SPENDSGIR U(0xF20) + +#define IGROUPR_SHIFT U(5) +#define ISENABLER_SHIFT U(5) #define ICENABLER_SHIFT ISENABLER_SHIFT -#define ISPENDR_SHIFT 5 +#define ISPENDR_SHIFT U(5) #define ICPENDR_SHIFT ISPENDR_SHIFT -#define ISACTIVER_SHIFT 5 +#define ISACTIVER_SHIFT U(5) #define ICACTIVER_SHIFT ISACTIVER_SHIFT -#define IPRIORITYR_SHIFT 2 -#define ITARGETSR_SHIFT 2 -#define ICFGR_SHIFT 4 -#define CPENDSGIR_SHIFT 2 +#define IPRIORITYR_SHIFT U(2) +#define ITARGETSR_SHIFT U(2) +#define ICFGR_SHIFT U(4) +#define CPENDSGIR_SHIFT U(2) #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT /* GICD_TYPER bit definitions */ -#define IT_LINES_NO_MASK 0x1f +#define IT_LINES_NO_MASK U(0x1f) /* Physical CPU Interface registers */ -#define GICC_CTLR 0x0 -#define GICC_PMR 0x4 -#define GICC_BPR 0x8 -#define GICC_IAR 0xC -#define GICC_EOIR 0x10 -#define GICC_RPR 0x14 -#define GICC_HPPIR 0x18 -#define GICC_AHPPIR 0x28 -#define GICC_IIDR 0xFC -#define GICC_DIR 0x1000 +#define GICC_CTLR U(0x0) +#define GICC_PMR U(0x4) +#define GICC_BPR U(0x8) +#define GICC_IAR U(0xC) +#define GICC_EOIR U(0x10) +#define GICC_RPR U(0x14) +#define GICC_HPPIR U(0x18) +#define GICC_AHPPIR U(0x28) +#define GICC_IIDR U(0xFC) +#define GICC_DIR U(0x1000) #define GICC_PRIODROP GICC_EOIR /* Common CPU Interface definitions */ -#define INT_ID_MASK 0x3ff +#define INT_ID_MASK U(0x3ff) /* GICC_CTLR bit definitions */ -#define EOI_MODE_NS (1 << 10) -#define EOI_MODE_S (1 << 9) -#define IRQ_BYP_DIS_GRP1 (1 << 8) -#define FIQ_BYP_DIS_GRP1 (1 << 7) -#define IRQ_BYP_DIS_GRP0 (1 << 6) -#define FIQ_BYP_DIS_GRP0 (1 << 5) -#define CBPR (1 << 4) -#define FIQ_EN (1 << 3) -#define ACK_CTL (1 << 2) +#define EOI_MODE_NS (U(1) << 10) +#define EOI_MODE_S (U(1) << 9) +#define IRQ_BYP_DIS_GRP1 (U(1) << 8) +#define FIQ_BYP_DIS_GRP1 (U(1) << 7) +#define IRQ_BYP_DIS_GRP0 (U(1) << 6) +#define FIQ_BYP_DIS_GRP0 (U(1) << 5) +#define CBPR (U(1) << 4) +#define FIQ_EN (U(1) << 3) +#define ACK_CTL (U(1) << 2) /* GICC_IIDR bit masks and shifts */ -#define GICC_IIDR_PID_SHIFT 20 -#define GICC_IIDR_ARCH_SHIFT 16 -#define GICC_IIDR_REV_SHIFT 12 -#define GICC_IIDR_IMP_SHIFT 0 +#define GICC_IIDR_PID_SHIFT U(20) +#define GICC_IIDR_ARCH_SHIFT U(16) +#define GICC_IIDR_REV_SHIFT U(12) +#define GICC_IIDR_IMP_SHIFT U(0) -#define GICC_IIDR_PID_MASK 0xfff -#define GICC_IIDR_ARCH_MASK 0xf -#define GICC_IIDR_REV_MASK 0xf -#define GICC_IIDR_IMP_MASK 0xfff +#define GICC_IIDR_PID_MASK U(0xfff) +#define GICC_IIDR_ARCH_MASK U(0xf) +#define GICC_IIDR_REV_MASK U(0xf) +#define GICC_IIDR_IMP_MASK U(0xfff) /* HYP view virtual CPU Interface registers */ -#define GICH_CTL 0x0 -#define GICH_VTR 0x4 -#define GICH_ELRSR0 0x30 -#define GICH_ELRSR1 0x34 -#define GICH_APR0 0xF0 -#define GICH_LR_BASE 0x100 +#define GICH_CTL U(0x0) +#define GICH_VTR U(0x4) +#define GICH_ELRSR0 U(0x30) +#define GICH_ELRSR1 U(0x34) +#define GICH_APR0 U(0xF0) +#define GICH_LR_BASE U(0x100) /* Virtual CPU Interface registers */ -#define GICV_CTL 0x0 -#define GICV_PRIMASK 0x4 -#define GICV_BP 0x8 -#define GICV_INTACK 0xC -#define GICV_EOI 0x10 -#define GICV_RUNNINGPRI 0x14 -#define GICV_HIGHESTPEND 0x18 -#define GICV_DEACTIVATE 0x1000 +#define GICV_CTL U(0x0) +#define GICV_PRIMASK U(0x4) +#define GICV_BP U(0x8) +#define GICV_INTACK U(0xC) +#define GICV_EOI U(0x10) +#define GICV_RUNNINGPRI U(0x14) +#define GICV_HIGHESTPEND U(0x18) +#define GICV_DEACTIVATE U(0x1000) #ifndef __ASSEMBLY__ diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 16adcf76..e84c888c 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -12,35 +12,35 @@ /******************************************************************************* * MIDR bit definitions ******************************************************************************/ -#define MIDR_IMPL_MASK 0xff -#define MIDR_IMPL_SHIFT 0x18 -#define MIDR_VAR_SHIFT 20 -#define MIDR_VAR_BITS 4 -#define MIDR_VAR_MASK 0xf -#define MIDR_REV_SHIFT 0 -#define MIDR_REV_BITS 4 -#define MIDR_REV_MASK 0xf -#define MIDR_PN_MASK 0xfff -#define MIDR_PN_SHIFT 0x4 +#define MIDR_IMPL_MASK U(0xff) +#define MIDR_IMPL_SHIFT U(0x18) +#define MIDR_VAR_SHIFT U(20) +#define MIDR_VAR_BITS U(4) +#define MIDR_VAR_MASK U(0xf) +#define MIDR_REV_SHIFT U(0) +#define MIDR_REV_BITS U(4) +#define MIDR_REV_MASK U(0xf) +#define MIDR_PN_MASK U(0xfff) +#define MIDR_PN_SHIFT U(0x4) /******************************************************************************* * MPIDR macros ******************************************************************************/ -#define MPIDR_MT_MASK (1 << 24) +#define MPIDR_MT_MASK (U(1) << 24) #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK -#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS -#define MPIDR_AFFINITY_BITS 8 -#define MPIDR_AFFLVL_MASK 0xff -#define MPIDR_AFF0_SHIFT 0 -#define MPIDR_AFF1_SHIFT 8 -#define MPIDR_AFF2_SHIFT 16 -#define MPIDR_AFF3_SHIFT 32 -#define MPIDR_AFFINITY_MASK 0xff00ffffff -#define MPIDR_AFFLVL_SHIFT 3 -#define MPIDR_AFFLVL0 0 -#define MPIDR_AFFLVL1 1 -#define MPIDR_AFFLVL2 2 -#define MPIDR_AFFLVL3 3 +#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) +#define MPIDR_AFFINITY_BITS U(8) +#define MPIDR_AFFLVL_MASK U(0xff) +#define MPIDR_AFF0_SHIFT U(0) +#define MPIDR_AFF1_SHIFT U(8) +#define MPIDR_AFF2_SHIFT U(16) +#define MPIDR_AFF3_SHIFT U(32) +#define MPIDR_AFFINITY_MASK U(0xff00ffffff) +#define MPIDR_AFFLVL_SHIFT U(3) +#define MPIDR_AFFLVL0 U(0) +#define MPIDR_AFFLVL1 U(1) +#define MPIDR_AFFLVL2 U(2) +#define MPIDR_AFFLVL3 U(3) #define MPIDR_AFFLVL0_VAL(mpidr) \ ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) #define MPIDR_AFFLVL1_VAL(mpidr) \ @@ -54,10 +54,10 @@ * add one while using this macro to define array sizes. * TODO: Support only the first 3 affinity levels for now. */ -#define MPIDR_MAX_AFFLVL 2 +#define MPIDR_MAX_AFFLVL U(2) /* Constant to highlight the assumption that MPIDR allocation starts from 0 */ -#define FIRST_MPIDR 0 +#define FIRST_MPIDR U(0) /******************************************************************************* * Definitions for CPU system register interface to GICv3 @@ -80,164 +80,164 @@ /******************************************************************************* * Generic timer memory mapped registers & offsets ******************************************************************************/ -#define CNTCR_OFF 0x000 -#define CNTFID_OFF 0x020 +#define CNTCR_OFF U(0x000) +#define CNTFID_OFF U(0x020) -#define CNTCR_EN (1 << 0) -#define CNTCR_HDBG (1 << 1) +#define CNTCR_EN (U(1) << 0) +#define CNTCR_HDBG (U(1) << 1) #define CNTCR_FCREQ(x) ((x) << 8) /******************************************************************************* * System register bit definitions ******************************************************************************/ /* CLIDR definitions */ -#define LOUIS_SHIFT 21 -#define LOC_SHIFT 24 -#define CLIDR_FIELD_WIDTH 3 +#define LOUIS_SHIFT U(21) +#define LOC_SHIFT U(24) +#define CLIDR_FIELD_WIDTH U(3) /* CSSELR definitions */ -#define LEVEL_SHIFT 1 +#define LEVEL_SHIFT U(1) /* D$ set/way op type defines */ -#define DCISW 0x0 -#define DCCISW 0x1 -#define DCCSW 0x2 +#define DCISW U(0x0) +#define DCCISW U(0x1) +#define DCCSW U(0x2) /* ID_AA64PFR0_EL1 definitions */ -#define ID_AA64PFR0_EL0_SHIFT 0 -#define ID_AA64PFR0_EL1_SHIFT 4 -#define ID_AA64PFR0_EL2_SHIFT 8 -#define ID_AA64PFR0_EL3_SHIFT 12 -#define ID_AA64PFR0_ELX_MASK 0xf +#define ID_AA64PFR0_EL0_SHIFT U(0) +#define ID_AA64PFR0_EL1_SHIFT U(4) +#define ID_AA64PFR0_EL2_SHIFT U(8) +#define ID_AA64PFR0_EL3_SHIFT U(12) +#define ID_AA64PFR0_ELX_MASK U(0xf) -#define EL_IMPL_NONE 0 -#define EL_IMPL_A64ONLY 1 -#define EL_IMPL_A64_A32 2 +#define EL_IMPL_NONE U(0) +#define EL_IMPL_A64ONLY U(1) +#define EL_IMPL_A64_A32 U(2) -#define ID_AA64PFR0_GIC_SHIFT 24 -#define ID_AA64PFR0_GIC_WIDTH 4 -#define ID_AA64PFR0_GIC_MASK ((1 << ID_AA64PFR0_GIC_WIDTH) - 1) +#define ID_AA64PFR0_GIC_SHIFT U(24) +#define ID_AA64PFR0_GIC_WIDTH U(4) +#define ID_AA64PFR0_GIC_MASK ((U(1) << ID_AA64PFR0_GIC_WIDTH) - 1) /* ID_AA64MMFR0_EL1 definitions */ -#define ID_AA64MMFR0_EL1_PARANGE_MASK 0xf +#define ID_AA64MMFR0_EL1_PARANGE_MASK U(0xf) -#define PARANGE_0000 32 -#define PARANGE_0001 36 -#define PARANGE_0010 40 -#define PARANGE_0011 42 -#define PARANGE_0100 44 -#define PARANGE_0101 48 +#define PARANGE_0000 U(32) +#define PARANGE_0001 U(36) +#define PARANGE_0010 U(40) +#define PARANGE_0011 U(42) +#define PARANGE_0100 U(44) +#define PARANGE_0101 U(48) /* ID_PFR1_EL1 definitions */ -#define ID_PFR1_VIRTEXT_SHIFT 12 -#define ID_PFR1_VIRTEXT_MASK 0xf +#define ID_PFR1_VIRTEXT_SHIFT U(12) +#define ID_PFR1_VIRTEXT_MASK U(0xf) #define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \ & ID_PFR1_VIRTEXT_MASK) /* SCTLR definitions */ -#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ - (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \ - (1 << 4)) +#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ + (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ + (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) -#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ - (1 << 20) | (1 << 11)) +#define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ + (U(1) << 22) | (U(1) << 20) | (U(1) << 11)) #define SCTLR_AARCH32_EL1_RES1 \ - ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \ - (1 << 3)) - -#define SCTLR_M_BIT (1 << 0) -#define SCTLR_A_BIT (1 << 1) -#define SCTLR_C_BIT (1 << 2) -#define SCTLR_SA_BIT (1 << 3) -#define SCTLR_CP15BEN_BIT (1 << 5) -#define SCTLR_I_BIT (1 << 12) -#define SCTLR_NTWI_BIT (1 << 16) -#define SCTLR_NTWE_BIT (1 << 18) -#define SCTLR_WXN_BIT (1 << 19) -#define SCTLR_EE_BIT (1 << 25) + ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ + (U(1) << 4) | (U(1) << 3)) + +#define SCTLR_M_BIT (U(1) << 0) +#define SCTLR_A_BIT (U(1) << 1) +#define SCTLR_C_BIT (U(1) << 2) +#define SCTLR_SA_BIT (U(1) << 3) +#define SCTLR_CP15BEN_BIT (U(1) << 5) +#define SCTLR_I_BIT (U(1) << 12) +#define SCTLR_NTWI_BIT (U(1) << 16) +#define SCTLR_NTWE_BIT (U(1) << 18) +#define SCTLR_WXN_BIT (U(1) << 19) +#define SCTLR_EE_BIT (U(1) << 25) /* CPACR_El1 definitions */ -#define CPACR_EL1_FPEN(x) (x << 20) -#define CPACR_EL1_FP_TRAP_EL0 0x1 -#define CPACR_EL1_FP_TRAP_ALL 0x2 -#define CPACR_EL1_FP_TRAP_NONE 0x3 +#define CPACR_EL1_FPEN(x) ((x) << 20) +#define CPACR_EL1_FP_TRAP_EL0 U(0x1) +#define CPACR_EL1_FP_TRAP_ALL U(0x2) +#define CPACR_EL1_FP_TRAP_NONE U(0x3) /* SCR definitions */ -#define SCR_RES1_BITS ((1 << 4) | (1 << 5)) -#define SCR_TWE_BIT (1 << 13) -#define SCR_TWI_BIT (1 << 12) -#define SCR_ST_BIT (1 << 11) -#define SCR_RW_BIT (1 << 10) -#define SCR_SIF_BIT (1 << 9) -#define SCR_HCE_BIT (1 << 8) -#define SCR_SMD_BIT (1 << 7) -#define SCR_EA_BIT (1 << 3) -#define SCR_FIQ_BIT (1 << 2) -#define SCR_IRQ_BIT (1 << 1) -#define SCR_NS_BIT (1 << 0) -#define SCR_VALID_BIT_MASK 0x2f8f +#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) +#define SCR_TWE_BIT (U(1) << 13) +#define SCR_TWI_BIT (U(1) << 12) +#define SCR_ST_BIT (U(1) << 11) +#define SCR_RW_BIT (U(1) << 10) +#define SCR_SIF_BIT (U(1) << 9) +#define SCR_HCE_BIT (U(1) << 8) +#define SCR_SMD_BIT (U(1) << 7) +#define SCR_EA_BIT (U(1) << 3) +#define SCR_FIQ_BIT (U(1) << 2) +#define SCR_IRQ_BIT (U(1) << 1) +#define SCR_NS_BIT (U(1) << 0) +#define SCR_VALID_BIT_MASK U(0x2f8f) /* MDCR definitions */ #define MDCR_SPD32(x) ((x) << 14) -#define MDCR_SPD32_LEGACY 0x0 -#define MDCR_SPD32_DISABLE 0x2 -#define MDCR_SPD32_ENABLE 0x3 -#define MDCR_SDD_BIT (1 << 16) +#define MDCR_SPD32_LEGACY U(0x0) +#define MDCR_SPD32_DISABLE U(0x2) +#define MDCR_SPD32_ENABLE U(0x3) +#define MDCR_SDD_BIT (U(1) << 16) #define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) /* HCR definitions */ -#define HCR_RW_SHIFT 31 -#define HCR_RW_BIT (1ull << HCR_RW_SHIFT) -#define HCR_AMO_BIT (1 << 5) -#define HCR_IMO_BIT (1 << 4) -#define HCR_FMO_BIT (1 << 3) +#define HCR_RW_SHIFT U(31) +#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) +#define HCR_AMO_BIT (U(1) << 5) +#define HCR_IMO_BIT (U(1) << 4) +#define HCR_FMO_BIT (U(1) << 3) /* ISR definitions */ -#define ISR_A_SHIFT 8 -#define ISR_I_SHIFT 7 -#define ISR_F_SHIFT 6 +#define ISR_A_SHIFT U(8) +#define ISR_I_SHIFT U(7) +#define ISR_F_SHIFT U(6) /* CNTHCTL_EL2 definitions */ -#define EVNTEN_BIT (1 << 2) -#define EL1PCEN_BIT (1 << 1) -#define EL1PCTEN_BIT (1 << 0) +#define EVNTEN_BIT (U(1) << 2) +#define EL1PCEN_BIT (U(1) << 1) +#define EL1PCTEN_BIT (U(1) << 0) /* CNTKCTL_EL1 definitions */ -#define EL0PTEN_BIT (1 << 9) -#define EL0VTEN_BIT (1 << 8) -#define EL0PCTEN_BIT (1 << 0) -#define EL0VCTEN_BIT (1 << 1) -#define EVNTEN_BIT (1 << 2) -#define EVNTDIR_BIT (1 << 3) -#define EVNTI_SHIFT 4 -#define EVNTI_MASK 0xf +#define EL0PTEN_BIT (U(1) << 9) +#define EL0VTEN_BIT (U(1) << 8) +#define EL0PCTEN_BIT (U(1) << 0) +#define EL0VCTEN_BIT (U(1) << 1) +#define EVNTEN_BIT (U(1) << 2) +#define EVNTDIR_BIT (U(1) << 3) +#define EVNTI_SHIFT U(4) +#define EVNTI_MASK U(0xf) /* CPTR_EL3 definitions */ -#define TCPAC_BIT (1 << 31) -#define TTA_BIT (1 << 20) -#define TFP_BIT (1 << 10) +#define TCPAC_BIT (U(1) << 31) +#define TTA_BIT (U(1) << 20) +#define TFP_BIT (U(1) << 10) /* CPSR/SPSR definitions */ -#define DAIF_FIQ_BIT (1 << 0) -#define DAIF_IRQ_BIT (1 << 1) -#define DAIF_ABT_BIT (1 << 2) -#define DAIF_DBG_BIT (1 << 3) -#define SPSR_DAIF_SHIFT 6 -#define SPSR_DAIF_MASK 0xf - -#define SPSR_AIF_SHIFT 6 -#define SPSR_AIF_MASK 0x7 - -#define SPSR_E_SHIFT 9 -#define SPSR_E_MASK 0x1 -#define SPSR_E_LITTLE 0x0 -#define SPSR_E_BIG 0x1 - -#define SPSR_T_SHIFT 5 -#define SPSR_T_MASK 0x1 -#define SPSR_T_ARM 0x0 -#define SPSR_T_THUMB 0x1 +#define DAIF_FIQ_BIT (U(1) << 0) +#define DAIF_IRQ_BIT (U(1) << 1) +#define DAIF_ABT_BIT (U(1) << 2) +#define DAIF_DBG_BIT (U(1) << 3) +#define SPSR_DAIF_SHIFT U(6) +#define SPSR_DAIF_MASK U(0xf) + +#define SPSR_AIF_SHIFT U(6) +#define SPSR_AIF_MASK U(0x7) + +#define SPSR_E_SHIFT U(9) +#define SPSR_E_MASK U(0x1) +#define SPSR_E_LITTLE U(0x0) +#define SPSR_E_BIG U(0x1) + +#define SPSR_T_SHIFT U(5) +#define SPSR_T_MASK U(0x1) +#define SPSR_T_ARM U(0x0) +#define SPSR_T_THUMB U(0x1) #define DISABLE_ALL_EXCEPTIONS \ (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) @@ -245,81 +245,81 @@ /* * RMR_EL3 definitions */ -#define RMR_EL3_RR_BIT (1 << 1) -#define RMR_EL3_AA64_BIT (1 << 0) +#define RMR_EL3_RR_BIT (U(1) << 1) +#define RMR_EL3_AA64_BIT (U(1) << 0) /* * HI-VECTOR address for AArch32 state */ -#define HI_VECTOR_BASE (0xFFFF0000) +#define HI_VECTOR_BASE U(0xFFFF0000) /* * TCR defintions */ #define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23)) -#define TCR_EL1_IPS_SHIFT 32 -#define TCR_EL3_PS_SHIFT 16 +#define TCR_EL1_IPS_SHIFT U(32) +#define TCR_EL3_PS_SHIFT U(16) -#define TCR_TxSZ_MIN 16 -#define TCR_TxSZ_MAX 39 +#define TCR_TxSZ_MIN U(16) +#define TCR_TxSZ_MAX U(39) /* (internal) physical address size bits in EL3/EL1 */ -#define TCR_PS_BITS_4GB (0x0) -#define TCR_PS_BITS_64GB (0x1) -#define TCR_PS_BITS_1TB (0x2) -#define TCR_PS_BITS_4TB (0x3) -#define TCR_PS_BITS_16TB (0x4) -#define TCR_PS_BITS_256TB (0x5) - -#define ADDR_MASK_48_TO_63 0xFFFF000000000000UL -#define ADDR_MASK_44_TO_47 0x0000F00000000000UL -#define ADDR_MASK_42_TO_43 0x00000C0000000000UL -#define ADDR_MASK_40_TO_41 0x0000030000000000UL -#define ADDR_MASK_36_TO_39 0x000000F000000000UL -#define ADDR_MASK_32_TO_35 0x0000000F00000000UL - -#define TCR_RGN_INNER_NC (0x0 << 8) -#define TCR_RGN_INNER_WBA (0x1 << 8) -#define TCR_RGN_INNER_WT (0x2 << 8) -#define TCR_RGN_INNER_WBNA (0x3 << 8) - -#define TCR_RGN_OUTER_NC (0x0 << 10) -#define TCR_RGN_OUTER_WBA (0x1 << 10) -#define TCR_RGN_OUTER_WT (0x2 << 10) -#define TCR_RGN_OUTER_WBNA (0x3 << 10) - -#define TCR_SH_NON_SHAREABLE (0x0 << 12) -#define TCR_SH_OUTER_SHAREABLE (0x2 << 12) -#define TCR_SH_INNER_SHAREABLE (0x3 << 12) - -#define MODE_SP_SHIFT 0x0 -#define MODE_SP_MASK 0x1 -#define MODE_SP_EL0 0x0 -#define MODE_SP_ELX 0x1 - -#define MODE_RW_SHIFT 0x4 -#define MODE_RW_MASK 0x1 -#define MODE_RW_64 0x0 -#define MODE_RW_32 0x1 - -#define MODE_EL_SHIFT 0x2 -#define MODE_EL_MASK 0x3 -#define MODE_EL3 0x3 -#define MODE_EL2 0x2 -#define MODE_EL1 0x1 -#define MODE_EL0 0x0 - -#define MODE32_SHIFT 0 -#define MODE32_MASK 0xf -#define MODE32_usr 0x0 -#define MODE32_fiq 0x1 -#define MODE32_irq 0x2 -#define MODE32_svc 0x3 -#define MODE32_mon 0x6 -#define MODE32_abt 0x7 -#define MODE32_hyp 0xa -#define MODE32_und 0xb -#define MODE32_sys 0xf +#define TCR_PS_BITS_4GB U(0x0) +#define TCR_PS_BITS_64GB U(0x1) +#define TCR_PS_BITS_1TB U(0x2) +#define TCR_PS_BITS_4TB U(0x3) +#define TCR_PS_BITS_16TB U(0x4) +#define TCR_PS_BITS_256TB U(0x5) + +#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) +#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) +#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) +#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) +#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) +#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) + +#define TCR_RGN_INNER_NC (U(0x0) << 8) +#define TCR_RGN_INNER_WBA (U(0x1) << 8) +#define TCR_RGN_INNER_WT (U(0x2) << 8) +#define TCR_RGN_INNER_WBNA (U(0x3) << 8) + +#define TCR_RGN_OUTER_NC (U(0x0) << 10) +#define TCR_RGN_OUTER_WBA (U(0x1) << 10) +#define TCR_RGN_OUTER_WT (U(0x2) << 10) +#define TCR_RGN_OUTER_WBNA (U(0x3) << 10) + +#define TCR_SH_NON_SHAREABLE (U(0x0) << 12) +#define TCR_SH_OUTER_SHAREABLE (U(0x2) << 12) +#define TCR_SH_INNER_SHAREABLE (U(0x3) << 12) + +#define MODE_SP_SHIFT U(0x0) +#define MODE_SP_MASK U(0x1) +#define MODE_SP_EL0 U(0x0) +#define MODE_SP_ELX U(0x1) + +#define MODE_RW_SHIFT U(0x4) +#define MODE_RW_MASK U(0x1) +#define MODE_RW_64 U(0x0) +#define MODE_RW_32 U(0x1) + +#define MODE_EL_SHIFT U(0x2) +#define MODE_EL_MASK U(0x3) +#define MODE_EL3 U(0x3) +#define MODE_EL2 U(0x2) +#define MODE_EL1 U(0x1) +#define MODE_EL0 U(0x0) + +#define MODE32_SHIFT U(0) +#define MODE32_MASK U(0xf) +#define MODE32_usr U(0x0) +#define MODE32_fiq U(0x1) +#define MODE32_irq U(0x2) +#define MODE32_svc U(0x3) +#define MODE32_mon U(0x6) +#define MODE32_abt U(0x7) +#define MODE32_hyp U(0xa) +#define MODE32_und U(0xb) +#define MODE32_sys U(0xf) #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) @@ -333,93 +333,93 @@ ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) #define SPSR_MODE32(mode, isa, endian, aif) \ - (MODE_RW_32 << MODE_RW_SHIFT | \ - ((mode) & MODE32_MASK) << MODE32_SHIFT | \ - ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ - ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ - ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) + ((MODE_RW_32 << MODE_RW_SHIFT) | \ + (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ + (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ + (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ + (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) /* * CTR_EL0 definitions */ -#define CTR_CWG_SHIFT 24 -#define CTR_CWG_MASK 0xf -#define CTR_ERG_SHIFT 20 -#define CTR_ERG_MASK 0xf -#define CTR_DMINLINE_SHIFT 16 -#define CTR_DMINLINE_MASK 0xf -#define CTR_L1IP_SHIFT 14 -#define CTR_L1IP_MASK 0x3 -#define CTR_IMINLINE_SHIFT 0 -#define CTR_IMINLINE_MASK 0xf - -#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */ +#define CTR_CWG_SHIFT U(24) +#define CTR_CWG_MASK U(0xf) +#define CTR_ERG_SHIFT U(20) +#define CTR_ERG_MASK U(0xf) +#define CTR_DMINLINE_SHIFT U(16) +#define CTR_DMINLINE_MASK U(0xf) +#define CTR_L1IP_SHIFT U(14) +#define CTR_L1IP_MASK U(0x3) +#define CTR_IMINLINE_SHIFT U(0) +#define CTR_IMINLINE_MASK U(0xf) + +#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ /* Physical timer control register bit fields shifts and masks */ -#define CNTP_CTL_ENABLE_SHIFT 0 -#define CNTP_CTL_IMASK_SHIFT 1 -#define CNTP_CTL_ISTATUS_SHIFT 2 +#define CNTP_CTL_ENABLE_SHIFT U(0) +#define CNTP_CTL_IMASK_SHIFT U(1) +#define CNTP_CTL_ISTATUS_SHIFT U(2) -#define CNTP_CTL_ENABLE_MASK 1 -#define CNTP_CTL_IMASK_MASK 1 -#define CNTP_CTL_ISTATUS_MASK 1 +#define CNTP_CTL_ENABLE_MASK U(1) +#define CNTP_CTL_IMASK_MASK U(1) +#define CNTP_CTL_ISTATUS_MASK U(1) -#define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \ +#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ CNTP_CTL_ENABLE_MASK) -#define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \ +#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ CNTP_CTL_IMASK_MASK) -#define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \ +#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ CNTP_CTL_ISTATUS_MASK) -#define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT) -#define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT) +#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) +#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) -#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT)) -#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT)) +#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) +#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) /* Exception Syndrome register bits and bobs */ -#define ESR_EC_SHIFT 26 -#define ESR_EC_MASK 0x3f -#define ESR_EC_LENGTH 6 -#define EC_UNKNOWN 0x0 -#define EC_WFE_WFI 0x1 -#define EC_AARCH32_CP15_MRC_MCR 0x3 -#define EC_AARCH32_CP15_MRRC_MCRR 0x4 -#define EC_AARCH32_CP14_MRC_MCR 0x5 -#define EC_AARCH32_CP14_LDC_STC 0x6 -#define EC_FP_SIMD 0x7 -#define EC_AARCH32_CP10_MRC 0x8 -#define EC_AARCH32_CP14_MRRC_MCRR 0xc -#define EC_ILLEGAL 0xe -#define EC_AARCH32_SVC 0x11 -#define EC_AARCH32_HVC 0x12 -#define EC_AARCH32_SMC 0x13 -#define EC_AARCH64_SVC 0x15 -#define EC_AARCH64_HVC 0x16 -#define EC_AARCH64_SMC 0x17 -#define EC_AARCH64_SYS 0x18 -#define EC_IABORT_LOWER_EL 0x20 -#define EC_IABORT_CUR_EL 0x21 -#define EC_PC_ALIGN 0x22 -#define EC_DABORT_LOWER_EL 0x24 -#define EC_DABORT_CUR_EL 0x25 -#define EC_SP_ALIGN 0x26 -#define EC_AARCH32_FP 0x28 -#define EC_AARCH64_FP 0x2c -#define EC_SERROR 0x2f - -#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK +#define ESR_EC_SHIFT U(26) +#define ESR_EC_MASK U(0x3f) +#define ESR_EC_LENGTH U(6) +#define EC_UNKNOWN U(0x0) +#define EC_WFE_WFI U(0x1) +#define EC_AARCH32_CP15_MRC_MCR U(0x3) +#define EC_AARCH32_CP15_MRRC_MCRR U(0x4) +#define EC_AARCH32_CP14_MRC_MCR U(0x5) +#define EC_AARCH32_CP14_LDC_STC U(0x6) +#define EC_FP_SIMD U(0x7) +#define EC_AARCH32_CP10_MRC U(0x8) +#define EC_AARCH32_CP14_MRRC_MCRR U(0xc) +#define EC_ILLEGAL U(0xe) +#define EC_AARCH32_SVC U(0x11) +#define EC_AARCH32_HVC U(0x12) +#define EC_AARCH32_SMC U(0x13) +#define EC_AARCH64_SVC U(0x15) +#define EC_AARCH64_HVC U(0x16) +#define EC_AARCH64_SMC U(0x17) +#define EC_AARCH64_SYS U(0x18) +#define EC_IABORT_LOWER_EL U(0x20) +#define EC_IABORT_CUR_EL U(0x21) +#define EC_PC_ALIGN U(0x22) +#define EC_DABORT_LOWER_EL U(0x24) +#define EC_DABORT_CUR_EL U(0x25) +#define EC_SP_ALIGN U(0x26) +#define EC_AARCH32_FP U(0x28) +#define EC_AARCH64_FP U(0x2c) +#define EC_SERROR U(0x2f) + +#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ -#define RMR_RESET_REQUEST_SHIFT 0x1u -#define RMR_WARM_RESET_CPU (1u << RMR_RESET_REQUEST_SHIFT) +#define RMR_RESET_REQUEST_SHIFT U(0x1) +#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) /******************************************************************************* * Definitions of register offsets, fields and macros for CPU system * instructions. ******************************************************************************/ -#define TLBI_ADDR_SHIFT 12 +#define TLBI_ADDR_SHIFT U(12) #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) @@ -427,20 +427,20 @@ * Definitions of register offsets and fields in the CNTCTLBase Frame of the * system level implementation of the Generic Timer. ******************************************************************************/ -#define CNTNSAR 0x4 -#define CNTNSAR_NS_SHIFT(x) x +#define CNTNSAR U(0x4) +#define CNTNSAR_NS_SHIFT(x) (x) -#define CNTACR_BASE(x) (0x40 + (x << 2)) -#define CNTACR_RPCT_SHIFT 0x0 -#define CNTACR_RVCT_SHIFT 0x1 -#define CNTACR_RFRQ_SHIFT 0x2 -#define CNTACR_RVOFF_SHIFT 0x3 -#define CNTACR_RWVT_SHIFT 0x4 -#define CNTACR_RWPT_SHIFT 0x5 +#define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) +#define CNTACR_RPCT_SHIFT U(0x0) +#define CNTACR_RVCT_SHIFT U(0x1) +#define CNTACR_RFRQ_SHIFT U(0x2) +#define CNTACR_RVOFF_SHIFT U(0x3) +#define CNTACR_RWVT_SHIFT U(0x4) +#define CNTACR_RWPT_SHIFT U(0x5) /* PMCR_EL0 definitions */ -#define PMCR_EL0_N_SHIFT 11 -#define PMCR_EL0_N_MASK 0x1f +#define PMCR_EL0_N_SHIFT U(11) +#define PMCR_EL0_N_MASK U(0x1f) #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) #endif /* __ARCH_H__ */ diff --git a/include/lib/aarch64/smcc_helpers.h b/include/lib/aarch64/smcc_helpers.h index ea2f7078..62294d04 100644 --- a/include/lib/aarch64/smcc_helpers.h +++ b/include/lib/aarch64/smcc_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,35 +17,35 @@ return (uint64_t) (_h); \ } #define SMC_RET1(_h, _x0) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X0, (_x0)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X0), (_x0)); \ SMC_RET0(_h); \ } #define SMC_RET2(_h, _x0, _x1) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X1, (_x1)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X1), (_x1)); \ SMC_RET1(_h, (_x0)); \ } #define SMC_RET3(_h, _x0, _x1, _x2) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X2, (_x2)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \ SMC_RET2(_h, (_x0), (_x1)); \ } #define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X3, (_x3)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X3), (_x3)); \ SMC_RET3(_h, (_x0), (_x1), (_x2)); \ } #define SMC_RET5(_h, _x0, _x1, _x2, _x3, _x4) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X4, (_x4)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X4), (_x4)); \ SMC_RET4(_h, (_x0), (_x1), (_x2), (_x3)); \ } #define SMC_RET6(_h, _x0, _x1, _x2, _x3, _x4, _x5) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X5, (_x5)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X5), (_x5)); \ SMC_RET5(_h, (_x0), (_x1), (_x2), (_x3), (_x4)); \ } #define SMC_RET7(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X6, (_x6)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X6), (_x6)); \ SMC_RET6(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5)); \ } #define SMC_RET8(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6, _x7) { \ - write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X7, (_x7)); \ + write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X7), (_x7)); \ SMC_RET7(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5), (_x6)); \ } @@ -54,18 +54,18 @@ * to SMC handler. These take the offset values defined in context.h */ #define SMC_GET_GP(_h, _g) \ - read_ctx_reg(get_gpregs_ctx(_h), (_g)) + read_ctx_reg((get_gpregs_ctx(_h)), (_g)) #define SMC_SET_GP(_h, _g, _v) \ - write_ctx_reg(get_gpregs_ctx(_h), (_g), (_v)) + write_ctx_reg((get_gpregs_ctx(_h)), (_g), (_v)) /* * Convenience macros to access EL3 context registers using handle provided to * SMC handler. These take the offset values defined in context.h */ #define SMC_GET_EL3(_h, _e) \ - read_ctx_reg(get_el3state_ctx(_h), (_e)) + read_ctx_reg((get_el3state_ctx(_h)), (_e)) #define SMC_SET_EL3(_h, _e, _v) \ - write_ctx_reg(get_el3state_ctx(_h), (_e), (_v)) + write_ctx_reg((get_el3state_ctx(_h)), (_e), (_v)) /* Return a UUID in the SMC return registers */ #define SMC_UUID_RET(_h, _uuid) \ diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h index 7f4c88ae..265cb158 100644 --- a/include/lib/cpus/aarch32/cortex_a53.h +++ b/include/lib/cpus/aarch32/cortex_a53.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,47 +22,47 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CPUECTLR p15, 1, c15 /* Instruction def. */ +#define CORTEX_A53_ECTLR p15, 1, c15 -#define CPUECTLR_SMP_BIT (1 << 6) +#define CORTEX_A53_ECTLR_SMP_BIT (1 << 6) -#define CPUECTLR_CPU_RET_CTRL_SHIFT 0 -#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT 0 +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) -#define CPUECTLR_FPU_RET_CTRL_SHIFT 3 -#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT 3 +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CPUMERRSR p15, 2, c15 /* Instruction def. */ +#define CORTEX_A53_MERRSR p15, 2, c15 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CPUACTLR p15, 0, c15 /* Instruction def. */ +#define CORTEX_A53_ACTLR p15, 0, c15 -#define CPUACTLR_DTAH (1 << 24) +#define CORTEX_A53_ACTLR_DTAH (1 << 24) /******************************************************************************* * L2 Auxiliary Control register specific definitions. ******************************************************************************/ -#define L2ACTLR p15, 1, c15, c0, 0 /* Instruction def. */ +#define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0 -#define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) -#define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) +#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) +#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) /******************************************************************************* * L2 Extended Control register specific definitions. ******************************************************************************/ -#define L2ECTLR p15, 1, c9, c0, 3 /* Instruction def. */ +#define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3 -#define L2ECTLR_RET_CTRL_SHIFT 0 -#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT 0 +#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define L2MERRSR p15, 3, c15 /* Instruction def. */ +#define CORTEX_A53_L2MERRSR p15, 3, c15 #endif /* __CORTEX_A53_H__ */ diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h index 94e5c8a4..1c3fa25c 100644 --- a/include/lib/cpus/aarch32/cortex_a57.h +++ b/include/lib/cpus/aarch32/cortex_a57.h @@ -22,58 +22,58 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CPUECTLR p15, 1, c15 /* Instruction def. */ +#define CORTEX_A57_ECTLR p15, 1, c15 -#define CPUECTLR_SMP_BIT (1 << 6) -#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A57_ECTLR_SMP_BIT (1 << 6) +#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) +#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) +#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) -#define CPUECTLR_CPU_RET_CTRL_SHIFT 0 -#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0 +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CPUMERRSR p15, 2, c15 /* Instruction def. */ +#define CORTEX_A57_CPUMERRSR p15, 2, c15 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CPUACTLR p15, 0, c15 /* Instruction def. */ - -#define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59) -#define CPUACTLR_GRE_NGRE_AS_NGNRE (1 << 54) -#define CPUACTLR_DIS_OVERREAD (1 << 52) -#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) -#define CPUACTLR_DCC_AS_DCCI (1 << 44) -#define CPUACTLR_FORCE_FPSCR_FLUSH (1 << 38) -#define CPUACTLR_DIS_STREAMING (3 << 27) -#define CPUACTLR_DIS_L1_STREAMING (3 << 25) -#define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) +#define CORTEX_A57_ACTLR p15, 0, c15 + +#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (1 << 59) +#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (1 << 54) +#define CORTEX_A57_ACTLR_DIS_OVERREAD (1 << 52) +#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (1 << 49) +#define CORTEX_A57_ACTLR_DCC_AS_DCCI (1 << 44) +#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (1 << 38) +#define CORTEX_A57_ACTLR_DIS_STREAMING (3 << 27) +#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (3 << 25) +#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define L2CTLR p15, 1, c9, c0, 3 /* Instruction def. */ +#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 3 -#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 -#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 /******************************************************************************* * L2 Extended Control register specific definitions. ******************************************************************************/ -#define L2ECTLR p15, 1, c9, c0, 3 /* Instruction def. */ +#define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3 -#define L2ECTLR_RET_CTRL_SHIFT 0 -#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0 +#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (0x7 << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define L2MERRSR p15, 3, c15 /* Instruction def. */ +#define CORTEX_A57_L2MERRSR p15, 3, c15 #endif /* __CORTEX_A57_H__ */ diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index e734b571..a550192c 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h @@ -13,42 +13,42 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CPUECTLR p15, 1, c15 /* Instruction def. */ +#define CORTEX_A72_ECTLR p15, 1, c15 -#define CPUECTLR_SMP_BIT (1 << 6) -#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6) +#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) +#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) +#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CPUMERRSR p15, 2, c15 /* Instruction def. */ +#define CORTEX_A72_MERRSR p15, 2, c15 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CPUACTLR p15, 0, c15 /* Instruction def. */ +#define CORTEX_A72_ACTLR p15, 0, c15 -#define CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) -#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) -#define CPUACTLR_DCC_AS_DCCI (1 << 44) +#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) +#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49) +#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define L2CTLR p15, 1, c9, c0, 3 /* Instruction def. */ +#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 3 -#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 -#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define L2_TAG_RAM_LATENCY_2_CYCLES 0x1 -#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define L2MERRSR p15, 3, c15 /* Instruction def. */ +#define CORTEX_A72_L2MERRSR p15, 3, c15 #endif /* __CORTEX_A72_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 10d9ee62..6627dcfa 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,68 +8,67 @@ #define __CORTEX_A53_H__ /* Cortex-A53 midr for revision 0 */ -#define CORTEX_A53_MIDR 0x410FD030 +#define CORTEX_A53_MIDR U(0x410FD030) /* Retention timer tick definitions */ -#define RETENTION_ENTRY_TICKS_2 0x1 -#define RETENTION_ENTRY_TICKS_8 0x2 -#define RETENTION_ENTRY_TICKS_32 0x3 -#define RETENTION_ENTRY_TICKS_64 0x4 -#define RETENTION_ENTRY_TICKS_128 0x5 -#define RETENTION_ENTRY_TICKS_256 0x6 -#define RETENTION_ENTRY_TICKS_512 0x7 +#define RETENTION_ENTRY_TICKS_2 U(0x1) +#define RETENTION_ENTRY_TICKS_8 U(0x2) +#define RETENTION_ENTRY_TICKS_32 U(0x3) +#define RETENTION_ENTRY_TICKS_64 U(0x4) +#define RETENTION_ENTRY_TICKS_128 U(0x5) +#define RETENTION_ENTRY_TICKS_256 U(0x6) +#define RETENTION_ENTRY_TICKS_512 U(0x7) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ +#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1 -#define CPUECTLR_SMP_BIT (1 << 6) +#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6) -#define CPUECTLR_CPU_RET_CTRL_SHIFT 0 -#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0) +#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) -#define CPUECTLR_FPU_RET_CTRL_SHIFT 3 -#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT) +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3) +#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ +#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ +#define CORTEX_A53_ACTLR_EL1 S3_1_C15_C2_0 -#define CPUACTLR_ENDCCASCI_SHIFT 44 -#define CPUACTLR_ENDCCASCI (1 << CPUACTLR_ENDCCASCI_SHIFT) -#define CPUACTLR_RADIS_SHIFT 27 -#define CPUACTLR_RADIS (3 << CPUACTLR_RADIS_SHIFT) -#define CPUACTLR_L1RADIS_SHIFT 25 -#define CPUACTLR_L1RADIS (3 << CPUACTLR_L1RADIS_SHIFT) -#define CPUACTLR_DTAH_SHIFT 24 -#define CPUACTLR_DTAH (1 << CPUACTLR_DTAH_SHIFT) +#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT U(44) +#define CORTEX_A53_ACTLR_ENDCCASCI (U(1) << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT) +#define CORTEX_A53_ACTLR_RADIS_SHIFT U(27) +#define CORTEX_A53_ACTLR_RADIS (U(3) << CORTEX_A53_ACTLR_RADIS_SHIFT) +#define CORTEX_A53_ACTLR_L1RADIS_SHIFT U(25) +#define CORTEX_A53_ACTLR_L1RADIS (U(3) << CORTEX_A53_ACTLR_L1RADIS_SHIFT) +#define CORTEX_A53_ACTLR_DTAH_SHIFT U(24) +#define CORTEX_A53_ACTLR_DTAH (U(1) << CORTEX_A53_ACTLR_DTAH_SHIFT) /******************************************************************************* * L2 Auxiliary Control register specific definitions. ******************************************************************************/ -#define L2ACTLR_EL1 S3_1_C15_C0_0 /* Instruction def. */ - -#define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) -#define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) +#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0 +#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14) +#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3) /******************************************************************************* * L2 Extended Control register specific definitions. ******************************************************************************/ -#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */ +#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3 -#define L2ECTLR_RET_CTRL_SHIFT 0 -#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0) +#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ +#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3 #endif /* __CORTEX_A53_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index c68f408c..20d11e14 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,74 +8,74 @@ #define __CORTEX_A57_H__ /* Cortex-A57 midr for revision 0 */ -#define CORTEX_A57_MIDR 0x410FD070 +#define CORTEX_A57_MIDR U(0x410FD070) /* Retention timer tick definitions */ -#define RETENTION_ENTRY_TICKS_2 0x1 -#define RETENTION_ENTRY_TICKS_8 0x2 -#define RETENTION_ENTRY_TICKS_32 0x3 -#define RETENTION_ENTRY_TICKS_64 0x4 -#define RETENTION_ENTRY_TICKS_128 0x5 -#define RETENTION_ENTRY_TICKS_256 0x6 -#define RETENTION_ENTRY_TICKS_512 0x7 +#define RETENTION_ENTRY_TICKS_2 U(0x1) +#define RETENTION_ENTRY_TICKS_8 U(0x2) +#define RETENTION_ENTRY_TICKS_32 U(0x3) +#define RETENTION_ENTRY_TICKS_64 U(0x4) +#define RETENTION_ENTRY_TICKS_128 U(0x5) +#define RETENTION_ENTRY_TICKS_256 U(0x6) +#define RETENTION_ENTRY_TICKS_512 U(0x7) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ +#define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 -#define CPUECTLR_SMP_BIT (1 << 6) -#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A57_ECTLR_SMP_BIT (U(1) << 6) +#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (U(1) << 38) +#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (U(0x3) << 35) +#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (U(0x3) << 32) -#define CPUECTLR_CPU_RET_CTRL_SHIFT 0 -#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) +#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ +#define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ - -#define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59) -#define CPUACTLR_GRE_NGRE_AS_NGNRE (1 << 54) -#define CPUACTLR_DIS_OVERREAD (1 << 52) -#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) -#define CPUACTLR_DCC_AS_DCCI (1 << 44) -#define CPUACTLR_FORCE_FPSCR_FLUSH (1 << 38) -#define CPUACTLR_DIS_STREAMING (3 << 27) -#define CPUACTLR_DIS_L1_STREAMING (3 << 25) -#define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) +#define CORTEX_A57_ACTLR_EL1 S3_1_C15_C2_0 + +#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) +#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) +#define CORTEX_A57_ACTLR_DIS_OVERREAD (ULL(1) << 52) +#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49) +#define CORTEX_A57_ACTLR_DCC_AS_DCCI (ULL(1) << 44) +#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38) +#define CORTEX_A57_ACTLR_DIS_STREAMING (ULL(3) << 27) +#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (ULL(3) << 25) +#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */ +#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 -#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) +#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) -#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) -#define L2_ECC_PARITY_PROTECTION_BIT (1 << 21) +#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) /******************************************************************************* * L2 Extended Control register specific definitions. ******************************************************************************/ -#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */ +#define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 -#define L2ECTLR_RET_CTRL_SHIFT 0 -#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) +#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) +#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ +#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 #endif /* __CORTEX_A57_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 51f7de68..90f0abd9 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,42 +13,42 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ +#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1 -#define CPUECTLR_SMP_BIT (1 << 6) -#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) -#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) -#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) +#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6) +#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) +#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) +#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) /******************************************************************************* * CPU Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ +#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2 /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ +#define CORTEX_A72_ACTLR_EL1 S3_1_C15_C2_0 -#define CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) -#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) -#define CPUACTLR_DCC_AS_DCCI (1 << 44) +#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) +#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49) +#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ -#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */ +#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 -#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 -#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 +#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 -#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 -#define L2_TAG_RAM_LATENCY_2_CYCLES 0x1 -#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 +#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 /******************************************************************************* * L2 Memory Error Syndrome register specific definitions. ******************************************************************************/ -#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ +#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3 #endif /* __CORTEX_A72_H__ */ diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h index d582d819..d8c4d2e7 100644 --- a/include/lib/cpus/aarch64/denver.h +++ b/include/lib/cpus/aarch64/denver.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,17 +8,17 @@ #define __DENVER_H__ /* MIDR values for Denver */ -#define DENVER_MIDR_PN0 0x4E0F0000 -#define DENVER_MIDR_PN1 0x4E0F0010 -#define DENVER_MIDR_PN2 0x4E0F0020 -#define DENVER_MIDR_PN3 0x4E0F0030 -#define DENVER_MIDR_PN4 0x4E0F0040 +#define DENVER_MIDR_PN0 U(0x4E0F0000) +#define DENVER_MIDR_PN1 U(0x4E0F0010) +#define DENVER_MIDR_PN2 U(0x4E0F0020) +#define DENVER_MIDR_PN3 U(0x4E0F0030) +#define DENVER_MIDR_PN4 U(0x4E0F0040) /* Implementer code in the MIDR register */ -#define DENVER_IMPL 0x4E +#define DENVER_IMPL U(0x4E) /* CPU state ids - implementation defined */ -#define DENVER_CPU_STATE_POWER_DOWN 0x3 +#define DENVER_CPU_STATE_POWER_DOWN U(0x3) #ifndef __ASSEMBLY__ diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h index a2ae897b..dead971c 100644 --- a/include/lib/el3_runtime/aarch64/context.h +++ b/include/lib/el3_runtime/aarch64/context.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,40 +11,40 @@ * Constants that allow assembler code to access members of and the 'gp_regs' * structure at their correct offsets. ******************************************************************************/ -#define CTX_GPREGS_OFFSET 0x0 -#define CTX_GPREG_X0 0x0 -#define CTX_GPREG_X1 0x8 -#define CTX_GPREG_X2 0x10 -#define CTX_GPREG_X3 0x18 -#define CTX_GPREG_X4 0x20 -#define CTX_GPREG_X5 0x28 -#define CTX_GPREG_X6 0x30 -#define CTX_GPREG_X7 0x38 -#define CTX_GPREG_X8 0x40 -#define CTX_GPREG_X9 0x48 -#define CTX_GPREG_X10 0x50 -#define CTX_GPREG_X11 0x58 -#define CTX_GPREG_X12 0x60 -#define CTX_GPREG_X13 0x68 -#define CTX_GPREG_X14 0x70 -#define CTX_GPREG_X15 0x78 -#define CTX_GPREG_X16 0x80 -#define CTX_GPREG_X17 0x88 -#define CTX_GPREG_X18 0x90 -#define CTX_GPREG_X19 0x98 -#define CTX_GPREG_X20 0xa0 -#define CTX_GPREG_X21 0xa8 -#define CTX_GPREG_X22 0xb0 -#define CTX_GPREG_X23 0xb8 -#define CTX_GPREG_X24 0xc0 -#define CTX_GPREG_X25 0xc8 -#define CTX_GPREG_X26 0xd0 -#define CTX_GPREG_X27 0xd8 -#define CTX_GPREG_X28 0xe0 -#define CTX_GPREG_X29 0xe8 -#define CTX_GPREG_LR 0xf0 -#define CTX_GPREG_SP_EL0 0xf8 -#define CTX_GPREGS_END 0x100 +#define CTX_GPREGS_OFFSET U(0x0) +#define CTX_GPREG_X0 U(0x0) +#define CTX_GPREG_X1 U(0x8) +#define CTX_GPREG_X2 U(0x10) +#define CTX_GPREG_X3 U(0x18) +#define CTX_GPREG_X4 U(0x20) +#define CTX_GPREG_X5 U(0x28) +#define CTX_GPREG_X6 U(0x30) +#define CTX_GPREG_X7 U(0x38) +#define CTX_GPREG_X8 U(0x40) +#define CTX_GPREG_X9 U(0x48) +#define CTX_GPREG_X10 U(0x50) +#define CTX_GPREG_X11 U(0x58) +#define CTX_GPREG_X12 U(0x60) +#define CTX_GPREG_X13 U(0x68) +#define CTX_GPREG_X14 U(0x70) +#define CTX_GPREG_X15 U(0x78) +#define CTX_GPREG_X16 U(0x80) +#define CTX_GPREG_X17 U(0x88) +#define CTX_GPREG_X18 U(0x90) +#define CTX_GPREG_X19 U(0x98) +#define CTX_GPREG_X20 U(0xa0) +#define CTX_GPREG_X21 U(0xa8) +#define CTX_GPREG_X22 U(0xb0) +#define CTX_GPREG_X23 U(0xb8) +#define CTX_GPREG_X24 U(0xc0) +#define CTX_GPREG_X25 U(0xc8) +#define CTX_GPREG_X26 U(0xd0) +#define CTX_GPREG_X27 U(0xd8) +#define CTX_GPREG_X28 U(0xe0) +#define CTX_GPREG_X29 U(0xe8) +#define CTX_GPREG_LR U(0xf0) +#define CTX_GPREG_SP_EL0 U(0xf8) +#define CTX_GPREGS_END U(0x100) /******************************************************************************* * Constants that allow assembler code to access members of and the 'el3_state' @@ -52,11 +52,11 @@ * 32-bits wide but are stored as 64-bit values for convenience ******************************************************************************/ #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) -#define CTX_SCR_EL3 0x0 -#define CTX_RUNTIME_SP 0x8 -#define CTX_SPSR_EL3 0x10 -#define CTX_ELR_EL3 0x18 -#define CTX_EL3STATE_END 0x20 +#define CTX_SCR_EL3 U(0x0) +#define CTX_RUNTIME_SP U(0x8) +#define CTX_SPSR_EL3 U(0x10) +#define CTX_ELR_EL3 U(0x18) +#define CTX_EL3STATE_END U(0x20) /******************************************************************************* * Constants that allow assembler code to access members of and the @@ -65,44 +65,44 @@ * convenience ******************************************************************************/ #define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) -#define CTX_SPSR_EL1 0x0 -#define CTX_ELR_EL1 0x8 -#define CTX_SCTLR_EL1 0x10 -#define CTX_ACTLR_EL1 0x18 -#define CTX_CPACR_EL1 0x20 -#define CTX_CSSELR_EL1 0x28 -#define CTX_SP_EL1 0x30 -#define CTX_ESR_EL1 0x38 -#define CTX_TTBR0_EL1 0x40 -#define CTX_TTBR1_EL1 0x48 -#define CTX_MAIR_EL1 0x50 -#define CTX_AMAIR_EL1 0x58 -#define CTX_TCR_EL1 0x60 -#define CTX_TPIDR_EL1 0x68 -#define CTX_TPIDR_EL0 0x70 -#define CTX_TPIDRRO_EL0 0x78 -#define CTX_PAR_EL1 0x80 -#define CTX_FAR_EL1 0x88 -#define CTX_AFSR0_EL1 0x90 -#define CTX_AFSR1_EL1 0x98 -#define CTX_CONTEXTIDR_EL1 0xa0 -#define CTX_VBAR_EL1 0xa8 +#define CTX_SPSR_EL1 U(0x0) +#define CTX_ELR_EL1 U(0x8) +#define CTX_SCTLR_EL1 U(0x10) +#define CTX_ACTLR_EL1 U(0x18) +#define CTX_CPACR_EL1 U(0x20) +#define CTX_CSSELR_EL1 U(0x28) +#define CTX_SP_EL1 U(0x30) +#define CTX_ESR_EL1 U(0x38) +#define CTX_TTBR0_EL1 U(0x40) +#define CTX_TTBR1_EL1 U(0x48) +#define CTX_MAIR_EL1 U(0x50) +#define CTX_AMAIR_EL1 U(0x58) +#define CTX_TCR_EL1 U(0x60) +#define CTX_TPIDR_EL1 U(0x68) +#define CTX_TPIDR_EL0 U(0x70) +#define CTX_TPIDRRO_EL0 U(0x78) +#define CTX_PAR_EL1 U(0x80) +#define CTX_FAR_EL1 U(0x88) +#define CTX_AFSR0_EL1 U(0x90) +#define CTX_AFSR1_EL1 U(0x98) +#define CTX_CONTEXTIDR_EL1 U(0xa0) +#define CTX_VBAR_EL1 U(0xa8) /* * If the platform is AArch64-only, there is no need to save and restore these * AArch32 registers. */ #if CTX_INCLUDE_AARCH32_REGS -#define CTX_SPSR_ABT 0xb0 -#define CTX_SPSR_UND 0xb8 -#define CTX_SPSR_IRQ 0xc0 -#define CTX_SPSR_FIQ 0xc8 -#define CTX_DACR32_EL2 0xd0 -#define CTX_IFSR32_EL2 0xd8 -#define CTX_FP_FPEXC32_EL2 0xe0 -#define CTX_TIMER_SYSREGS_OFF 0xf0 /* Align to the next 16 byte boundary */ +#define CTX_SPSR_ABT U(0xb0) +#define CTX_SPSR_UND U(0xb8) +#define CTX_SPSR_IRQ U(0xc0) +#define CTX_SPSR_FIQ U(0xc8) +#define CTX_DACR32_EL2 U(0xd0) +#define CTX_IFSR32_EL2 U(0xd8) +#define CTX_FP_FPEXC32_EL2 U(0xe0) +#define CTX_TIMER_SYSREGS_OFF U(0xf0) /* Align to the next 16 byte boundary */ #else -#define CTX_TIMER_SYSREGS_OFF 0xb0 +#define CTX_TIMER_SYSREGS_OFF U(0xb0) #endif /* __CTX_INCLUDE_AARCH32_REGS__ */ /* @@ -110,12 +110,12 @@ * space for them in the context */ #if NS_TIMER_SWITCH -#define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x0) -#define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x8) -#define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x10) -#define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x18) -#define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + 0x20) -#define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + 0x30) /* Align to the next 16 byte boundary */ +#define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x0)) +#define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x8)) +#define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x10)) +#define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x18)) +#define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + U(0x20)) +#define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + U(0x30)) /* Align to the next 16 byte boundary */ #else #define CTX_SYSREGS_END CTX_TIMER_SYSREGS_OFF #endif /* __NS_TIMER_SWITCH__ */ @@ -126,41 +126,41 @@ ******************************************************************************/ #if CTX_INCLUDE_FPREGS #define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) -#define CTX_FP_Q0 0x0 -#define CTX_FP_Q1 0x10 -#define CTX_FP_Q2 0x20 -#define CTX_FP_Q3 0x30 -#define CTX_FP_Q4 0x40 -#define CTX_FP_Q5 0x50 -#define CTX_FP_Q6 0x60 -#define CTX_FP_Q7 0x70 -#define CTX_FP_Q8 0x80 -#define CTX_FP_Q9 0x90 -#define CTX_FP_Q10 0xa0 -#define CTX_FP_Q11 0xb0 -#define CTX_FP_Q12 0xc0 -#define CTX_FP_Q13 0xd0 -#define CTX_FP_Q14 0xe0 -#define CTX_FP_Q15 0xf0 -#define CTX_FP_Q16 0x100 -#define CTX_FP_Q17 0x110 -#define CTX_FP_Q18 0x120 -#define CTX_FP_Q19 0x130 -#define CTX_FP_Q20 0x140 -#define CTX_FP_Q21 0x150 -#define CTX_FP_Q22 0x160 -#define CTX_FP_Q23 0x170 -#define CTX_FP_Q24 0x180 -#define CTX_FP_Q25 0x190 -#define CTX_FP_Q26 0x1a0 -#define CTX_FP_Q27 0x1b0 -#define CTX_FP_Q28 0x1c0 -#define CTX_FP_Q29 0x1d0 -#define CTX_FP_Q30 0x1e0 -#define CTX_FP_Q31 0x1f0 -#define CTX_FP_FPSR 0x200 -#define CTX_FP_FPCR 0x208 -#define CTX_FPREGS_END 0x210 +#define CTX_FP_Q0 U(0x0) +#define CTX_FP_Q1 U(0x10) +#define CTX_FP_Q2 U(0x20) +#define CTX_FP_Q3 U(0x30) +#define CTX_FP_Q4 U(0x40) +#define CTX_FP_Q5 U(0x50) +#define CTX_FP_Q6 U(0x60) +#define CTX_FP_Q7 U(0x70) +#define CTX_FP_Q8 U(0x80) +#define CTX_FP_Q9 U(0x90) +#define CTX_FP_Q10 U(0xa0) +#define CTX_FP_Q11 U(0xb0) +#define CTX_FP_Q12 U(0xc0) +#define CTX_FP_Q13 U(0xd0) +#define CTX_FP_Q14 U(0xe0) +#define CTX_FP_Q15 U(0xf0) +#define CTX_FP_Q16 U(0x100) +#define CTX_FP_Q17 U(0x110) +#define CTX_FP_Q18 U(0x120) +#define CTX_FP_Q19 U(0x130) +#define CTX_FP_Q20 U(0x140) +#define CTX_FP_Q21 U(0x150) +#define CTX_FP_Q22 U(0x160) +#define CTX_FP_Q23 U(0x170) +#define CTX_FP_Q24 U(0x180) +#define CTX_FP_Q25 U(0x190) +#define CTX_FP_Q26 U(0x1a0) +#define CTX_FP_Q27 U(0x1b0) +#define CTX_FP_Q28 U(0x1c0) +#define CTX_FP_Q29 U(0x1d0) +#define CTX_FP_Q30 U(0x1e0) +#define CTX_FP_Q31 U(0x1f0) +#define CTX_FP_FPSR U(0x200) +#define CTX_FP_FPCR U(0x208) +#define CTX_FPREGS_END U(0x210) #endif #ifndef __ASSEMBLY__ @@ -173,7 +173,7 @@ * Common constants to help define the 'cpu_context' structure and its * members below. */ -#define DWORD_SHIFT 3 +#define DWORD_SHIFT U(3) #define DEFINE_REG_STRUCT(name, num_regs) \ typedef struct name { \ uint64_t _regs[num_regs]; \ diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h index b23ed943..fee6a24f 100644 --- a/include/lib/psci/psci.h +++ b/include/lib/psci/psci.h @@ -14,6 +14,7 @@ #include <psci_compat.h> #endif #include <psci_lib.h> /* To maintain compatibility for SPDs */ +#include <utils_def.h> /******************************************************************************* * Number of power domains whose state this PSCI implementation can track @@ -21,90 +22,90 @@ #ifdef PLAT_NUM_PWR_DOMAINS #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS #else -#define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT) +#define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT) #endif #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ PLATFORM_CORE_COUNT) /* This is the power level corresponding to a CPU */ -#define PSCI_CPU_PWR_LVL 0 +#define PSCI_CPU_PWR_LVL (0) /* * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND * uses the old power_state parameter format which has 2 bits to specify the * power level, this constant is defined to be 3. */ -#define PSCI_MAX_PWR_LVL 3 +#define PSCI_MAX_PWR_LVL U(3) /******************************************************************************* * Defines for runtime services function ids ******************************************************************************/ -#define PSCI_VERSION 0x84000000 -#define PSCI_CPU_SUSPEND_AARCH32 0x84000001 -#define PSCI_CPU_SUSPEND_AARCH64 0xc4000001 -#define PSCI_CPU_OFF 0x84000002 -#define PSCI_CPU_ON_AARCH32 0x84000003 -#define PSCI_CPU_ON_AARCH64 0xc4000003 -#define PSCI_AFFINITY_INFO_AARCH32 0x84000004 -#define PSCI_AFFINITY_INFO_AARCH64 0xc4000004 -#define PSCI_MIG_AARCH32 0x84000005 -#define PSCI_MIG_AARCH64 0xc4000005 -#define PSCI_MIG_INFO_TYPE 0x84000006 -#define PSCI_MIG_INFO_UP_CPU_AARCH32 0x84000007 -#define PSCI_MIG_INFO_UP_CPU_AARCH64 0xc4000007 -#define PSCI_SYSTEM_OFF 0x84000008 -#define PSCI_SYSTEM_RESET 0x84000009 -#define PSCI_FEATURES 0x8400000A -#define PSCI_NODE_HW_STATE_AARCH32 0x8400000d -#define PSCI_NODE_HW_STATE_AARCH64 0xc400000d -#define PSCI_SYSTEM_SUSPEND_AARCH32 0x8400000E -#define PSCI_SYSTEM_SUSPEND_AARCH64 0xc400000E -#define PSCI_STAT_RESIDENCY_AARCH32 0x84000010 -#define PSCI_STAT_RESIDENCY_AARCH64 0xc4000010 -#define PSCI_STAT_COUNT_AARCH32 0x84000011 -#define PSCI_STAT_COUNT_AARCH64 0xc4000011 +#define PSCI_VERSION U(0x84000000) +#define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001) +#define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001) +#define PSCI_CPU_OFF U(0x84000002) +#define PSCI_CPU_ON_AARCH32 U(0x84000003) +#define PSCI_CPU_ON_AARCH64 U(0xc4000003) +#define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004) +#define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004) +#define PSCI_MIG_AARCH32 U(0x84000005) +#define PSCI_MIG_AARCH64 U(0xc4000005) +#define PSCI_MIG_INFO_TYPE U(0x84000006) +#define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007) +#define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007) +#define PSCI_SYSTEM_OFF U(0x84000008) +#define PSCI_SYSTEM_RESET U(0x84000009) +#define PSCI_FEATURES U(0x8400000A) +#define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d) +#define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d) +#define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E) +#define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E) +#define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010) +#define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010) +#define PSCI_STAT_COUNT_AARCH32 U(0x84000011) +#define PSCI_STAT_COUNT_AARCH64 U(0xc4000011) /* Macro to help build the psci capabilities bitfield */ -#define define_psci_cap(x) (1 << (x & 0x1f)) +#define define_psci_cap(x) (U(1) << (x & U(0x1f))) /* * Number of PSCI calls (above) implemented */ #if ENABLE_PSCI_STAT -#define PSCI_NUM_CALLS 22 +#define PSCI_NUM_CALLS U(22) #else -#define PSCI_NUM_CALLS 18 +#define PSCI_NUM_CALLS U(18) #endif /* The macros below are used to identify PSCI calls from the SMC function ID */ -#define PSCI_FID_MASK 0xffe0u -#define PSCI_FID_VALUE 0u +#define PSCI_FID_MASK U(0xffe0) +#define PSCI_FID_VALUE U(0) #define is_psci_fid(_fid) \ (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) /******************************************************************************* * PSCI Migrate and friends ******************************************************************************/ -#define PSCI_TOS_UP_MIG_CAP 0 -#define PSCI_TOS_NOT_UP_MIG_CAP 1 -#define PSCI_TOS_NOT_PRESENT_MP 2 +#define PSCI_TOS_UP_MIG_CAP U(0) +#define PSCI_TOS_NOT_UP_MIG_CAP U(1) +#define PSCI_TOS_NOT_PRESENT_MP U(2) /******************************************************************************* * PSCI CPU_SUSPEND 'power_state' parameter specific defines ******************************************************************************/ -#define PSTATE_ID_SHIFT 0 +#define PSTATE_ID_SHIFT U(0) #if PSCI_EXTENDED_STATE_ID -#define PSTATE_VALID_MASK 0xB0000000 -#define PSTATE_TYPE_SHIFT 30 -#define PSTATE_ID_MASK 0xfffffff +#define PSTATE_VALID_MASK U(0xB0000000) +#define PSTATE_TYPE_SHIFT U(30) +#define PSTATE_ID_MASK U(0xfffffff) #else -#define PSTATE_VALID_MASK 0xFCFE0000 -#define PSTATE_TYPE_SHIFT 16 -#define PSTATE_PWR_LVL_SHIFT 24 -#define PSTATE_ID_MASK 0xffff -#define PSTATE_PWR_LVL_MASK 0x3 +#define PSTATE_VALID_MASK U(0xFCFE0000) +#define PSTATE_TYPE_SHIFT U(16) +#define PSTATE_PWR_LVL_SHIFT U(24) +#define PSTATE_ID_MASK U(0xffff) +#define PSTATE_PWR_LVL_MASK U(0x3) #define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ PSTATE_PWR_LVL_MASK) @@ -114,9 +115,9 @@ (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) #endif /* __PSCI_EXTENDED_STATE_ID__ */ -#define PSTATE_TYPE_STANDBY 0x0 -#define PSTATE_TYPE_POWERDOWN 0x1 -#define PSTATE_TYPE_MASK 0x1 +#define PSTATE_TYPE_STANDBY U(0x0) +#define PSTATE_TYPE_POWERDOWN U(0x1) +#define PSTATE_TYPE_MASK U(0x1) #define psci_get_pstate_id(pstate) (((pstate) >> PSTATE_ID_SHIFT) & \ PSTATE_ID_MASK) @@ -128,9 +129,9 @@ * PSCI CPU_FEATURES feature flag specific defines ******************************************************************************/ /* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ -#define FF_PSTATE_SHIFT 1 -#define FF_PSTATE_ORIG 0 -#define FF_PSTATE_EXTENDED 1 +#define FF_PSTATE_SHIFT U(1) +#define FF_PSTATE_ORIG U(0) +#define FF_PSTATE_EXTENDED U(1) #if PSCI_EXTENDED_STATE_ID #define FF_PSTATE FF_PSTATE_EXTENDED #else @@ -138,14 +139,14 @@ #endif /* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ -#define FF_MODE_SUPPORT_SHIFT 0 -#define FF_SUPPORTS_OS_INIT_MODE 1 +#define FF_MODE_SUPPORT_SHIFT U(0) +#define FF_SUPPORTS_OS_INIT_MODE U(1) /******************************************************************************* * PSCI version ******************************************************************************/ -#define PSCI_MAJOR_VER (1 << 16) -#define PSCI_MINOR_VER 0x0 +#define PSCI_MAJOR_VER (U(1) << 16) +#define PSCI_MINOR_VER U(0x0) /******************************************************************************* * PSCI error codes @@ -174,9 +175,9 @@ * PSCI specification (ARM DEN 0022C). */ typedef enum { - AFF_STATE_ON = 0, - AFF_STATE_OFF = 1, - AFF_STATE_ON_PENDING = 2 + AFF_STATE_ON = U(0), + AFF_STATE_OFF = U(1), + AFF_STATE_ON_PENDING = U(2) } aff_info_state_t; /* @@ -185,15 +186,15 @@ typedef enum { * of PSCI specification (ARM DEN 0022C). */ typedef enum { - HW_ON = 0, - HW_OFF = 1, - HW_STANDBY = 2 + HW_ON = U(0), + HW_OFF = U(1), + HW_STANDBY = U(2) } node_hw_state_t; /* * Macro to represent invalid affinity level within PSCI. */ -#define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + 1) +#define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1)) /* * Type for representing the local power state at a particular level. @@ -201,7 +202,7 @@ typedef enum { typedef uint8_t plat_local_state_t; /* The local state macro used to represent RUN state. */ -#define PSCI_LOCAL_STATE_RUN 0 +#define PSCI_LOCAL_STATE_RUN U(0) /* * Macro to test whether the plat_local_state is RUN state @@ -236,7 +237,7 @@ typedef struct psci_power_state { * The pwr_domain_state[] stores the local power state at each level * for the CPU. */ - plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + 1]; + plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)]; } psci_power_state_t; /******************************************************************************* diff --git a/include/lib/smcc.h b/include/lib/smcc.h index 7270a88f..13b1e7ac 100644 --- a/include/lib/smcc.h +++ b/include/lib/smcc.h @@ -12,55 +12,55 @@ /******************************************************************************* * Bit definitions inside the function id as per the SMC calling convention ******************************************************************************/ -#define FUNCID_TYPE_SHIFT 31 -#define FUNCID_CC_SHIFT 30 -#define FUNCID_OEN_SHIFT 24 -#define FUNCID_NUM_SHIFT 0 +#define FUNCID_TYPE_SHIFT U(31) +#define FUNCID_CC_SHIFT U(30) +#define FUNCID_OEN_SHIFT U(24) +#define FUNCID_NUM_SHIFT U(0) -#define FUNCID_TYPE_MASK 0x1 -#define FUNCID_CC_MASK 0x1 -#define FUNCID_OEN_MASK 0x3f -#define FUNCID_NUM_MASK 0xffff +#define FUNCID_TYPE_MASK U(0x1) +#define FUNCID_CC_MASK U(0x1) +#define FUNCID_OEN_MASK U(0x3f) +#define FUNCID_NUM_MASK U(0xffff) -#define FUNCID_TYPE_WIDTH 1 -#define FUNCID_CC_WIDTH 1 -#define FUNCID_OEN_WIDTH 6 -#define FUNCID_NUM_WIDTH 16 +#define FUNCID_TYPE_WIDTH U(1) +#define FUNCID_CC_WIDTH U(1) +#define FUNCID_OEN_WIDTH U(6) +#define FUNCID_NUM_WIDTH U(16) #define GET_SMC_CC(id) ((id >> FUNCID_CC_SHIFT) & \ FUNCID_CC_MASK) #define GET_SMC_TYPE(id) ((id >> FUNCID_TYPE_SHIFT) & \ FUNCID_TYPE_MASK) -#define SMC_64 1 -#define SMC_32 0 -#define SMC_OK 0 -#define SMC_UNK 0xffffffff +#define SMC_64 U(1) +#define SMC_32 U(0) +#define SMC_OK U(0) +#define SMC_UNK U(0xffffffff) #define SMC_TYPE_FAST ULL(1) #if !ERROR_DEPRECATED -#define SMC_TYPE_STD 0 +#define SMC_TYPE_STD ULL(0) #endif -#define SMC_TYPE_YIELD 0 -#define SMC_PREEMPTED 0xfffffffe +#define SMC_TYPE_YIELD U(0) +#define SMC_PREEMPTED U(0xfffffffe) /******************************************************************************* * Owning entity number definitions inside the function id as per the SMC * calling convention ******************************************************************************/ -#define OEN_ARM_START 0 -#define OEN_ARM_END 0 -#define OEN_CPU_START 1 -#define OEN_CPU_END 1 -#define OEN_SIP_START 2 -#define OEN_SIP_END 2 -#define OEN_OEM_START 3 -#define OEN_OEM_END 3 -#define OEN_STD_START 4 /* Standard Service Calls */ -#define OEN_STD_END 4 -#define OEN_TAP_START 48 /* Trusted Applications */ -#define OEN_TAP_END 49 -#define OEN_TOS_START 50 /* Trusted OS */ -#define OEN_TOS_END 63 -#define OEN_LIMIT 64 +#define OEN_ARM_START U(0) +#define OEN_ARM_END U(0) +#define OEN_CPU_START U(1) +#define OEN_CPU_END U(1) +#define OEN_SIP_START U(2) +#define OEN_SIP_END U(2) +#define OEN_OEM_START U(3) +#define OEN_OEM_END U(3) +#define OEN_STD_START U(4) /* Standard Service Calls */ +#define OEN_STD_END U(4) +#define OEN_TAP_START U(48) /* Trusted Applications */ +#define OEN_TAP_END U(49) +#define OEN_TOS_START U(50) /* Trusted OS */ +#define OEN_TOS_END U(63) +#define OEN_LIMIT U(64) #ifndef __ASSEMBLY__ @@ -68,8 +68,8 @@ #include <stdint.h> /* Various flags passed to SMC handlers */ -#define SMC_FROM_SECURE (0 << 0) -#define SMC_FROM_NON_SECURE (1 << 0) +#define SMC_FROM_SECURE (U(0) << 0) +#define SMC_FROM_NON_SECURE (U(1) << 0) #define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE)) #define is_caller_secure(_f) (!(is_caller_non_secure(_f))) @@ -79,7 +79,7 @@ FUNCID_OEN_MASK) == OEN_STD_START) /* The macro below is used to identify a valid Fast SMC call */ -#define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & 0xff)) && \ +#define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & U(0xff))) && \ (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST)) /* diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h index 98e78347..52496000 100644 --- a/include/lib/utils_def.h +++ b/include/lib/utils_def.h @@ -57,16 +57,19 @@ (((ptr) > UINTPTR_MAX - (inc)) ? 1 : 0) /* - * For those constants to be shared between C and other sources, apply a 'ull' - * suffix to the argument only in C, to avoid undefined or unintended behaviour. + * For those constants to be shared between C and other sources, apply a 'u' + * or 'ull' suffix to the argument only in C, to avoid undefined or unintended + * behaviour. * - * The GNU assembler and linker do not support the 'ull' suffix (it causes the - * build process to fail) therefore the suffix is omitted when used in linker - * scripts and assembler files. + * The GNU assembler and linker do not support the 'u' and 'ull' suffix (it + * causes the build process to fail) therefore the suffix is omitted when used + * in linker scripts and assembler files. */ #if defined(__LINKER__) || defined(__ASSEMBLY__) +# define U(_x) (_x) # define ULL(_x) (_x) #else +# define U(_x) (_x##u) # define ULL(_x) (_x##ull) #endif diff --git a/include/lib/xlat_tables/xlat_tables.h b/include/lib/xlat_tables/xlat_tables.h index 66efa209..91f2f055 100644 --- a/include/lib/xlat_tables/xlat_tables.h +++ b/include/lib/xlat_tables/xlat_tables.h @@ -27,14 +27,14 @@ /* * Shifts and masks to access fields of an mmap_attr_t */ -#define MT_TYPE_MASK 0x7 +#define MT_TYPE_MASK U(0x7) #define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK) /* Access permissions (RO/RW) */ -#define MT_PERM_SHIFT 3 +#define MT_PERM_SHIFT U(3) /* Security state (SECURE/NS) */ -#define MT_SEC_SHIFT 4 +#define MT_SEC_SHIFT U(4) /* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */ -#define MT_EXECUTE_SHIFT 5 +#define MT_EXECUTE_SHIFT U(5) /* * Memory mapping attributes @@ -51,11 +51,11 @@ typedef enum { MT_MEMORY, /* Values up to 7 are reserved to add new memory types in the future */ - MT_RO = 0 << MT_PERM_SHIFT, - MT_RW = 1 << MT_PERM_SHIFT, + MT_RO = U(0) << MT_PERM_SHIFT, + MT_RW = U(1) << MT_PERM_SHIFT, - MT_SECURE = 0 << MT_SEC_SHIFT, - MT_NS = 1 << MT_SEC_SHIFT, + MT_SECURE = U(0) << MT_SEC_SHIFT, + MT_NS = U(1) << MT_SEC_SHIFT, /* * Access permissions for instruction execution are only relevant for @@ -64,8 +64,8 @@ typedef enum { * - Device memory is always marked as execute-never. * - Read-write normal memory is always marked as execute-never. */ - MT_EXECUTE = 0 << MT_EXECUTE_SHIFT, - MT_EXECUTE_NEVER = 1 << MT_EXECUTE_SHIFT, + MT_EXECUTE = U(0) << MT_EXECUTE_SHIFT, + MT_EXECUTE_NEVER = U(1) << MT_EXECUTE_SHIFT, } mmap_attr_t; #define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE) diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h index c54b7294..4b993a04 100644 --- a/include/lib/xlat_tables/xlat_tables_defs.h +++ b/include/lib/xlat_tables/xlat_tables_defs.h @@ -10,23 +10,23 @@ #include <utils_def.h> /* Miscellaneous MMU related constants */ -#define NUM_2MB_IN_GB (1 << 9) -#define NUM_4K_IN_2MB (1 << 9) -#define NUM_GB_IN_4GB (1 << 2) +#define NUM_2MB_IN_GB (U(1) << 9) +#define NUM_4K_IN_2MB (U(1) << 9) +#define NUM_GB_IN_4GB (U(1) << 2) -#define TWO_MB_SHIFT 21 -#define ONE_GB_SHIFT 30 -#define FOUR_KB_SHIFT 12 +#define TWO_MB_SHIFT U(21) +#define ONE_GB_SHIFT U(30) +#define FOUR_KB_SHIFT U(12) #define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) #define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) #define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) -#define INVALID_DESC 0x0 -#define BLOCK_DESC 0x1 /* Table levels 0-2 */ -#define TABLE_DESC 0x3 /* Table levels 0-2 */ -#define PAGE_DESC 0x3 /* Table level 3 */ -#define DESC_MASK 0x3 +#define INVALID_DESC U(0x0) +#define BLOCK_DESC U(0x1) /* Table levels 0-2 */ +#define TABLE_DESC U(0x3) /* Table levels 0-2 */ +#define PAGE_DESC U(0x3) /* Table level 3 */ +#define DESC_MASK U(0x3) #define FIRST_LEVEL_DESC_N ONE_GB_SHIFT #define SECOND_LEVEL_DESC_N TWO_MB_SHIFT @@ -40,36 +40,36 @@ #define CONT_HINT (ULL(1) << 0) #define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52) -#define NON_GLOBAL (1 << 9) -#define ACCESS_FLAG (1 << 8) -#define NSH (0x0 << 6) -#define OSH (0x2 << 6) -#define ISH (0x3 << 6) +#define NON_GLOBAL (U(1) << 9) +#define ACCESS_FLAG (U(1) << 8) +#define NSH (U(0x0) << 6) +#define OSH (U(0x2) << 6) +#define ISH (U(0x3) << 6) #define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000) #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT /* 4, 16 or 64 KB */ -#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) +#define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT) #define PAGE_SIZE_MASK (PAGE_SIZE - 1) #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) -#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */ -#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT) +#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes (1 << 3) */ +#define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT) #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ -#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT) +#define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT) #ifdef AARCH32 -#define XLAT_TABLE_LEVEL_MIN 1 +#define XLAT_TABLE_LEVEL_MIN U(1) #else -#define XLAT_TABLE_LEVEL_MIN 0 +#define XLAT_TABLE_LEVEL_MIN U(0) #endif /* AARCH32 */ -#define XLAT_TABLE_LEVEL_MAX 3 +#define XLAT_TABLE_LEVEL_MAX U(3) /* Values for number of entries in each MMU translation table */ #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) -#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT) +#define XLAT_TABLE_ENTRIES (U(1) << XLAT_TABLE_ENTRIES_SHIFT) #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) /* Values to convert a memory address to an index into a translation table */ @@ -90,34 +90,34 @@ * AP[1] bit is ignored by hardware and is * treated as if it is One in EL2/EL3 */ -#define AP_RO (0x1 << 5) -#define AP_RW (0x0 << 5) - -#define NS (0x1 << 3) -#define ATTR_NON_CACHEABLE_INDEX 0x2 -#define ATTR_DEVICE_INDEX 0x1 -#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 -#define LOWER_ATTRS(x) (((x) & 0xfff) << 2) +#define AP_RO (U(0x1) << 5) +#define AP_RW (U(0x0) << 5) + +#define NS (U(0x1) << 3) +#define ATTR_NON_CACHEABLE_INDEX U(0x2) +#define ATTR_DEVICE_INDEX U(0x1) +#define ATTR_IWBWA_OWBWA_NTR_INDEX U(0x0) +#define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2) /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */ -#define ATTR_NON_CACHEABLE (0x44) +#define ATTR_NON_CACHEABLE U(0x44) /* Device-nGnRE */ -#define ATTR_DEVICE (0x4) +#define ATTR_DEVICE U(0x4) /* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */ -#define ATTR_IWBWA_OWBWA_NTR (0xff) +#define ATTR_IWBWA_OWBWA_NTR U(0xff) #define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3)) -#define ATTR_INDEX_MASK 0x3 +#define ATTR_INDEX_MASK U(0x3) #define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK) /* * Flags to override default values used to program system registers while * enabling the MMU. */ -#define DISABLE_DCACHE (1 << 0) +#define DISABLE_DCACHE (U(1) << 0) /* * This flag marks the translation tables are Non-cacheable for MMU accesses. * If the flag is not specified, by default the tables are cacheable. */ -#define XLAT_TABLE_NC (1 << 1) +#define XLAT_TABLE_NC (U(1) << 1) #endif /* __XLAT_TABLES_DEFS_H__ */ diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h index e7ed2337..9db67191 100644 --- a/include/lib/xlat_tables/xlat_tables_v2.h +++ b/include/lib/xlat_tables/xlat_tables_v2.h @@ -27,14 +27,14 @@ /* * Shifts and masks to access fields of an mmap_attr_t */ -#define MT_TYPE_MASK 0x7 +#define MT_TYPE_MASK U(0x7) #define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK) /* Access permissions (RO/RW) */ -#define MT_PERM_SHIFT 3 +#define MT_PERM_SHIFT U(3) /* Security state (SECURE/NS) */ -#define MT_SEC_SHIFT 4 +#define MT_SEC_SHIFT U(4) /* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */ -#define MT_EXECUTE_SHIFT 5 +#define MT_EXECUTE_SHIFT U(5) /* All other bits are reserved */ /* @@ -52,11 +52,11 @@ typedef enum { MT_MEMORY, /* Values up to 7 are reserved to add new memory types in the future */ - MT_RO = 0 << MT_PERM_SHIFT, - MT_RW = 1 << MT_PERM_SHIFT, + MT_RO = U(0) << MT_PERM_SHIFT, + MT_RW = U(1) << MT_PERM_SHIFT, - MT_SECURE = 0 << MT_SEC_SHIFT, - MT_NS = 1 << MT_SEC_SHIFT, + MT_SECURE = U(0) << MT_SEC_SHIFT, + MT_NS = U(1) << MT_SEC_SHIFT, /* * Access permissions for instruction execution are only relevant for @@ -65,8 +65,8 @@ typedef enum { * - Device memory is always marked as execute-never. * - Read-write normal memory is always marked as execute-never. */ - MT_EXECUTE = 0 << MT_EXECUTE_SHIFT, - MT_EXECUTE_NEVER = 1 << MT_EXECUTE_SHIFT, + MT_EXECUTE = U(0) << MT_EXECUTE_SHIFT, + MT_EXECUTE_NEVER = U(1) << MT_EXECUTE_SHIFT, } mmap_attr_t; #define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE) diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S index cdc8cacb..3d5f833a 100644 --- a/lib/cpus/aarch32/cortex_a53.S +++ b/lib/cpus/aarch32/cortex_a53.S @@ -15,9 +15,9 @@ * --------------------------------------------- */ func cortex_a53_disable_smp - ldcopr16 r0, r1, CPUECTLR - bic64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A53_ECTLR + bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A53_ECTLR isb dsb sy bx lr @@ -32,9 +32,9 @@ func cortex_a53_reset_func * Enable the SMP bit. * --------------------------------------------- */ - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A53_ECTLR + orr64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A53_ECTLR isb bx lr endfunc cortex_a53_reset_func diff --git a/lib/cpus/aarch32/cortex_a57.S b/lib/cpus/aarch32/cortex_a57.S index 3fc0a6d1..ed478463 100644 --- a/lib/cpus/aarch32/cortex_a57.S +++ b/lib/cpus/aarch32/cortex_a57.S @@ -16,9 +16,9 @@ * --------------------------------------------- */ func cortex_a57_disable_smp - ldcopr16 r0, r1, CPUECTLR - bic64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A57_ECTLR + bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A57_ECTLR bx lr endfunc cortex_a57_disable_smp @@ -28,11 +28,11 @@ endfunc cortex_a57_disable_smp * --------------------------------------------- */ func cortex_a57_disable_l2_prefetch - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT - bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \ - CPUECTLR_L2_DPFTCH_DIST_MASK) - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A57_ECTLR + orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT + bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \ + CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK) + stcopr16 r0, r1, CORTEX_A57_ECTLR isb dsb ish bx lr @@ -59,9 +59,9 @@ func cortex_a57_reset_func * Enable the SMP bit. * --------------------------------------------- */ - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A57_ECTLR + orr64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A57_ECTLR isb bx lr endfunc cortex_a57_reset_func diff --git a/lib/cpus/aarch32/cortex_a72.S b/lib/cpus/aarch32/cortex_a72.S index 9d39a538..cdd83adf 100644 --- a/lib/cpus/aarch32/cortex_a72.S +++ b/lib/cpus/aarch32/cortex_a72.S @@ -15,11 +15,11 @@ * --------------------------------------------- */ func cortex_a72_disable_l2_prefetch - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT - bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \ - CPUECTLR_L2_DPFTCH_DIST_MASK) - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A72_ECTLR + orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT + bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \ + CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK) + stcopr16 r0, r1, CORTEX_A72_ECTLR isb bx lr endfunc cortex_a72_disable_l2_prefetch @@ -29,9 +29,9 @@ endfunc cortex_a72_disable_l2_prefetch * --------------------------------------------- */ func cortex_a72_disable_hw_prefetcher - ldcopr16 r0, r1, CPUACTLR - orr64_imm r0, r1, CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH - stcopr16 r0, r1, CPUACTLR + ldcopr16 r0, r1, CORTEX_A72_ACTLR + orr64_imm r0, r1, CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH + stcopr16 r0, r1, CORTEX_A72_ACTLR isb dsb ish bx lr @@ -43,9 +43,9 @@ endfunc cortex_a72_disable_hw_prefetcher * --------------------------------------------- */ func cortex_a72_disable_smp - ldcopr16 r0, r1, CPUECTLR - bic64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A72_ECTLR + bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A72_ECTLR bx lr endfunc cortex_a72_disable_smp @@ -70,9 +70,9 @@ func cortex_a72_reset_func * Enable the SMP bit. * --------------------------------------------- */ - ldcopr16 r0, r1, CPUECTLR - orr64_imm r0, r1, CPUECTLR_SMP_BIT - stcopr16 r0, r1, CPUECTLR + ldcopr16 r0, r1, CORTEX_A72_ECTLR + orr64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT + stcopr16 r0, r1, CORTEX_A72_ECTLR isb bx lr endfunc cortex_a72_reset_func diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index 77c564ae..d369c6db 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -33,9 +33,9 @@ endfunc cortex_a53_disable_dcache * --------------------------------------------- */ func cortex_a53_disable_smp - mrs x0, CPUECTLR_EL1 - bic x0, x0, #CPUECTLR_SMP_BIT - msr CPUECTLR_EL1, x0 + mrs x0, CORTEX_A53_ECTLR_EL1 + bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT + msr CORTEX_A53_ECTLR_EL1, x0 isb dsb sy ret @@ -56,10 +56,10 @@ func errata_a53_826319_wa mov x17, x30 bl check_errata_826319 cbz x0, 1f - mrs x1, L2ACTLR_EL1 - bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN - orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH - msr L2ACTLR_EL1, x1 + mrs x1, CORTEX_A53_L2ACTLR_EL1 + bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN + orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH + msr CORTEX_A53_L2ACTLR_EL1, x1 1: ret x17 endfunc errata_a53_826319_wa @@ -93,9 +93,9 @@ func a53_disable_non_temporal_hint mov x17, x30 bl check_errata_disable_non_temporal_hint cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_DTAH - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A53_ACTLR_EL1 + orr x1, x1, #CORTEX_A53_ACTLR_DTAH + msr CORTEX_A53_ACTLR_EL1, x1 1: ret x17 endfunc a53_disable_non_temporal_hint @@ -126,9 +126,9 @@ func errata_a53_855873_wa bl check_errata_855873 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_ENDCCASCI - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A53_ACTLR_EL1 + orr x1, x1, #CORTEX_A53_ACTLR_ENDCCASCI + msr CORTEX_A53_ACTLR_EL1, x1 1: ret x17 endfunc errata_a53_855873_wa @@ -168,9 +168,9 @@ func cortex_a53_reset_func * Enable the SMP bit. * --------------------------------------------- */ - mrs x0, CPUECTLR_EL1 - orr x0, x0, #CPUECTLR_SMP_BIT - msr CPUECTLR_EL1, x0 + mrs x0, CORTEX_A53_ECTLR_EL1 + orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT + msr CORTEX_A53_ECTLR_EL1, x0 isb ret x19 endfunc cortex_a53_reset_func @@ -275,10 +275,10 @@ cortex_a53_regs: /* The ascii list of register names to be reported */ func cortex_a53_cpu_reg_dump adr x6, cortex_a53_regs - mrs x8, CPUECTLR_EL1 - mrs x9, CPUMERRSR_EL1 - mrs x10, L2MERRSR_EL1 - mrs x11, CPUACTLR_EL1 + mrs x8, CORTEX_A53_ECTLR_EL1 + mrs x9, CORTEX_A53_MERRSR_EL1 + mrs x10, CORTEX_A53_L2MERRSR_EL1 + mrs x11, CORTEX_A53_ACTLR_EL1 ret endfunc cortex_a53_cpu_reg_dump diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index ffaf44e5..9e8480a3 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -29,12 +29,12 @@ endfunc cortex_a57_disable_dcache * --------------------------------------------- */ func cortex_a57_disable_l2_prefetch - mrs x0, CPUECTLR_EL1 - orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT - mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK - orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK + mrs x0, CORTEX_A57_ECTLR_EL1 + orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT + mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK + orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK bic x0, x0, x1 - msr CPUECTLR_EL1, x0 + msr CORTEX_A57_ECTLR_EL1, x0 isb dsb ish ret @@ -45,9 +45,9 @@ endfunc cortex_a57_disable_l2_prefetch * --------------------------------------------- */ func cortex_a57_disable_smp - mrs x0, CPUECTLR_EL1 - bic x0, x0, #CPUECTLR_SMP_BIT - msr CPUECTLR_EL1, x0 + mrs x0, CORTEX_A57_ECTLR_EL1 + bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT + msr CORTEX_A57_ECTLR_EL1, x0 ret endfunc cortex_a57_disable_smp @@ -78,9 +78,9 @@ func errata_a57_806969_wa mov x17, x30 bl check_errata_806969 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_806969_wa @@ -120,9 +120,9 @@ func errata_a57_813420_wa mov x17, x30 bl check_errata_813420 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_DCC_AS_DCCI - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_DCC_AS_DCCI + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_813420_wa @@ -150,9 +150,9 @@ func a57_disable_ldnp_overread mov x17, x30 bl check_errata_disable_ldnp_overread cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_DIS_OVERREAD - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_DIS_OVERREAD + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc a57_disable_ldnp_overread @@ -177,9 +177,9 @@ func errata_a57_826974_wa mov x17, x30 bl check_errata_826974 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_826974_wa @@ -204,9 +204,9 @@ func errata_a57_826977_wa mov x17, x30 bl check_errata_826977 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_826977_wa @@ -231,15 +231,16 @@ func errata_a57_828024_wa mov x17, x30 bl check_errata_828024 cbz x0, 1f - mrs x1, CPUACTLR_EL1 + mrs x1, CORTEX_A57_ACTLR_EL1 /* * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 * instructions here because the resulting bitmask doesn't fit in a * 16-bit value so it cannot be encoded in a single instruction. */ - orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA - orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING) - msr CPUACTLR_EL1, x1 + orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA + orr x1, x1, #(CORTEX_A57_ACTLR_DIS_L1_STREAMING | \ + CORTEX_A57_ACTLR_DIS_STREAMING) + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_828024_wa @@ -264,9 +265,9 @@ func errata_a57_829520_wa mov x17, x30 bl check_errata_829520 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_829520_wa @@ -291,9 +292,9 @@ func errata_a57_833471_wa mov x17, x30 bl check_errata_833471 cbz x0, 1f - mrs x1, CPUACTLR_EL1 - orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH - msr CPUACTLR_EL1, x1 + mrs x1, CORTEX_A57_ACTLR_EL1 + orr x1, x1, #CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH + msr CORTEX_A57_ACTLR_EL1, x1 1: ret x17 endfunc errata_a57_833471_wa @@ -357,9 +358,9 @@ func cortex_a57_reset_func * Enable the SMP bit. * --------------------------------------------- */ - mrs x0, CPUECTLR_EL1 - orr x0, x0, #CPUECTLR_SMP_BIT - msr CPUECTLR_EL1, x0 + mrs x0, CORTEX_A57_ECTLR_EL1 + orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT + msr CORTEX_A57_ECTLR_EL1, x0 isb ret x19 endfunc cortex_a57_reset_func @@ -503,9 +504,9 @@ cortex_a57_regs: /* The ascii list of register names to be reported */ func cortex_a57_cpu_reg_dump adr x6, cortex_a57_regs - mrs x8, CPUECTLR_EL1 - mrs x9, CPUMERRSR_EL1 - mrs x10, L2MERRSR_EL1 + mrs x8, CORTEX_A57_ECTLR_EL1 + mrs x9, CORTEX_A57_MERRSR_EL1 + mrs x10, CORTEX_A57_L2MERRSR_EL1 ret endfunc cortex_a57_cpu_reg_dump diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S index acd2d965..0307627c 100644 --- a/lib/cpus/aarch64/cortex_a72.S +++ b/lib/cpus/aarch64/cortex_a72.S @@ -27,12 +27,12 @@ endfunc cortex_a72_disable_dcache * --------------------------------------------- */ func cortex_a72_disable_l2_prefetch - mrs x0, CPUECTLR_EL1 - orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT - mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK - orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK + mrs x0, CORTEX_A72_ECTLR_EL1 + orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT + mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK + orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK bic x0, x0, x1 - msr CPUECTLR_EL1, x0 + msr CORTEX_A72_ECTLR_EL1, x0 isb ret endfunc cortex_a72_disable_l2_prefetch @@ -42,9 +42,9 @@ endfunc cortex_a72_disable_l2_prefetch * --------------------------------------------- */ func cortex_a72_disable_hw_prefetcher - mrs x0, CPUACTLR_EL1 - orr x0, x0, #CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH - msr CPUACTLR_EL1, x0 + mrs x0, CORTEX_A72_ACTLR_EL1 + orr x0, x0, #CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH + msr CORTEX_A72_ACTLR_EL1, x0 isb dsb ish ret @@ -55,9 +55,9 @@ endfunc cortex_a72_disable_hw_prefetcher * --------------------------------------------- */ func cortex_a72_disable_smp - mrs x0, CPUECTLR_EL1 - bic x0, x0, #CPUECTLR_SMP_BIT - msr CPUECTLR_EL1, x0 + mrs x0, CORTEX_A72_ECTLR_EL1 + bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT + msr CORTEX_A72_ECTLR_EL1, x0 ret endfunc cortex_a72_disable_smp @@ -82,9 +82,9 @@ func cortex_a72_reset_func * As a bare minimum enable the SMP bit. * --------------------------------------------- */ - mrs x0, CPUECTLR_EL1 - orr x0, x0, #CPUECTLR_SMP_BIT - msr CPUECTLR_EL1, x0 + mrs x0, CORTEX_A72_ECTLR_EL1 + orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT + msr CORTEX_A72_ECTLR_EL1, x0 isb ret endfunc cortex_a72_reset_func @@ -211,9 +211,9 @@ cortex_a72_regs: /* The ascii list of register names to be reported */ func cortex_a72_cpu_reg_dump adr x6, cortex_a72_regs - mrs x8, CPUECTLR_EL1 - mrs x9, CPUMERRSR_EL1 - mrs x10, L2MERRSR_EL1 + mrs x8, CORTEX_A72_ECTLR_EL1 + mrs x9, CORTEX_A72_MERRSR_EL1 + mrs x10, CORTEX_A72_L2MERRSR_EL1 ret endfunc cortex_a72_cpu_reg_dump diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c index 4d9757e0..1e1fc786 100644 --- a/lib/cpus/errata_report.c +++ b/lib/cpus/errata_report.c @@ -60,7 +60,7 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported) * Applied: INFO * Not applied: VERBOSE */ -void errata_print_msg(int status, const char *cpu, const char *id) +void errata_print_msg(unsigned int status, const char *cpu, const char *id) { /* Errata status strings */ static const char *const errata_status_str[] = { diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 763de046..f31b3238 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -332,7 +332,7 @@ void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, unsigned int node_index[]) { unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node; - int i; + unsigned int i; for (i = PSCI_CPU_PWR_LVL + 1; i <= end_lvl; i++) { *node_index++ = parent_node; @@ -901,7 +901,7 @@ void psci_print_power_domain_map(void) *****************************************************************************/ int psci_secondaries_brought_up(void) { - int idx, n_valid = 0; + unsigned int idx, n_valid = 0; for (idx = 0; idx < ARRAY_SIZE(psci_cpu_pd_nodes); idx++) { if (psci_cpu_pd_nodes[idx].mpidr != PSCI_INVALID_MPIDR) diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c index 2a6644b6..257479aa 100644 --- a/lib/psci/psci_main.c +++ b/lib/psci/psci_main.c @@ -209,7 +209,7 @@ int psci_cpu_off(void) int psci_affinity_info(u_register_t target_affinity, unsigned int lowest_affinity_level) { - unsigned int target_idx; + int target_idx; /* We dont support level higher than PSCI_CPU_PWR_LVL */ if (lowest_affinity_level > PSCI_CPU_PWR_LVL) diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c index 8be44c31..e7fb6532 100644 --- a/lib/psci/psci_off.c +++ b/lib/psci/psci_off.c @@ -19,7 +19,7 @@ ******************************************************************************/ static void psci_set_power_off_state(psci_power_state_t *state_info) { - int lvl; + unsigned int lvl; for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) state_info->pwr_domain_state[lvl] = PLAT_MAX_OFF_STATE; diff --git a/lib/xlat_tables_v2/xlat_tables_internal.c b/lib/xlat_tables_v2/xlat_tables_internal.c index 2d556e65..e1a252be 100644 --- a/lib/xlat_tables_v2/xlat_tables_internal.c +++ b/lib/xlat_tables_v2/xlat_tables_internal.c @@ -37,7 +37,7 @@ */ static int xlat_table_get_index(xlat_ctx_t *ctx, const uint64_t *table) { - for (int i = 0; i < ctx->tables_num; i++) + for (unsigned int i = 0; i < ctx->tables_num; i++) if (ctx->tables[i] == table) return i; @@ -53,7 +53,7 @@ static int xlat_table_get_index(xlat_ctx_t *ctx, const uint64_t *table) /* Returns a pointer to an empty translation table. */ static uint64_t *xlat_table_get_empty(xlat_ctx_t *ctx) { - for (int i = 0; i < ctx->tables_num; i++) + for (unsigned int i = 0; i < ctx->tables_num; i++) if (ctx->tables_mapped_regions[i] == 0) return ctx->tables[i]; @@ -203,7 +203,7 @@ static void xlat_tables_unmap_region(xlat_ctx_t *ctx, mmap_region_t *mm, const uintptr_t table_base_va, uint64_t *const table_base, const int table_entries, - const int level) + const unsigned int level) { assert(level >= ctx->base_level && level <= XLAT_TABLE_LEVEL_MAX); @@ -468,7 +468,7 @@ static uintptr_t xlat_tables_map_region(xlat_ctx_t *ctx, mmap_region_t *mm, const uintptr_t table_base_va, uint64_t *const table_base, const int table_entries, - const int level) + const unsigned int level) { assert(level >= ctx->base_level && level <= XLAT_TABLE_LEVEL_MAX); @@ -1053,14 +1053,14 @@ void init_xlation_table(xlat_ctx_t *ctx) /* All tables must be zeroed before mapping any region. */ - for (int i = 0; i < ctx->base_table_entries; i++) + for (unsigned int i = 0; i < ctx->base_table_entries; i++) ctx->base_table[i] = INVALID_DESC; - for (int j = 0; j < ctx->tables_num; j++) { + for (unsigned int j = 0; j < ctx->tables_num; j++) { #if PLAT_XLAT_TABLES_DYNAMIC ctx->tables_mapped_regions[j] = 0; #endif - for (int i = 0; i < XLAT_TABLE_ENTRIES; i++) + for (unsigned int i = 0; i < XLAT_TABLE_ENTRIES; i++) ctx->tables[j][i] = INVALID_DESC; } diff --git a/lib/xlat_tables_v2/xlat_tables_private.h b/lib/xlat_tables_v2/xlat_tables_private.h index 7b3e555e..83e0b6ea 100644 --- a/lib/xlat_tables_v2/xlat_tables_private.h +++ b/lib/xlat_tables_v2/xlat_tables_private.h @@ -52,7 +52,7 @@ typedef struct { * null entry. */ mmap_region_t *mmap; - int mmap_num; + unsigned int mmap_num; /* * Array of finer-grain translation tables. @@ -60,7 +60,7 @@ typedef struct { * contain both level-2 and level-3 entries. */ uint64_t (*tables)[XLAT_TABLE_ENTRIES]; - int tables_num; + unsigned int tables_num; /* * Keep track of how many regions are mapped in each table. The base * table can't be unmapped so it isn't needed to keep track of it. @@ -69,14 +69,14 @@ typedef struct { int *tables_mapped_regions; #endif /* PLAT_XLAT_TABLES_DYNAMIC */ - int next_table; + unsigned int next_table; /* * Base translation table. It doesn't need to have the same amount of * entries as the ones used for other levels. */ uint64_t *base_table; - int base_table_entries; + unsigned int base_table_entries; /* * Max Physical and Virtual addresses currently in use by the @@ -87,10 +87,10 @@ typedef struct { uintptr_t max_va; /* Level of the base translation table. */ - int base_level; + unsigned int base_level; /* Set to 1 when the translation tables are initialized. */ - int initialized; + unsigned int initialized; /* * Bit mask that has to be ORed to the rest of a translation table diff --git a/plat/arm/board/juno/aarch64/juno_helpers.S b/plat/arm/board/juno/aarch64/juno_helpers.S index e4113602..8d00a1a7 100644 --- a/plat/arm/board/juno/aarch64/juno_helpers.S +++ b/plat/arm/board/juno/aarch64/juno_helpers.S @@ -86,9 +86,9 @@ func JUNO_HANDLER(0) * Cortex-A57 specific settings * -------------------------------------------------------------------- */ - mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ - (L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) - msr L2CTLR_EL1, x0 + mov x0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ + (CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT)) + msr CORTEX_A57_L2CTLR_EL1, x0 1: isb ret @@ -123,8 +123,8 @@ A57: * Cortex-A57 specific settings * -------------------------------------------------------------------- */ - mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) - msr L2CTLR_EL1, x0 + mov x0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) + msr CORTEX_A57_L2CTLR_EL1, x0 isb ret endfunc JUNO_HANDLER(1) @@ -157,9 +157,9 @@ A72: * Cortex-A72 specific settings * -------------------------------------------------------------------- */ - mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ - (L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) - msr L2CTLR_EL1, x0 + mov x0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ + (CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES << CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT)) + msr CORTEX_A57_L2CTLR_EL1, x0 isb ret endfunc JUNO_HANDLER(2) diff --git a/plat/hisilicon/hikey/hisi_pwrc_sram.S b/plat/hisilicon/hikey/hisi_pwrc_sram.S index 054763bb..1fb63eaf 100644 --- a/plat/hisilicon/hikey/hisi_pwrc_sram.S +++ b/plat/hisilicon/hikey/hisi_pwrc_sram.S @@ -20,11 +20,11 @@ func pm_asm_code mov x0, 0 msr oslar_el1, x0 - mrs x0, CPUACTLR_EL1 - bic x0, x0, #(CPUACTLR_RADIS | CPUACTLR_L1RADIS) + mrs x0, CORTEX_A53_ACTLR_EL1 + bic x0, x0, #(CORTEX_A53_ACTLR_RADIS | CORTEX_A53_ACTLR_L1RADIS) orr x0, x0, #0x180000 orr x0, x0, #0xe000 - msr CPUACTLR_EL1, x0 + msr CORTEX_A53_ACTLR_EL1, x0 mrs x3, actlr_el3 orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index 1a4236fd..22389f27 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -68,18 +68,18 @@ * Enable processor retention * --------------------------- */ - mrs x0, L2ECTLR_EL1 - mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT - bic x0, x0, #L2ECTLR_RET_CTRL_MASK + mrs x0, CORTEX_A57_L2ECTLR_EL1 + mov x1, #RETENTION_ENTRY_TICKS_512 + bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK orr x0, x0, x1 - msr L2ECTLR_EL1, x0 + msr CORTEX_A57_L2ECTLR_EL1, x0 isb - mrs x0, CPUECTLR_EL1 - mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT - bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK + mrs x0, CORTEX_A57_ECTLR_EL1 + mov x1, #RETENTION_ENTRY_TICKS_512 + bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK orr x0, x0, x1 - msr CPUECTLR_EL1, x0 + msr CORTEX_A57_ECTLR_EL1, x0 isb /* ------------------------------------------------------- @@ -98,11 +98,11 @@ adr x0, tegra_enable_l2_ecc_parity_prot ldr x0, [x0] cbz x0, 1f - mrs x0, L2CTLR_EL1 - and x1, x0, #L2_ECC_PARITY_PROTECTION_BIT + mrs x0, CORTEX_A57_L2CTLR_EL1 + and x1, x0, #CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT cbnz x1, 1f - orr x0, x0, #L2_ECC_PARITY_PROTECTION_BIT - msr L2CTLR_EL1, x0 + orr x0, x0, #CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT + msr CORTEX_A57_L2CTLR_EL1, x0 isb /* -------------------------------- @@ -317,18 +317,18 @@ func tegra_secure_entrypoint * entries from the branch predictor array. * ------------------------------------------------------- */ - mrs x0, CPUACTLR_EL1 + mrs x0, CORTEX_A57_ACTLR_EL1 orr x0, x0, #1 - msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ + msr CORTEX_A57_ACTLR_EL1, x0 /* invalidate BTB and I$ together */ dsb sy isb ic iallu /* actual invalidate */ dsb sy isb - mrs x0, CPUACTLR_EL1 + mrs x0, CORTEX_A57_ACTLR_EL1 bic x0, x0, #1 - msr CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ + msr CORTEX_A57_ACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ dsb sy isb @@ -352,7 +352,7 @@ func tegra_secure_entrypoint msr oslar_el1, x0 /* os lock stays 0 across warm reset */ mov x3, #3 movz x4, #0x8000, lsl #48 - msr CPUACTLR_EL1, x4 /* turn off RCG */ + msr CORTEX_A57_ACTLR_EL1, x4 /* turn off RCG */ isb msr rmr_el3, x3 /* request warm reset */ isb diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c index 2faefc8f..9944e729 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c @@ -15,9 +15,6 @@ #include <utils.h> #include <xlat_tables_v2.h> -#define TEGRA_GPU_RESET_REG_OFFSET 0x28c -#define GPU_RESET_BIT (1 << 24) - /* Video Memory base and size (live values) */ static uint64_t video_mem_base; static uint64_t video_mem_size; @@ -135,21 +132,9 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) { uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20); uintptr_t vmem_end_new = phys_base + size_in_bytes; - uint32_t regval; unsigned long long non_overlap_area_size; /* - * The GPU is the user of the Video Memory region. In order to - * transition to the new memory region smoothly, we program the - * new base/size ONLY if the GPU is in reset mode. - */ - regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); - if ((regval & GPU_RESET_BIT) == 0) { - ERROR("GPU not in reset! Video Memory setup failed\n"); - return; - } - - /* * Setup the Memory controller to restrict CPU accesses to the Video * Memory region */ diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index e0e67d5c..92fdadcf 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -19,9 +19,6 @@ #include <utils.h> #include <xlat_tables_v2.h> -#define TEGRA_GPU_RESET_REG_OFFSET 0x30 -#define GPU_RESET_BIT (1 << 0) - /* Video Memory base and size (live values) */ static uint64_t video_mem_base; static uint64_t video_mem_size_mb; @@ -254,32 +251,12 @@ static void tegra_memctrl_reconfig_mss_clients(void) wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); - /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ - do { - val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); - } while ((val & wdata_0) != wdata_0); - - /* Wait one more time due to SW WAR for known legacy issue */ - do { - val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); - } while ((val & wdata_0) != wdata_0); - val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1); assert(val == wdata_1); wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL; tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); - /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ - do { - val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); - } while ((val & wdata_1) != wdata_1); - - /* Wait one more time due to SW WAR for known legacy issue */ - do { - val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); - } while ((val & wdata_1) != wdata_1); - #endif } @@ -623,21 +600,9 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) { uintptr_t vmem_end_old = video_mem_base + (video_mem_size_mb << 20); uintptr_t vmem_end_new = phys_base + size_in_bytes; - uint32_t regval; unsigned long long non_overlap_area_size; /* - * The GPU is the user of the Video Memory region. In order to - * transition to the new memory region smoothly, we program the - * new base/size ONLY if the GPU is in reset mode. - */ - regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); - if ((regval & GPU_RESET_BIT) == 0U) { - ERROR("GPU not in reset! Video Memory setup failed\n"); - return; - } - - /* * Setup the Memory controller to restrict CPU accesses to the Video * Memory region */ diff --git a/plat/nvidia/tegra/common/drivers/pmc/pmc.c b/plat/nvidia/tegra/common/drivers/pmc/pmc.c index 09e4c4aa..d8827e10 100644 --- a/plat/nvidia/tegra/common/drivers/pmc/pmc.c +++ b/plat/nvidia/tegra/common/drivers/pmc/pmc.c @@ -11,8 +11,10 @@ #include <pmc.h> #include <tegra_def.h> +#define RESET_ENABLE 0x10U + /* Module IDs used during power ungate procedure */ -static const int pmc_cpu_powergate_id[4] = { +static const uint32_t pmc_cpu_powergate_id[4] = { 0, /* CPU 0 */ 9, /* CPU 1 */ 10, /* CPU 2 */ @@ -23,7 +25,7 @@ static const int pmc_cpu_powergate_id[4] = { * Power ungate CPU to start the boot process. CPU reset vectors must be * populated before calling this function. ******************************************************************************/ -void tegra_pmc_cpu_on(int cpu) +void tegra_pmc_cpu_on(int32_t cpu) { uint32_t val; @@ -31,35 +33,34 @@ void tegra_pmc_cpu_on(int cpu) * Check if CPU is already power ungated */ val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); - if (val & (1 << pmc_cpu_powergate_id[cpu])) - return; - - /* - * The PMC deasserts the START bit when it starts the power - * ungate process. Loop till no power toggle is in progress. - */ - do { - val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); - } while (val & PMC_TOGGLE_START); - - /* - * Start the power ungate procedure - */ - val = pmc_cpu_powergate_id[cpu] | PMC_TOGGLE_START; - tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val); - - /* - * The PMC deasserts the START bit when it starts the power - * ungate process. Loop till powergate START bit is asserted. - */ - do { - val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); - } while (val & (1 << 8)); - - /* loop till the CPU is power ungated */ - do { - val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); - } while ((val & (1 << pmc_cpu_powergate_id[cpu])) == 0); + if ((val & (1U << pmc_cpu_powergate_id[cpu])) == 0U) { + /* + * The PMC deasserts the START bit when it starts the power + * ungate process. Loop till no power toggle is in progress. + */ + do { + val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); + } while ((val & PMC_TOGGLE_START) != 0U); + + /* + * Start the power ungate procedure + */ + val = pmc_cpu_powergate_id[cpu] | PMC_TOGGLE_START; + tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val); + + /* + * The PMC deasserts the START bit when it starts the power + * ungate process. Loop till powergate START bit is asserted. + */ + do { + val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); + } while ((val & (1U << 8)) != 0U); + + /* loop till the CPU is power ungated */ + do { + val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); + } while ((val & (1U << pmc_cpu_powergate_id[cpu])) == 0U); + } } /******************************************************************************* @@ -69,9 +70,10 @@ void tegra_pmc_cpu_setup(uint64_t reset_addr) { uint32_t val; - tegra_pmc_write_32(PMC_SECURE_SCRATCH34, (reset_addr & 0xFFFFFFFF) | 1); - val = reset_addr >> 32; - tegra_pmc_write_32(PMC_SECURE_SCRATCH35, val & 0x7FF); + tegra_pmc_write_32(PMC_SECURE_SCRATCH34, + ((uint32_t)reset_addr & 0xFFFFFFFFU) | 1U); + val = (uint32_t)(reset_addr >> 32U); + tegra_pmc_write_32(PMC_SECURE_SCRATCH35, val & 0x7FFU); } /******************************************************************************* @@ -101,7 +103,7 @@ __dead2 void tegra_pmc_system_reset(void) uint32_t reg; reg = tegra_pmc_read_32(PMC_CONFIG); - reg |= 0x10; /* restart */ + reg |= RESET_ENABLE; /* restart */ tegra_pmc_write_32(PMC_CONFIG, reg); wfi(); diff --git a/plat/nvidia/tegra/common/tegra_delay_timer.c b/plat/nvidia/tegra/common/tegra_delay_timer.c index 56c98516..3bd2b0e2 100644 --- a/plat/nvidia/tegra/common/tegra_delay_timer.c +++ b/plat/nvidia/tegra/common/tegra_delay_timer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,23 +7,24 @@ #include <delay_timer.h> #include <mmio.h> #include <tegra_def.h> +#include <tegra_private.h> static uint32_t tegra_timerus_get_value(void) { return mmio_read_32(TEGRA_TMRUS_BASE); } -static const timer_ops_t tegra_timer_ops = { - .get_timer_value = tegra_timerus_get_value, - .clk_mult = 1, - .clk_div = 1, -}; - /* * Initialise the on-chip free rolling us counter as the delay * timer. */ void tegra_delay_timer_init(void) { + static const timer_ops_t tegra_timer_ops = { + .get_timer_value = tegra_timerus_get_value, + .clk_mult = 1, + .clk_div = 1, + }; + timer_init(&tegra_timer_ops); } diff --git a/plat/nvidia/tegra/common/tegra_fiq_glue.c b/plat/nvidia/tegra/common/tegra_fiq_glue.c index c2bfb1c5..2f439587 100644 --- a/plat/nvidia/tegra/common/tegra_fiq_glue.c +++ b/plat/nvidia/tegra/common/tegra_fiq_glue.c @@ -18,13 +18,13 @@ #include <tegra_def.h> #include <tegra_private.h> -DEFINE_BAKERY_LOCK(tegra_fiq_lock); +static DEFINE_BAKERY_LOCK(tegra_fiq_lock); /******************************************************************************* * Static variables ******************************************************************************/ static uint64_t ns_fiq_handler_addr; -static unsigned int fiq_handler_active; +static uint32_t fiq_handler_active; static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT]; /******************************************************************************* @@ -37,7 +37,7 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id, { cpu_context_t *ctx = cm_get_context(NON_SECURE); el3_state_t *el3state_ctx = get_el3state_ctx(ctx); - int cpu = plat_my_core_pos(); + uint32_t cpu = plat_my_core_pos(); uint32_t irq; bakery_lock_get(&tegra_fiq_lock); @@ -52,22 +52,23 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id, * Save elr_el3 and spsr_el3 from the saved context, and overwrite * the context with the NS fiq_handler_addr and SPSR value. */ - fiq_state[cpu].elr_el3 = read_ctx_reg(el3state_ctx, CTX_ELR_EL3); - fiq_state[cpu].spsr_el3 = read_ctx_reg(el3state_ctx, CTX_SPSR_EL3); + fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); + fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); /* * Set the new ELR to continue execution in the NS world using the * FIQ handler registered earlier. */ assert(ns_fiq_handler_addr); - write_ctx_reg(el3state_ctx, CTX_ELR_EL3, ns_fiq_handler_addr); + write_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3), (ns_fiq_handler_addr)); /* * Mark this interrupt as complete to avoid a FIQ storm. */ irq = plat_ic_acknowledge_interrupt(); - if (irq < 1022) + if (irq < 1022U) { plat_ic_end_of_interrupt(irq); + } bakery_lock_release(&tegra_fiq_lock); @@ -79,27 +80,27 @@ static uint64_t tegra_fiq_interrupt_handler(uint32_t id, ******************************************************************************/ void tegra_fiq_handler_setup(void) { - uint64_t flags; - int rc; + uint32_t flags; + int32_t rc; /* return if already registered */ - if (fiq_handler_active) - return; - - /* - * Register an interrupt handler for FIQ interrupts generated for - * NS interrupt sources - */ - flags = 0; - set_interrupt_rm_flag(flags, NON_SECURE); - rc = register_interrupt_type_handler(INTR_TYPE_EL3, - tegra_fiq_interrupt_handler, - flags); - if (rc) - panic(); - - /* handler is now active */ - fiq_handler_active = 1; + if (fiq_handler_active == 0U) { + /* + * Register an interrupt handler for FIQ interrupts generated for + * NS interrupt sources + */ + flags = 0U; + set_interrupt_rm_flag((flags), (NON_SECURE)); + rc = register_interrupt_type_handler(INTR_TYPE_EL3, + tegra_fiq_interrupt_handler, + flags); + if (rc != 0) { + panic(); + } + + /* handler is now active */ + fiq_handler_active = 1; + } } /******************************************************************************* @@ -113,26 +114,26 @@ void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint) /******************************************************************************* * Handler to return the NS EL1/EL0 CPU context ******************************************************************************/ -int tegra_fiq_get_intr_context(void) +int32_t tegra_fiq_get_intr_context(void) { cpu_context_t *ctx = cm_get_context(NON_SECURE); gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx); - el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx); - int cpu = plat_my_core_pos(); + const el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx); + uint32_t cpu = plat_my_core_pos(); uint64_t val; /* * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so * that el3_exit() sends these values back to the NS world. */ - write_ctx_reg(gpregs_ctx, CTX_GPREG_X0, fiq_state[cpu].elr_el3); - write_ctx_reg(gpregs_ctx, CTX_GPREG_X1, fiq_state[cpu].spsr_el3); + write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); + write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3)); - val = read_ctx_reg(gpregs_ctx, CTX_GPREG_SP_EL0); - write_ctx_reg(gpregs_ctx, CTX_GPREG_X2, val); + val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0)); + write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); - val = read_ctx_reg(el1state_ctx, CTX_SP_EL1); - write_ctx_reg(gpregs_ctx, CTX_GPREG_X3, val); + val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1)); + write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val)); return 0; } diff --git a/plat/nvidia/tegra/common/tegra_gic.c b/plat/nvidia/tegra/common/tegra_gic.c index 4a84eec3..ae56d55a 100644 --- a/plat/nvidia/tegra/common/tegra_gic.c +++ b/plat/nvidia/tegra/common/tegra_gic.c @@ -24,7 +24,7 @@ (GIC_HIGHEST_NS_PRIORITY << 24)) static const irq_sec_cfg_t *g_irq_sec_ptr; -static unsigned int g_num_irqs; +static uint32_t g_num_irqs; /******************************************************************************* * Place the cpu interface in a state where it can never make a cpu exit wfi as @@ -32,7 +32,7 @@ static unsigned int g_num_irqs; ******************************************************************************/ void tegra_gic_cpuif_deactivate(void) { - unsigned int val; + uint32_t val; /* Disable secure, non-secure interrupts and disable their bypass */ val = gicc_read_ctlr(TEGRA_GICC_BASE); @@ -46,9 +46,9 @@ void tegra_gic_cpuif_deactivate(void) * Enable secure interrupts and set the priority mask register to allow all * interrupts to trickle in. ******************************************************************************/ -static void tegra_gic_cpuif_setup(unsigned int gicc_base) +static void tegra_gic_cpuif_setup(uint32_t gicc_base) { - unsigned int val; + uint32_t val; val = ENABLE_GRP0 | ENABLE_GRP1 | FIQ_EN | FIQ_BYP_DIS_GRP0; val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; @@ -61,14 +61,14 @@ static void tegra_gic_cpuif_setup(unsigned int gicc_base) * Per cpu gic distributor setup which will be done by all cpus after a cold * boot/hotplug. This marks out the secure interrupts & enables them. ******************************************************************************/ -static void tegra_gic_pcpu_distif_setup(unsigned int gicd_base) +static void tegra_gic_pcpu_distif_setup(uint32_t gicd_base) { - unsigned int index, sec_ppi_sgi_mask = 0; + uint32_t index, sec_ppi_sgi_mask = 0; - assert(gicd_base); + assert(gicd_base != 0U); /* Setup PPI priorities doing four at a time */ - for (index = 0; index < 32; index += 4) { + for (index = 0U; index < 32U; index += 4U) { gicd_write_ipriorityr(gicd_base, index, GICD_IPRIORITYR_DEF_VAL); } @@ -87,9 +87,9 @@ static void tegra_gic_pcpu_distif_setup(unsigned int gicd_base) * cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them. * It then enables the secure GIC distributor interface. ******************************************************************************/ -static void tegra_gic_distif_setup(unsigned int gicd_base) +static void tegra_gic_distif_setup(uint32_t gicd_base) { - unsigned int index, num_ints, irq_num; + uint32_t index, num_ints, irq_num; uint8_t target_cpus; uint32_t val; @@ -99,22 +99,23 @@ static void tegra_gic_distif_setup(unsigned int gicd_base) * number of IT_LINES */ num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; - num_ints = (num_ints + 1) << 5; - for (index = MIN_SPI_ID; index < num_ints; index += 32) - gicd_write_igroupr(gicd_base, index, ~0); + num_ints = (num_ints + 1U) << 5; + for (index = MIN_SPI_ID; index < num_ints; index += 32U) { + gicd_write_igroupr(gicd_base, index, 0xFFFFFFFFU); + } /* Setup SPI priorities doing four at a time */ - for (index = MIN_SPI_ID; index < num_ints; index += 4) { + for (index = MIN_SPI_ID; index < num_ints; index += 4U) { gicd_write_ipriorityr(gicd_base, index, GICD_IPRIORITYR_DEF_VAL); } /* Configure SPI secure interrupts now */ - if (g_irq_sec_ptr) { + if (g_irq_sec_ptr != NULL) { - for (index = 0; index < g_num_irqs; index++) { - irq_num = (g_irq_sec_ptr + index)->irq; - target_cpus = (g_irq_sec_ptr + index)->target_cpus; + for (index = 0U; index < g_num_irqs; index++) { + irq_num = g_irq_sec_ptr[index].irq; + target_cpus = (uint8_t)g_irq_sec_ptr[index].target_cpus; if (irq_num >= MIN_SPI_ID) { @@ -122,14 +123,15 @@ static void tegra_gic_distif_setup(unsigned int gicd_base) gicd_clr_igroupr(gicd_base, irq_num); /* Configure SPI priority */ - mmio_write_8(gicd_base + GICD_IPRIORITYR + - irq_num, + mmio_write_8((uint64_t)gicd_base + + (uint64_t)GICD_IPRIORITYR + + (uint64_t)irq_num, GIC_HIGHEST_SEC_PRIORITY & GIC_PRI_MASK); /* Configure as level triggered */ val = gicd_read_icfgr(gicd_base, irq_num); - val |= (3 << ((irq_num & 0xF) << 1)); + val |= (3U << ((irq_num & 0xFU) << 1U)); gicd_write_icfgr(gicd_base, irq_num, val); /* Route SPI to the target CPUs */ @@ -153,7 +155,7 @@ static void tegra_gic_distif_setup(unsigned int gicd_base) gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1); } -void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, unsigned int num_irqs) +void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs) { g_irq_sec_ptr = irq_sec_ptr; g_num_irqs = num_irqs; @@ -172,12 +174,12 @@ void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, unsigned int num_irqs) * SCR_EL3 to control its routing to EL3. The interrupt line is represented as * the bit position of the IRQ or FIQ bit in the SCR_EL3. ******************************************************************************/ -uint32_t tegra_gic_interrupt_type_to_line(uint32_t type, +static uint32_t tegra_gic_interrupt_type_to_line(uint32_t type, uint32_t security_state) { - assert(type == INTR_TYPE_S_EL1 || - type == INTR_TYPE_EL3 || - type == INTR_TYPE_NS); + assert((type == INTR_TYPE_S_EL1) || + (type == INTR_TYPE_EL3) || + (type == INTR_TYPE_NS)); assert(sec_state_is_valid(security_state)); @@ -199,25 +201,29 @@ uint32_t tegra_gic_interrupt_type_to_line(uint32_t type, * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no * interrupt pending. ******************************************************************************/ -uint32_t tegra_gic_get_pending_interrupt_type(void) +static uint32_t tegra_gic_get_pending_interrupt_type(void) { uint32_t id; - unsigned int index; + uint32_t index; + uint32_t ret = INTR_TYPE_NS; id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK; /* get the interrupt type */ - if (id < 1022) { - for (index = 0; index < g_num_irqs; index++) { - if (id == (g_irq_sec_ptr + index)->irq) - return (g_irq_sec_ptr + index)->type; + if (id < 1022U) { + for (index = 0U; index < g_num_irqs; index++) { + if (id == g_irq_sec_ptr[index].irq) { + ret = g_irq_sec_ptr[index].type; + break; + } + } + } else { + if (id == GIC_SPURIOUS_INTERRUPT) { + ret = INTR_TYPE_INVAL; } } - if (id == GIC_SPURIOUS_INTERRUPT) - return INTR_TYPE_INVAL; - - return INTR_TYPE_NS; + return ret; } /******************************************************************************* @@ -225,30 +231,32 @@ uint32_t tegra_gic_get_pending_interrupt_type(void) * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no * interrupt pending. ******************************************************************************/ -uint32_t tegra_gic_get_pending_interrupt_id(void) +static uint32_t tegra_gic_get_pending_interrupt_id(void) { - uint32_t id; + uint32_t id, ret; id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK; - if (id < 1022) - return id; - - if (id == 1023) - return INTR_ID_UNAVAILABLE; + if (id < 1022UL) { + ret = id; + } else if (id == 1023UL) { + ret = 0xFFFFFFFFUL; /* INTR_ID_UNAVAILABLE */ + } else { + /* + * Find out which non-secure interrupt it is under the assumption that + * the GICC_CTLR.AckCtl bit is 0. + */ + ret = gicc_read_ahppir(TEGRA_GICC_BASE) & INT_ID_MASK; + } - /* - * Find out which non-secure interrupt it is under the assumption that - * the GICC_CTLR.AckCtl bit is 0. - */ - return gicc_read_ahppir(TEGRA_GICC_BASE) & INT_ID_MASK; + return ret; } /******************************************************************************* * This functions reads the GIC cpu interface Interrupt Acknowledge register * to start handling the pending interrupt. It returns the contents of the IAR. ******************************************************************************/ -uint32_t tegra_gic_acknowledge_interrupt(void) +static uint32_t tegra_gic_acknowledge_interrupt(void) { return gicc_read_IAR(TEGRA_GICC_BASE); } @@ -257,7 +265,7 @@ uint32_t tegra_gic_acknowledge_interrupt(void) * This functions writes the GIC cpu interface End Of Interrupt register with * the passed value to finish handling the active interrupt ******************************************************************************/ -void tegra_gic_end_of_interrupt(uint32_t id) +static void tegra_gic_end_of_interrupt(uint32_t id) { gicc_write_EOIR(TEGRA_GICC_BASE, id); } @@ -267,22 +275,25 @@ void tegra_gic_end_of_interrupt(uint32_t id) * this interrupt has been configured under by the interrupt controller i.e. * group0 or group1. ******************************************************************************/ -uint32_t tegra_gic_get_interrupt_type(uint32_t id) +static uint32_t tegra_gic_get_interrupt_type(uint32_t id) { uint32_t group; - unsigned int index; + uint32_t index; + uint32_t ret = INTR_TYPE_NS; group = gicd_get_igroupr(TEGRA_GICD_BASE, id); /* get the interrupt type */ if (group == GRP0) { - for (index = 0; index < g_num_irqs; index++) { - if (id == (g_irq_sec_ptr + index)->irq) - return (g_irq_sec_ptr + index)->type; + for (index = 0U; index < g_num_irqs; index++) { + if (id == g_irq_sec_ptr[index].irq) { + ret = g_irq_sec_ptr[index].type; + break; + } } } - return INTR_TYPE_NS; + return ret; } #else diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index 94450191..6f841ef0 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -107,7 +107,7 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state) { /* all affinities use system suspend state id */ - for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) + for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN; } diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/common/tegra_sip_calls.c index 9b0a36c8..dcad21e0 100644 --- a/plat/nvidia/tegra/common/tegra_sip_calls.c +++ b/plat/nvidia/tegra/common/tegra_sip_calls.c @@ -11,6 +11,7 @@ #include <debug.h> #include <errno.h> #include <memctrl.h> +#include <mmio.h> #include <runtime_svc.h> #include <tegra_private.h> #include <tegra_platform.h> @@ -57,6 +58,7 @@ uint64_t tegra_sip_handler(uint32_t smc_fid, void *handle, uint64_t flags) { + uint32_t regval; int err; /* Check if this is a SoC specific SiP */ @@ -87,6 +89,18 @@ uint64_t tegra_sip_handler(uint32_t smc_fid, SMC_RET1(handle, -ENOTSUP); } + /* + * The GPU is the user of the Video Memory region. In order to + * transition to the new memory region smoothly, we program the + * new base/size ONLY if the GPU is in reset mode. + */ + regval = mmio_read_32(TEGRA_CAR_RESET_BASE + + TEGRA_GPU_RESET_REG_OFFSET); + if ((regval & GPU_RESET_BIT) == 0U) { + ERROR("GPU not in reset! Video Memory setup failed\n"); + SMC_RET1(handle, -ENOTSUP); + } + /* new video memory carveout settings */ tegra_memctrl_videomem_setup(x1, x2); diff --git a/plat/nvidia/tegra/include/drivers/mce.h b/plat/nvidia/tegra/include/drivers/mce.h index 232f2633..c7867a50 100644 --- a/plat/nvidia/tegra/include/drivers/mce.h +++ b/plat/nvidia/tegra/include/drivers/mce.h @@ -63,14 +63,14 @@ typedef struct mce_cstate_info { } mce_cstate_info_t; /* public interfaces */ -int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, +int mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, uint64_t arg2); int mce_update_reset_vector(void); int mce_update_gsc_videomem(void); int mce_update_gsc_tzdram(void); int mce_update_gsc_tzram(void); __dead2 void mce_enter_ccplex_state(uint32_t state_idx); -void mce_update_cstate_info(mce_cstate_info_t *cstate); +void mce_update_cstate_info(const mce_cstate_info_t *cstate); void mce_verify_firmware_version(void); #endif /* __MCE_H__ */ diff --git a/plat/nvidia/tegra/include/drivers/pmc.h b/plat/nvidia/tegra/include/drivers/pmc.h index 7bf3f813..ea9392b6 100644 --- a/plat/nvidia/tegra/include/drivers/pmc.h +++ b/plat/nvidia/tegra/include/drivers/pmc.h @@ -9,20 +9,21 @@ #include <mmio.h> #include <tegra_def.h> +#include <utils_def.h> -#define PMC_CONFIG 0x0U -#define PMC_PWRGATE_STATUS 0x38U -#define PMC_PWRGATE_TOGGLE 0x30U -#define PMC_TOGGLE_START 0x100U -#define PMC_SCRATCH39 0x138U -#define PMC_SECURE_DISABLE2 0x2c4U -#define PMC_SECURE_DISABLE2_WRITE22_ON (1U << 28) -#define PMC_SECURE_SCRATCH22 0x338U -#define PMC_SECURE_DISABLE3 0x2d8U -#define PMC_SECURE_DISABLE3_WRITE34_ON (1U << 20) -#define PMC_SECURE_DISABLE3_WRITE35_ON (1U << 22) -#define PMC_SECURE_SCRATCH34 0x368U -#define PMC_SECURE_SCRATCH35 0x36cU +#define PMC_CONFIG U(0x0) +#define PMC_PWRGATE_STATUS U(0x38) +#define PMC_PWRGATE_TOGGLE U(0x30) +#define PMC_TOGGLE_START U(0x100) +#define PMC_SCRATCH39 U(0x138) +#define PMC_SECURE_DISABLE2 U(0x2c4) +#define PMC_SECURE_DISABLE2_WRITE22_ON (U(1) << 28) +#define PMC_SECURE_SCRATCH22 U(0x338) +#define PMC_SECURE_DISABLE3 U(0x2d8) +#define PMC_SECURE_DISABLE3_WRITE34_ON (U(1) << 20) +#define PMC_SECURE_DISABLE3_WRITE35_ON (U(1) << 22) +#define PMC_SECURE_SCRATCH34 U(0x368) +#define PMC_SECURE_SCRATCH35 U(0x36c) static inline uint32_t tegra_pmc_read_32(uint32_t off) { @@ -36,7 +37,7 @@ static inline void tegra_pmc_write_32(uint32_t off, uint32_t val) void tegra_pmc_cpu_setup(uint64_t reset_addr); void tegra_pmc_lock_cpu_vectors(void); -void tegra_pmc_cpu_on(int cpu); +void tegra_pmc_cpu_on(int32_t cpu); __dead2 void tegra_pmc_system_reset(void); #endif /* __PMC_H__ */ diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index 41d771c0..4894442a 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -10,6 +10,7 @@ #include <arch.h> #include <common_def.h> #include <tegra_def.h> +#include <utils_def.h> /******************************************************************************* * Generic platform constants @@ -17,10 +18,10 @@ /* Size of cacheable stacks */ #ifdef IMAGE_BL31 -#define PLATFORM_STACK_SIZE 0x400 +#define PLATFORM_STACK_SIZE U(0x400) #endif -#define TEGRA_PRIMARY_CPU 0x0 +#define TEGRA_PRIMARY_CPU U(0x0) #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ @@ -31,20 +32,20 @@ /******************************************************************************* * Platform console related constants ******************************************************************************/ -#define TEGRA_CONSOLE_BAUDRATE 115200 -#define TEGRA_BOOT_UART_CLK_IN_HZ 408000000 +#define TEGRA_CONSOLE_BAUDRATE U(115200) +#define TEGRA_BOOT_UART_CLK_IN_HZ U(408000000) /******************************************************************************* * Platform memory map related constants ******************************************************************************/ /* Size of trusted dram */ -#define TZDRAM_SIZE 0x00400000 +#define TZDRAM_SIZE U(0x00400000) #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) /******************************************************************************* * BL31 specific defines. ******************************************************************************/ -#define BL31_SIZE 0x40000 +#define BL31_SIZE U(0x40000) #define BL31_BASE TZDRAM_BASE #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) @@ -53,8 +54,8 @@ /******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ -#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 35) -#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 35) +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) /******************************************************************************* * Some data must be aligned on the biggest cache line size in the platform. @@ -62,6 +63,6 @@ * integrated and external caches. ******************************************************************************/ #define CACHE_WRITEBACK_SHIFT 6 -#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) +#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h index fcb074a7..ae00fb5c 100644 --- a/plat/nvidia/tegra/include/t132/tegra_def.h +++ b/plat/nvidia/tegra/include/t132/tegra_def.h @@ -7,11 +7,13 @@ #ifndef __TEGRA_DEF_H__ #define __TEGRA_DEF_H__ +#include <utils_def.h> + /******************************************************************************* * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` * call as the `state-id` field in the 'power state' parameter. ******************************************************************************/ -#define PSTATE_ID_SOC_POWERDN 0xD +#define PSTATE_ID_SOC_POWERDN U(0xD) /******************************************************************************* * Platform power states (used by PSCI framework) @@ -19,80 +21,82 @@ * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID ******************************************************************************/ -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) /******************************************************************************* * GIC memory map ******************************************************************************/ -#define TEGRA_GICD_BASE 0x50041000 -#define TEGRA_GICC_BASE 0x50042000 +#define TEGRA_GICD_BASE U(0x50041000) +#define TEGRA_GICC_BASE U(0x50042000) /******************************************************************************* * Tegra micro-seconds timer constants ******************************************************************************/ -#define TEGRA_TMRUS_BASE 0x60005010 -#define TEGRA_TMRUS_SIZE 0x1000 +#define TEGRA_TMRUS_BASE U(0x60005010) +#define TEGRA_TMRUS_SIZE U(0x1000) /******************************************************************************* * Tegra Clock and Reset Controller constants ******************************************************************************/ -#define TEGRA_CAR_RESET_BASE 0x60006000 +#define TEGRA_CAR_RESET_BASE U(0x60006000) +#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) +#define GPU_RESET_BIT (U(1) << 24) /******************************************************************************* * Tegra Flow Controller constants ******************************************************************************/ -#define TEGRA_FLOWCTRL_BASE 0x60007000 +#define TEGRA_FLOWCTRL_BASE U(0x60007000) /******************************************************************************* * Tegra Secure Boot Controller constants ******************************************************************************/ -#define TEGRA_SB_BASE 0x6000C200 +#define TEGRA_SB_BASE U(0x6000C200) /******************************************************************************* * Tegra Exception Vectors constants ******************************************************************************/ -#define TEGRA_EVP_BASE 0x6000F000 +#define TEGRA_EVP_BASE U(0x6000F000) /******************************************************************************* * Tegra Miscellaneous register constants ******************************************************************************/ -#define TEGRA_MISC_BASE 0x70000000 -#define HARDWARE_REVISION_OFFSET 0x804 +#define TEGRA_MISC_BASE U(0x70000000) +#define HARDWARE_REVISION_OFFSET U(0x804) /******************************************************************************* * Tegra UART controller base addresses ******************************************************************************/ -#define TEGRA_UARTA_BASE 0x70006000 -#define TEGRA_UARTB_BASE 0x70006040 -#define TEGRA_UARTC_BASE 0x70006200 -#define TEGRA_UARTD_BASE 0x70006300 -#define TEGRA_UARTE_BASE 0x70006400 +#define TEGRA_UARTA_BASE U(0x70006000) +#define TEGRA_UARTB_BASE U(0x70006040) +#define TEGRA_UARTC_BASE U(0x70006200) +#define TEGRA_UARTD_BASE U(0x70006300) +#define TEGRA_UARTE_BASE U(0x70006400) /******************************************************************************* * Tegra Power Mgmt Controller constants ******************************************************************************/ -#define TEGRA_PMC_BASE 0x7000E400 +#define TEGRA_PMC_BASE U(0x7000E400) /******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/ -#define TEGRA_MC_BASE 0x70019000 +#define TEGRA_MC_BASE U(0x70019000) /* TZDRAM carveout configuration registers */ -#define MC_SECURITY_CFG0_0 0x70 -#define MC_SECURITY_CFG1_0 0x74 -#define MC_SECURITY_CFG3_0 0x9BC +#define MC_SECURITY_CFG0_0 U(0x70) +#define MC_SECURITY_CFG1_0 U(0x74) +#define MC_SECURITY_CFG3_0 U(0x9BC) /* Video Memory carveout configuration registers */ -#define MC_VIDEO_PROTECT_BASE_HI 0x978 -#define MC_VIDEO_PROTECT_BASE_LO 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c +#define MC_VIDEO_PROTECT_BASE_HI U(0x978) +#define MC_VIDEO_PROTECT_BASE_LO U(0x648) +#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) /******************************************************************************* * Tegra TZRAM constants ******************************************************************************/ -#define TEGRA_TZRAM_BASE 0x7C010000 -#define TEGRA_TZRAM_SIZE 0x10000 +#define TEGRA_TZRAM_BASE U(0x7C010000) +#define TEGRA_TZRAM_SIZE U(0x10000) #endif /* __TEGRA_DEF_H__ */ diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index 106f8f66..d0331472 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -7,6 +7,8 @@ #ifndef __TEGRA_DEF_H__ #define __TEGRA_DEF_H__ +#include <utils_def.h> + /******************************************************************************* * MCE apertures used by the ARI interface * @@ -17,34 +19,34 @@ * Aperture 4 - Cpu4 (Denver15) * Aperture 5 - Cpu5 (Denver15) ******************************************************************************/ -#define MCE_ARI_APERTURE_0_OFFSET 0x0 -#define MCE_ARI_APERTURE_1_OFFSET 0x10000 -#define MCE_ARI_APERTURE_2_OFFSET 0x20000 -#define MCE_ARI_APERTURE_3_OFFSET 0x30000 -#define MCE_ARI_APERTURE_4_OFFSET 0x40000 -#define MCE_ARI_APERTURE_5_OFFSET 0x50000 +#define MCE_ARI_APERTURE_0_OFFSET U(0x0) +#define MCE_ARI_APERTURE_1_OFFSET U(0x10000) +#define MCE_ARI_APERTURE_2_OFFSET U(0x20000) +#define MCE_ARI_APERTURE_3_OFFSET U(0x30000) +#define MCE_ARI_APERTURE_4_OFFSET U(0x40000) +#define MCE_ARI_APERTURE_5_OFFSET U(0x50000) #define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET /* number of apertures */ -#define MCE_ARI_APERTURES_MAX 6 +#define MCE_ARI_APERTURES_MAX U(6) /* each ARI aperture is 64KB */ -#define MCE_ARI_APERTURE_SIZE 0x10000 +#define MCE_ARI_APERTURE_SIZE U(0x10000) /******************************************************************************* * CPU core id macros for the MCE_ONLINE_CORE ARI ******************************************************************************/ -#define MCE_CORE_ID_MAX 8 -#define MCE_CORE_ID_MASK 0x7 +#define MCE_CORE_ID_MAX U(8) +#define MCE_CORE_ID_MASK U(0x7) /******************************************************************************* * These values are used by the PSCI implementation during the `CPU_SUSPEND` * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' * parameter. ******************************************************************************/ -#define PSTATE_ID_CORE_IDLE 6 -#define PSTATE_ID_CORE_POWERDN 7 -#define PSTATE_ID_SOC_POWERDN 2 +#define PSTATE_ID_CORE_IDLE U(6) +#define PSTATE_ID_CORE_POWERDN U(7) +#define PSTATE_ID_SOC_POWERDN U(2) /******************************************************************************* * Platform power states (used by PSCI framework) @@ -52,209 +54,197 @@ * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID ******************************************************************************/ -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE 8 - -/******************************************************************************* - * Implementation defined ACTLR_EL3 bit definitions - ******************************************************************************/ -#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) -#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) -#define ACTLR_EL3_L2CTLR_BIT (1 << 4) -#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) -#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) -#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ - ACTLR_EL3_L2ECTLR_BIT | \ - ACTLR_EL3_L2CTLR_BIT | \ - ACTLR_EL3_CPUECTLR_BIT | \ - ACTLR_EL3_CPUACTLR_BIT) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE U(8) /******************************************************************************* * Secure IRQ definitions ******************************************************************************/ -#define TEGRA186_TOP_WDT_IRQ 49 -#define TEGRA186_AON_WDT_IRQ 50 +#define TEGRA186_TOP_WDT_IRQ U(49) +#define TEGRA186_AON_WDT_IRQ U(50) -#define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ +#define TEGRA186_SEC_IRQ_TARGET_MASK U(0xF3) /* 4 A57 - 2 Denver */ /******************************************************************************* * Tegra Miscellanous register constants ******************************************************************************/ -#define TEGRA_MISC_BASE 0x00100000 -#define HARDWARE_REVISION_OFFSET 0x4 +#define TEGRA_MISC_BASE U(0x00100000) +#define HARDWARE_REVISION_OFFSET U(0x4) -#define MISCREG_PFCFG 0x200C +#define MISCREG_PFCFG U(0x200C) /******************************************************************************* * Tegra TSA Controller constants ******************************************************************************/ -#define TEGRA_TSA_BASE 0x02400000 +#define TEGRA_TSA_BASE U(0x02400000) /******************************************************************************* * TSA configuration registers ******************************************************************************/ -#define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010 -#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038 -#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010 -#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008 -#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008 -#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100 -#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018 -#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018 -#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028 -#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018 -#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008 -#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018 -#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028 -#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038 -#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008 -#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 -#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018 -#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 - -#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) -#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) +#define TSA_CONFIG_STATIC0_CSW_SESWR U(0x4010) +#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_ETRW U(0x4038) +#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB U(0x5010) +#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_AXISW U(0x7008) +#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_HDAW U(0xA008) +#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET U(0x100) +#define TSA_CONFIG_STATIC0_CSW_AONDMAW U(0xB018) +#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_SCEDMAW U(0xD018) +#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW U(0xD028) +#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_APEDMAW U(0x12018) +#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_UFSHCW U(0x13008) +#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_AFIW U(0x13018) +#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_SATAW U(0x13028) +#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_EQOSW U(0x13038) +#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW U(0x15008) +#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET U(0x1100) +#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW U(0x15018) +#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET U(0x1100) + +#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (U(0x3) << 11) +#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (U(0) << 11) /******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/ -#define TEGRA_MC_STREAMID_BASE 0x02C00000 -#define TEGRA_MC_BASE 0x02C10000 +#define TEGRA_MC_STREAMID_BASE U(0x02C00000) +#define TEGRA_MC_BASE U(0x02C10000) /* General Security Carveout register macros */ -#define MC_GSC_CONFIG_REGS_SIZE 0x40UL -#define MC_GSC_LOCK_CFG_SETTINGS_BIT (1UL << 1) -#define MC_GSC_ENABLE_TZ_LOCK_BIT (1UL << 0) -#define MC_GSC_SIZE_RANGE_4KB_SHIFT 27UL -#define MC_GSC_BASE_LO_SHIFT 12UL -#define MC_GSC_BASE_LO_MASK 0xFFFFFUL -#define MC_GSC_BASE_HI_SHIFT 0UL -#define MC_GSC_BASE_HI_MASK 3UL +#define MC_GSC_CONFIG_REGS_SIZE U(0x40) +#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1) +#define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0) +#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27) +#define MC_GSC_BASE_LO_SHIFT U(12) +#define MC_GSC_BASE_LO_MASK U(0xFFFFF) +#define MC_GSC_BASE_HI_SHIFT U(0) +#define MC_GSC_BASE_HI_MASK U(3) /* TZDRAM carveout configuration registers */ -#define MC_SECURITY_CFG0_0 0x70 -#define MC_SECURITY_CFG1_0 0x74 -#define MC_SECURITY_CFG3_0 0x9BC +#define MC_SECURITY_CFG0_0 U(0x70) +#define MC_SECURITY_CFG1_0 U(0x74) +#define MC_SECURITY_CFG3_0 U(0x9BC) /* Video Memory carveout configuration registers */ -#define MC_VIDEO_PROTECT_BASE_HI 0x978 -#define MC_VIDEO_PROTECT_BASE_LO 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64C +#define MC_VIDEO_PROTECT_BASE_HI U(0x978) +#define MC_VIDEO_PROTECT_BASE_LO U(0x648) +#define MC_VIDEO_PROTECT_SIZE_MB U(0x64C) /* * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the * non-overlapping Video memory region */ -#define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 -#define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 -#define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 -#define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC -#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 +#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0) +#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4) +#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8) +#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC) +#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0) /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ -#define MC_TZRAM_CARVEOUT_CFG 0x2190 -#define MC_TZRAM_BASE_LO 0x2194 -#define MC_TZRAM_BASE_HI 0x2198 -#define MC_TZRAM_SIZE 0x219C -#define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 +#define MC_TZRAM_CARVEOUT_CFG U(0x2190) +#define MC_TZRAM_BASE_LO U(0x2194) +#define MC_TZRAM_BASE_HI U(0x2198) +#define MC_TZRAM_SIZE U(0x219C) +#define MC_TZRAM_CLIENT_ACCESS_CFG0 U(0x21A0) /******************************************************************************* * Tegra UART Controller constants ******************************************************************************/ -#define TEGRA_UARTA_BASE 0x03100000 -#define TEGRA_UARTB_BASE 0x03110000 -#define TEGRA_UARTC_BASE 0x0C280000 -#define TEGRA_UARTD_BASE 0x03130000 -#define TEGRA_UARTE_BASE 0x03140000 -#define TEGRA_UARTF_BASE 0x03150000 -#define TEGRA_UARTG_BASE 0x0C290000 +#define TEGRA_UARTA_BASE U(0x03100000) +#define TEGRA_UARTB_BASE U(0x03110000) +#define TEGRA_UARTC_BASE U(0x0C280000) +#define TEGRA_UARTD_BASE U(0x03130000) +#define TEGRA_UARTE_BASE U(0x03140000) +#define TEGRA_UARTF_BASE U(0x03150000) +#define TEGRA_UARTG_BASE U(0x0C290000) /******************************************************************************* * Tegra Fuse Controller related constants ******************************************************************************/ -#define TEGRA_FUSE_BASE 0x03820000 -#define OPT_SUBREVISION 0x248 -#define SUBREVISION_MASK 0xFF +#define TEGRA_FUSE_BASE U(0x03820000) +#define OPT_SUBREVISION U(0x248) +#define SUBREVISION_MASK U(0xFF) /******************************************************************************* * GICv2 & interrupt handling related constants ******************************************************************************/ -#define TEGRA_GICD_BASE 0x03881000 -#define TEGRA_GICC_BASE 0x03882000 +#define TEGRA_GICD_BASE U(0x03881000) +#define TEGRA_GICC_BASE U(0x03882000) /******************************************************************************* * Security Engine related constants ******************************************************************************/ -#define TEGRA_SE0_BASE 0x03AC0000 -#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C -#define TEGRA_PKA1_BASE 0x03AD0000 -#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 -#define TEGRA_RNG1_BASE 0x03AE0000 -#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 +#define TEGRA_SE0_BASE U(0x03AC0000) +#define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C) +#define TEGRA_PKA1_BASE U(0x03AD0000) +#define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144) +#define TEGRA_RNG1_BASE U(0x03AE0000) +#define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0) /******************************************************************************* * Tegra Clock and Reset Controller constants ******************************************************************************/ -#define TEGRA_CAR_RESET_BASE 0x05000000 +#define TEGRA_CAR_RESET_BASE U(0x05000000) +#define TEGRA_GPU_RESET_REG_OFFSET U(0x30) +#define GPU_RESET_BIT (U(1) << 0) /******************************************************************************* * Tegra micro-seconds timer constants ******************************************************************************/ -#define TEGRA_TMRUS_BASE 0x0C2E0000 -#define TEGRA_TMRUS_SIZE 0x1000 +#define TEGRA_TMRUS_BASE U(0x0C2E0000) +#define TEGRA_TMRUS_SIZE U(0x1000) /******************************************************************************* * Tegra Power Mgmt Controller constants ******************************************************************************/ -#define TEGRA_PMC_BASE 0x0C360000 +#define TEGRA_PMC_BASE U(0x0C360000) /******************************************************************************* * Tegra scratch registers constants ******************************************************************************/ -#define TEGRA_SCRATCH_BASE 0x0C390000 -#define SECURE_SCRATCH_RSV1_LO 0x658 -#define SECURE_SCRATCH_RSV1_HI 0x65C -#define SECURE_SCRATCH_RSV6 0x680 -#define SECURE_SCRATCH_RSV11_LO 0x6A8 -#define SECURE_SCRATCH_RSV11_HI 0x6AC -#define SECURE_SCRATCH_RSV53_LO 0x7F8 -#define SECURE_SCRATCH_RSV53_HI 0x7FC -#define SECURE_SCRATCH_RSV54_HI 0x804 -#define SECURE_SCRATCH_RSV55_LO 0x808 -#define SECURE_SCRATCH_RSV55_HI 0x80C +#define TEGRA_SCRATCH_BASE U(0x0C390000) +#define SECURE_SCRATCH_RSV1_LO U(0x658) +#define SECURE_SCRATCH_RSV1_HI U(0x65C) +#define SECURE_SCRATCH_RSV6 U(0x680) +#define SECURE_SCRATCH_RSV11_LO U(0x6A8) +#define SECURE_SCRATCH_RSV11_HI U(0x6AC) +#define SECURE_SCRATCH_RSV53_LO U(0x7F8) +#define SECURE_SCRATCH_RSV53_HI U(0x7FC) +#define SECURE_SCRATCH_RSV54_HI U(0x804) +#define SECURE_SCRATCH_RSV55_LO U(0x808) +#define SECURE_SCRATCH_RSV55_HI U(0x80C) /******************************************************************************* * Tegra Memory Mapped Control Register Access constants ******************************************************************************/ -#define TEGRA_MMCRAB_BASE 0x0E000000 +#define TEGRA_MMCRAB_BASE U(0x0E000000) /******************************************************************************* * Tegra Memory Mapped Activity Monitor Register Access constants ******************************************************************************/ -#define TEGRA_ARM_ACTMON_CTR_BASE 0x0E060000 -#define TEGRA_DENVER_ACTMON_CTR_BASE 0x0E070000 +#define TEGRA_ARM_ACTMON_CTR_BASE U(0x0E060000) +#define TEGRA_DENVER_ACTMON_CTR_BASE U(0x0E070000) /******************************************************************************* * Tegra SMMU Controller constants ******************************************************************************/ -#define TEGRA_SMMU0_BASE 0x12000000 +#define TEGRA_SMMU0_BASE U(0x12000000) /******************************************************************************* * Tegra TZRAM constants ******************************************************************************/ -#define TEGRA_TZRAM_BASE 0x30000000 -#define TEGRA_TZRAM_SIZE 0x40000 +#define TEGRA_TZRAM_BASE U(0x30000000) +#define TEGRA_TZRAM_SIZE U(0x40000) #endif /* __TEGRA_DEF_H__ */ diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index efa2d501..454c666d 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -7,13 +7,15 @@ #ifndef __TEGRA_DEF_H__ #define __TEGRA_DEF_H__ +#include <utils_def.h> + /******************************************************************************* * Power down state IDs ******************************************************************************/ -#define PSTATE_ID_CORE_POWERDN 7 -#define PSTATE_ID_CLUSTER_IDLE 16 -#define PSTATE_ID_CLUSTER_POWERDN 17 -#define PSTATE_ID_SOC_POWERDN 27 +#define PSTATE_ID_CORE_POWERDN U(7) +#define PSTATE_ID_CLUSTER_IDLE U(16) +#define PSTATE_ID_CLUSTER_POWERDN U(17) +#define PSTATE_ID_SOC_POWERDN U(27) /******************************************************************************* * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` @@ -27,26 +29,26 @@ * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID ******************************************************************************/ -#define PLAT_MAX_RET_STATE 1 -#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) +#define PLAT_MAX_RET_STATE U(1) +#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) /******************************************************************************* * GIC memory map ******************************************************************************/ -#define TEGRA_GICD_BASE 0x50041000 -#define TEGRA_GICC_BASE 0x50042000 +#define TEGRA_GICD_BASE U(0x50041000) +#define TEGRA_GICC_BASE U(0x50042000) /******************************************************************************* * Tegra Memory Select Switch Controller constants ******************************************************************************/ -#define TEGRA_MSELECT_BASE 0x50060000 - -#define MSELECT_CONFIG 0x0 -#define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29) -#define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28) -#define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27) -#define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25) -#define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24) +#define TEGRA_MSELECT_BASE U(0x50060000) + +#define MSELECT_CONFIG U(0x0) +#define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) +#define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) +#define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) +#define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) +#define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ UNSUPPORTED_TX_ERR_MASTER1_BIT) #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ @@ -56,68 +58,70 @@ /******************************************************************************* * Tegra micro-seconds timer constants ******************************************************************************/ -#define TEGRA_TMRUS_BASE 0x60005010 -#define TEGRA_TMRUS_SIZE 0x1000 +#define TEGRA_TMRUS_BASE U(0x60005010) +#define TEGRA_TMRUS_SIZE U(0x1000) /******************************************************************************* * Tegra Clock and Reset Controller constants ******************************************************************************/ -#define TEGRA_CAR_RESET_BASE 0x60006000 +#define TEGRA_CAR_RESET_BASE U(0x60006000) +#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) +#define GPU_RESET_BIT (U(1) << 24) /******************************************************************************* * Tegra Flow Controller constants ******************************************************************************/ -#define TEGRA_FLOWCTRL_BASE 0x60007000 +#define TEGRA_FLOWCTRL_BASE U(0x60007000) /******************************************************************************* * Tegra Secure Boot Controller constants ******************************************************************************/ -#define TEGRA_SB_BASE 0x6000C200 +#define TEGRA_SB_BASE U(0x6000C200) /******************************************************************************* * Tegra Exception Vectors constants ******************************************************************************/ -#define TEGRA_EVP_BASE 0x6000F000 +#define TEGRA_EVP_BASE U(0x6000F000) /******************************************************************************* * Tegra Miscellaneous register constants ******************************************************************************/ -#define TEGRA_MISC_BASE 0x70000000 -#define HARDWARE_REVISION_OFFSET 0x804 +#define TEGRA_MISC_BASE U(0x70000000) +#define HARDWARE_REVISION_OFFSET U(0x804) /******************************************************************************* * Tegra UART controller base addresses ******************************************************************************/ -#define TEGRA_UARTA_BASE 0x70006000 -#define TEGRA_UARTB_BASE 0x70006040 -#define TEGRA_UARTC_BASE 0x70006200 -#define TEGRA_UARTD_BASE 0x70006300 -#define TEGRA_UARTE_BASE 0x70006400 +#define TEGRA_UARTA_BASE U(0x70006000) +#define TEGRA_UARTB_BASE U(0x70006040) +#define TEGRA_UARTC_BASE U(0x70006200) +#define TEGRA_UARTD_BASE U(0x70006300) +#define TEGRA_UARTE_BASE U(0x70006400) /******************************************************************************* * Tegra Power Mgmt Controller constants ******************************************************************************/ -#define TEGRA_PMC_BASE 0x7000E400 +#define TEGRA_PMC_BASE U(0x7000E400) /******************************************************************************* * Tegra Memory Controller constants ******************************************************************************/ -#define TEGRA_MC_BASE 0x70019000 +#define TEGRA_MC_BASE U(0x70019000) /* TZDRAM carveout configuration registers */ -#define MC_SECURITY_CFG0_0 0x70 -#define MC_SECURITY_CFG1_0 0x74 -#define MC_SECURITY_CFG3_0 0x9BC +#define MC_SECURITY_CFG0_0 U(0x70) +#define MC_SECURITY_CFG1_0 U(0x74) +#define MC_SECURITY_CFG3_0 U(0x9BC) /* Video Memory carveout configuration registers */ -#define MC_VIDEO_PROTECT_BASE_HI 0x978 -#define MC_VIDEO_PROTECT_BASE_LO 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c +#define MC_VIDEO_PROTECT_BASE_HI U(0x978) +#define MC_VIDEO_PROTECT_BASE_LO U(0x648) +#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) /******************************************************************************* * Tegra TZRAM constants ******************************************************************************/ -#define TEGRA_TZRAM_BASE 0x7C010000 -#define TEGRA_TZRAM_SIZE 0x10000 +#define TEGRA_TZRAM_BASE U(0x7C010000) +#define TEGRA_TZRAM_SIZE U(0x10000) #endif /* __TEGRA_DEF_H__ */ diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index 6aa75641..ec7a277c 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -15,8 +15,8 @@ /******************************************************************************* * Tegra DRAM memory base address ******************************************************************************/ -#define TEGRA_DRAM_BASE 0x80000000ULL -#define TEGRA_DRAM_END 0x27FFFFFFFULL +#define TEGRA_DRAM_BASE ULL(0x80000000) +#define TEGRA_DRAM_END ULL(0x27FFFFFFF) /******************************************************************************* * Struct for parameters received from BL2 @@ -71,8 +71,8 @@ int tegra_fiq_get_intr_context(void); void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); /* Declarations for tegra_gic.c */ -void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, unsigned int num_irqs); void tegra_gic_cpuif_deactivate(void); +void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs); /* Declarations for tegra_security.c */ void tegra_security_setup(void); diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk index f5af4081..eaf10914 100644 --- a/plat/nvidia/tegra/platform.mk +++ b/plat/nvidia/tegra/platform.mk @@ -34,3 +34,6 @@ include ${SOC_DIR}/platform_${TARGET_SOC}.mk # modify BUILD_PLAT to point to SoC specific build directory BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_SOC}/${BUILD_TYPE} + +# enable signed comparison checks +CFLAGS += -Wsign-compare diff --git a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c index 56ce91be..9b7dc853 100644 --- a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c @@ -49,7 +49,7 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, } /* Set lower power states to PLAT_MAX_OFF_STATE */ - for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) + for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; /* Set the SYSTEM_SUSPEND state-id */ diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h index 7d814d22..26197e97 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h +++ b/plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h @@ -14,127 +14,68 @@ * Macros to prepare CSTATE info request ******************************************************************************/ /* Description of the parameters for UPDATE_CSTATE_INFO request */ -#define CLUSTER_CSTATE_MASK 0x7ULL -#define CLUSTER_CSTATE_SHIFT 0U -#define CLUSTER_CSTATE_UPDATE_BIT (1ULL << 7) -#define CCPLEX_CSTATE_MASK 0x3ULL -#define CCPLEX_CSTATE_SHIFT 8ULL -#define CCPLEX_CSTATE_UPDATE_BIT (1ULL << 15) -#define SYSTEM_CSTATE_MASK 0xFULL -#define SYSTEM_CSTATE_SHIFT 16ULL -#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22ULL -#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1ULL << 22) -#define SYSTEM_CSTATE_UPDATE_BIT (1ULL << 23) -#define CSTATE_WAKE_MASK_UPDATE_BIT (1ULL << 31) -#define CSTATE_WAKE_MASK_SHIFT 32ULL -#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU +#define CLUSTER_CSTATE_MASK ULL(0x7) +#define CLUSTER_CSTATE_SHIFT U(0) +#define CLUSTER_CSTATE_UPDATE_BIT (ULL(1) << 7) +#define CCPLEX_CSTATE_MASK ULL(0x3) +#define CCPLEX_CSTATE_SHIFT ULL(8) +#define CCPLEX_CSTATE_UPDATE_BIT (ULL(1) << 15) +#define SYSTEM_CSTATE_MASK ULL(0xF) +#define SYSTEM_CSTATE_SHIFT ULL(16) +#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT ULL(22) +#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (ULL(1) << 22) +#define SYSTEM_CSTATE_UPDATE_BIT (ULL(1) << 23) +#define CSTATE_WAKE_MASK_UPDATE_BIT (ULL(1) << 31) +#define CSTATE_WAKE_MASK_SHIFT ULL(32) +#define CSTATE_WAKE_MASK_CLEAR U(0xFFFFFFFF) /******************************************************************************* * Auto-CC3 control macros ******************************************************************************/ -#define MCE_AUTO_CC3_FREQ_MASK 0x1FFU -#define MCE_AUTO_CC3_FREQ_SHIFT 0U -#define MCE_AUTO_CC3_VTG_MASK 0x7FU -#define MCE_AUTO_CC3_VTG_SHIFT 16U -#define MCE_AUTO_CC3_ENABLE_BIT (1U << 31) +#define MCE_AUTO_CC3_FREQ_MASK U(0x1FF) +#define MCE_AUTO_CC3_FREQ_SHIFT U(0) +#define MCE_AUTO_CC3_VTG_MASK U(0x7F) +#define MCE_AUTO_CC3_VTG_SHIFT U(16) +#define MCE_AUTO_CC3_ENABLE_BIT (U(1) << 31) /******************************************************************************* * Macros for the 'IS_SC7_ALLOWED' command ******************************************************************************/ -#define MCE_SC7_ALLOWED_MASK 0x7U -#define MCE_SC7_WAKE_TIME_SHIFT 32U +#define MCE_SC7_ALLOWED_MASK U(0x7) +#define MCE_SC7_WAKE_TIME_SHIFT U(32) /******************************************************************************* * Macros for 'read/write ctats' commands ******************************************************************************/ -#define MCE_CSTATE_STATS_TYPE_SHIFT 32ULL -#define MCE_CSTATE_WRITE_DATA_LO_MASK 0xFU +#define MCE_CSTATE_STATS_TYPE_SHIFT ULL(32) +#define MCE_CSTATE_WRITE_DATA_LO_MASK U(0xF) /******************************************************************************* * Macros for 'update crossover threshold' command ******************************************************************************/ -#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32U +#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT U(32) /******************************************************************************* - * MCA command struct + * MCA argument macros ******************************************************************************/ -typedef union mca_cmd { - struct command { - uint8_t cmd; - uint8_t idx; - uint8_t subidx; - } command; - struct input { - uint32_t low; - uint32_t high; - } input; - uint64_t data; -} mca_cmd_t; - -/******************************************************************************* - * MCA argument struct - ******************************************************************************/ -typedef union mca_arg { - struct err { - uint32_t error:8; - uint32_t unused:24; - uint32_t unused2:24; - uint32_t finish:8; - } err; - struct arg { - uint32_t low; - uint32_t high; - } arg; - uint64_t data; -} mca_arg_t; +#define MCA_ARG_ERROR_MASK U(0xFF) +#define MCA_ARG_FINISH_SHIFT U(24) +#define MCA_ARG_FINISH_MASK U(0xFF) /******************************************************************************* * Uncore PERFMON ARI struct ******************************************************************************/ -typedef union uncore_perfmon_req { - struct perfmon_command { - /* - * Commands: 0 = READ, 1 = WRITE - */ - uint32_t cmd:8; - /* - * The unit group: L2=0, L3=1, ROC=2, MC=3, IOB=4 - */ - uint32_t grp:4; - /* - * Unit selector: Selects the unit instance, with 0 = Unit - * = (number of units in group) - 1. - */ - uint32_t unit:4; - /* - * Selects the uncore perfmon register to access - */ - uint32_t reg:8; - /* - * Counter number. Selects which counter to use for - * registers NV_PMEVCNTR and NV_PMEVTYPER. - */ - uint32_t counter:8; - } perfmon_command; - struct perfmon_status { - /* - * Resulting command status - */ - uint32_t val:8; - uint32_t unused:24; - } perfmon_status; - uint64_t data; -} uncore_perfmon_req_t; - -#define UNCORE_PERFMON_CMD_READ 0U -#define UNCORE_PERFMON_CMD_WRITE 1U +#define UNCORE_PERFMON_CMD_READ U(0) +#define UNCORE_PERFMON_CMD_WRITE U(1) -#define UNCORE_PERFMON_CMD_MASK 0xFFU -#define UNCORE_PERFMON_UNIT_GRP_MASK 0xFU -#define UNCORE_PERFMON_SELECTOR_MASK 0xFU -#define UNCORE_PERFMON_REG_MASK 0xFFU -#define UNCORE_PERFMON_CTR_MASK 0xFFU -#define UNCORE_PERFMON_RESP_STATUS_MASK 0xFFU +#define UNCORE_PERFMON_CMD_MASK U(0xFF) +#define UNCORE_PERFMON_CMD_SHIFT U(24) +#define UNCORE_PERFMON_UNIT_GRP_MASK U(0xF) +#define UNCORE_PERFMON_SELECTOR_MASK U(0xF) +#define UNCORE_PERFMON_REG_MASK U(0xFF) +#define UNCORE_PERFMON_CTR_MASK U(0xFF) +#define UNCORE_PERFMON_RESP_STATUS_MASK U(0xFF) +#define UNCORE_PERFMON_RESP_STATUS_SHIFT U(24) /******************************************************************************* * Structure populated by arch specific code to export routines which perform @@ -146,13 +87,13 @@ typedef struct arch_mce_ops { * of STANDBYWFI, update the core power state and expected wake time, * then determine the proper power state to enter. */ - int (*enter_cstate)(uint32_t ari_base, uint32_t state, + int32_t (*enter_cstate)(uint32_t ari_base, uint32_t state, uint32_t wake_time); /* * This ARI request allows updating of the CLUSTER_CSTATE, * CCPLEX_CSTATE, and SYSTEM_CSTATE register values. */ - int (*update_cstate_info)(uint32_t ari_base, + int32_t (*update_cstate_info)(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, uint32_t system, @@ -164,7 +105,7 @@ typedef struct arch_mce_ops { * threshold times. An index value specifies which crossover * state is being updated. */ - int (*update_crossover_time)(uint32_t ari_base, + int32_t (*update_crossover_time)(uint32_t ari_base, uint32_t type, uint32_t time); /* @@ -177,7 +118,7 @@ typedef struct arch_mce_ops { * This ARI request allows write access to statistical information * related to power states. */ - int (*write_cstate_stats)(uint32_t ari_base, + int32_t (*write_cstate_stats)(uint32_t ari_base, uint32_t state, uint32_t stats); /* @@ -193,7 +134,7 @@ typedef struct arch_mce_ops { * must be entered. If the CCx state is not allowed, the response * indicates CC6/CC7 can't be entered */ - int (*is_ccx_allowed)(uint32_t ari_base, uint32_t state, + int32_t (*is_ccx_allowed)(uint32_t ari_base, uint32_t state, uint32_t wake_time); /* * This ARI request allows querying the CCPLEX to determine if @@ -203,19 +144,19 @@ typedef struct arch_mce_ops { * indicates SC7 must be entered. If the SC7 state is not allowed, * the response indicates SC7 can't be entered */ - int (*is_sc7_allowed)(uint32_t ari_base, uint32_t state, + int32_t (*is_sc7_allowed)(uint32_t ari_base, uint32_t state, uint32_t wake_time); /* * This ARI request allows a core to bring another offlined core * back online to the C0 state. Note that a core is offlined by * entering a C-state where the WAKE_MASK is all 0. */ - int (*online_core)(uint32_t ari_base, uint32_t cpuid); + int32_t (*online_core)(uint32_t ari_base, uint32_t cpuid); /* * This ARI request allows the CPU to enable/disable Auto-CC3 idle * state. */ - int (*cc3_ctrl)(uint32_t ari_base, + int32_t (*cc3_ctrl)(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); @@ -223,30 +164,30 @@ typedef struct arch_mce_ops { * This ARI request allows updating the reset vector register for * D15 and A57 CPUs. */ - int (*update_reset_vector)(uint32_t ari_base); + int32_t (*update_reset_vector)(uint32_t ari_base); /* * This ARI request instructs the ROC to flush A57 data caches in * order to maintain coherency with the Denver cluster. */ - int (*roc_flush_cache)(uint32_t ari_base); + int32_t (*roc_flush_cache)(uint32_t ari_base); /* * This ARI request instructs the ROC to flush A57 data caches along * with the caches covering ARM code in order to maintain coherency * with the Denver cluster. */ - int (*roc_flush_cache_trbits)(uint32_t ari_base); + int32_t (*roc_flush_cache_trbits)(uint32_t ari_base); /* * This ARI request instructs the ROC to clean A57 data caches along * with the caches covering ARM code in order to maintain coherency * with the Denver cluster. */ - int (*roc_clean_cache)(uint32_t ari_base); + int32_t (*roc_clean_cache)(uint32_t ari_base); /* * This ARI request reads/writes the Machine Check Arch. (MCA) * registers. */ uint64_t (*read_write_mca)(uint32_t ari_base, - mca_cmd_t cmd, + uint64_t cmd, uint64_t *data); /* * Some MC GSC (General Security Carveout) register values are @@ -258,7 +199,7 @@ typedef struct arch_mce_ops { * register value. This ARI request allows updating the GSC register * value for a certain carveout in the CCPLEX. */ - int (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx); + int32_t (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx); /* * This ARI request instructs the CCPLEX to either shutdown or * reset the entire system @@ -268,8 +209,8 @@ typedef struct arch_mce_ops { * This ARI request reads/writes data from/to Uncore PERFMON * registers */ - int (*read_write_uncore_perfmon)(uint32_t ari_base, - uncore_perfmon_req_t req, uint64_t *data); + int32_t (*read_write_uncore_perfmon)(uint32_t ari_base, + uint64_t req, uint64_t *data); /* * This ARI implements ARI_MISC_CCPLEX commands. This can be * used to enable/disable coresight clock gating. @@ -279,39 +220,42 @@ typedef struct arch_mce_ops { } arch_mce_ops_t; /* declarations for ARI/NVG handler functions */ -int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); -int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, +int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); +int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, uint8_t update_wake_mask); -int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); +int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state); -int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); +int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data); -int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); -int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); -int ari_online_core(uint32_t ari_base, uint32_t core); -int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); -int ari_reset_vector_update(uint32_t ari_base); -int ari_roc_flush_cache_trbits(uint32_t ari_base); -int ari_roc_flush_cache(uint32_t ari_base); -int ari_roc_clean_cache(uint32_t ari_base); -uint64_t ari_read_write_mca(uint32_t ari_base, mca_cmd_t cmd, uint64_t *data); -int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx); +int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); +int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); +int32_t ari_online_core(uint32_t ari_base, uint32_t core); +int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); +int32_t ari_reset_vector_update(uint32_t ari_base); +int32_t ari_roc_flush_cache_trbits(uint32_t ari_base); +int32_t ari_roc_flush_cache(uint32_t ari_base); +int32_t ari_roc_clean_cache(uint32_t ari_base); +uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data); +int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx); void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx); -int ari_read_write_uncore_perfmon(uint32_t ari_base, - uncore_perfmon_req_t req, uint64_t *data); +int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, + uint64_t req, uint64_t *data); void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value); -int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); -int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, +int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); +int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, uint8_t update_wake_mask); -int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); +int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state); -int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t val); -int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); -int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); -int nvg_online_core(uint32_t ari_base, uint32_t core); -int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); +int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); +int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); +int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); +int32_t nvg_online_core(uint32_t ari_base, uint32_t core); +int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); +extern void nvg_set_request_data(uint64_t req, uint64_t data); +extern void nvg_set_request(uint64_t req); +extern uint64_t nvg_get_result(void); #endif /* __MCE_PRIVATE_H__ */ diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c index 4765ba00..2803f4ea 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c @@ -19,13 +19,13 @@ /******************************************************************************* * Register offsets for ARI request/results ******************************************************************************/ -#define ARI_REQUEST 0x0 -#define ARI_REQUEST_EVENT_MASK 0x4 -#define ARI_STATUS 0x8 -#define ARI_REQUEST_DATA_LO 0xC -#define ARI_REQUEST_DATA_HI 0x10 -#define ARI_RESPONSE_DATA_LO 0x14 -#define ARI_RESPONSE_DATA_HI 0x18 +#define ARI_REQUEST 0x0U +#define ARI_REQUEST_EVENT_MASK 0x4U +#define ARI_STATUS 0x8U +#define ARI_REQUEST_DATA_LO 0xCU +#define ARI_REQUEST_DATA_HI 0x10U +#define ARI_RESPONSE_DATA_LO 0x14U +#define ARI_RESPONSE_DATA_HI 0x18U /* Status values for the current request */ #define ARI_REQ_PENDING 1U @@ -41,12 +41,12 @@ ******************************************************************************/ static inline uint32_t ari_read_32(uint32_t ari_base, uint32_t reg) { - return mmio_read_32(ari_base + reg); + return mmio_read_32((uint64_t)ari_base + (uint64_t)reg); } static inline void ari_write_32(uint32_t ari_base, uint32_t val, uint32_t reg) { - mmio_write_32(ari_base + reg, val); + mmio_write_32((uint64_t)ari_base + (uint64_t)reg, val); } static inline uint32_t ari_get_request_low(uint32_t ari_base) @@ -75,11 +75,12 @@ static inline void ari_clobber_response(uint32_t ari_base) ari_write_32(ari_base, 0, ARI_RESPONSE_DATA_HI); } -static int ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req, +static int32_t ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req, uint32_t lo, uint32_t hi) { uint32_t retries = ARI_MAX_RETRY_COUNT; uint32_t status; + int32_t ret = 0; /* program the request, event_mask, hi and lo registers */ ari_write_32(ari_base, lo, ARI_REQUEST_DATA_LO); @@ -92,236 +93,270 @@ static int ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req, * ARI_STATUS polling, since MCE is waiting for SW to trigger * the event. */ - if (evt_mask) - return 0; - - /* For shutdown/reboot commands, we dont have to check for timeouts */ - if ((req == (uint32_t)TEGRA_ARI_MISC_CCPLEX) && - ((lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) || - (lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) { - return 0; - } - - /* - * Wait for the command response for not more than the timeout - */ - while (retries != 0U) { - - /* read the command status */ - status = ari_read_32(ari_base, ARI_STATUS); - if ((status & (ARI_REQ_ONGOING | ARI_REQ_PENDING)) == 0U) - break; - - /* delay 1 ms */ - mdelay(1); - - /* decrement the retry count */ - retries--; - } - - /* assert if the command timed out */ - if (retries == 0U) { - ERROR("ARI request timed out: req %d on CPU %d\n", - req, plat_my_core_pos()); - assert(retries != 0U); + if (evt_mask != 0U) { + ret = 0; + } else { + /* For shutdown/reboot commands, we dont have to check for timeouts */ + if ((req == (uint32_t)TEGRA_ARI_MISC_CCPLEX) && + ((lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) || + (lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) { + ret = 0; + } else { + /* + * Wait for the command response for not more than the timeout + */ + while (retries != 0U) { + + /* read the command status */ + status = ari_read_32(ari_base, ARI_STATUS); + if ((status & (ARI_REQ_ONGOING | ARI_REQ_PENDING)) == 0U) { + break; + } + + /* delay 1 ms */ + mdelay(1); + + /* decrement the retry count */ + retries--; + } + + /* assert if the command timed out */ + if (retries == 0U) { + ERROR("ARI request timed out: req %d on CPU %d\n", + req, plat_my_core_pos()); + assert(retries != 0U); + } + } } - return 0; + return ret; } -int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) +int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) { + int32_t ret = 0; + /* check for allowed power state */ - if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 && - state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) { + if ((state != TEGRA_ARI_CORE_C0) && + (state != TEGRA_ARI_CORE_C1) && + (state != TEGRA_ARI_CORE_C6) && + (state != TEGRA_ARI_CORE_C7)) { ERROR("%s: unknown cstate (%d)\n", __func__, state); - return EINVAL; - } - - /* clean the previous response state */ - ari_clobber_response(ari_base); + ret = EINVAL; + } else { + /* clean the previous response state */ + ari_clobber_response(ari_base); - /* Enter the cstate, to be woken up after wake_time (TSC ticks) */ - return ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT, + /* Enter the cstate, to be woken up after wake_time (TSC ticks) */ + ret = ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT, TEGRA_ARI_ENTER_CSTATE, state, wake_time); + } + + return ret; } -int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, +int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, uint8_t update_wake_mask) { - uint32_t val = 0; + uint32_t val = 0U; /* clean the previous response state */ ari_clobber_response(ari_base); /* update CLUSTER_CSTATE? */ - if (cluster) - val |= (cluster & CLUSTER_CSTATE_MASK) | - CLUSTER_CSTATE_UPDATE_BIT; + if (cluster != 0U) { + val |= (cluster & (uint32_t)CLUSTER_CSTATE_MASK) | + (uint32_t)CLUSTER_CSTATE_UPDATE_BIT; + } /* update CCPLEX_CSTATE? */ - if (ccplex) - val |= (ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT | - CCPLEX_CSTATE_UPDATE_BIT; + if (ccplex != 0U) { + val |= ((ccplex & (uint32_t)CCPLEX_CSTATE_MASK) << (uint32_t)CCPLEX_CSTATE_SHIFT) | + (uint32_t)CCPLEX_CSTATE_UPDATE_BIT; + } /* update SYSTEM_CSTATE? */ - if (system) - val |= ((system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | - ((sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) | - SYSTEM_CSTATE_UPDATE_BIT); + if (system != 0U) { + val |= ((system & (uint32_t)SYSTEM_CSTATE_MASK) << (uint32_t)SYSTEM_CSTATE_SHIFT) | + (((uint32_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) | + (uint32_t)SYSTEM_CSTATE_UPDATE_BIT); + } /* update wake mask value? */ - if (update_wake_mask) - val |= CSTATE_WAKE_MASK_UPDATE_BIT; + if (update_wake_mask != 0U) { + val |= (uint32_t)CSTATE_WAKE_MASK_UPDATE_BIT; + } /* set the updated cstate info */ - return ari_request_wait(ari_base, 0, TEGRA_ARI_UPDATE_CSTATE_INFO, val, + return ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CSTATE_INFO, val, wake_mask); } -int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) +int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) { + int32_t ret = 0; + /* sanity check crossover type */ if ((type == TEGRA_ARI_CROSSOVER_C1_C6) || - (type > TEGRA_ARI_CROSSOVER_CCP3_SC1)) - return EINVAL; - - /* clean the previous response state */ - ari_clobber_response(ari_base); - - /* update crossover threshold time */ - return ari_request_wait(ari_base, 0, TEGRA_ARI_UPDATE_CROSSOVER, + (type > TEGRA_ARI_CROSSOVER_CCP3_SC1)) { + ret = EINVAL; + } else { + /* clean the previous response state */ + ari_clobber_response(ari_base); + + /* update crossover threshold time */ + ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CROSSOVER, type, time); + } + + return ret; } uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state) { - int ret; + int32_t ret; + uint64_t result; /* sanity check crossover type */ - if (state == 0) - return EINVAL; - - /* clean the previous response state */ - ari_clobber_response(ari_base); - - ret = ari_request_wait(ari_base, 0, TEGRA_ARI_CSTATE_STATS, state, 0); - if (ret != 0) - return EINVAL; - - return (uint64_t)ari_get_response_low(ari_base); + if (state == 0U) { + result = EINVAL; + } else { + /* clean the previous response state */ + ari_clobber_response(ari_base); + + ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_CSTATE_STATS, state, 0U); + if (ret != 0) { + result = EINVAL; + } else { + result = (uint64_t)ari_get_response_low(ari_base); + } + } + return result; } -int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) +int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) { /* clean the previous response state */ ari_clobber_response(ari_base); /* write the cstate stats */ - return ari_request_wait(ari_base, 0, TEGRA_ARI_WRITE_CSTATE_STATS, state, + return ari_request_wait(ari_base, 0U, TEGRA_ARI_WRITE_CSTATE_STATS, state, stats); } uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data) { uint64_t resp; - int ret; + int32_t ret; + uint32_t local_data = data; /* clean the previous response state */ ari_clobber_response(ari_base); /* ARI_REQUEST_DATA_HI is reserved for commands other than 'ECHO' */ - if (cmd != TEGRA_ARI_MISC_ECHO) - data = 0; - - ret = ari_request_wait(ari_base, 0, TEGRA_ARI_MISC, cmd, data); - if (ret) - return (uint64_t)ret; + if (cmd != TEGRA_ARI_MISC_ECHO) { + local_data = 0U; + } - /* get the command response */ - resp = ari_get_response_low(ari_base); - resp |= ((uint64_t)ari_get_response_high(ari_base) << 32); + ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC, cmd, local_data); + if (ret != 0) { + resp = (uint64_t)ret; + } else { + /* get the command response */ + resp = ari_get_response_low(ari_base); + resp |= ((uint64_t)ari_get_response_high(ari_base) << 32); + } return resp; } -int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) +int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) { - int ret; + int32_t ret; + uint32_t result; /* clean the previous response state */ ari_clobber_response(ari_base); - ret = ari_request_wait(ari_base, 0, TEGRA_ARI_IS_CCX_ALLOWED, state & 0x7, + ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_IS_CCX_ALLOWED, state & 0x7U, wake_time); - if (ret) { + if (ret != 0) { ERROR("%s: failed (%d)\n", __func__, ret); - return 0; + result = 0U; + } else { + result = ari_get_response_low(ari_base) & 0x1U; } /* 1 = CCx allowed, 0 = CCx not allowed */ - return (ari_get_response_low(ari_base) & 0x1); + return (int32_t)result; } -int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) +int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) { - int ret; + int32_t ret, result; /* check for allowed power state */ - if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 && - state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) { + if ((state != TEGRA_ARI_CORE_C0) && + (state != TEGRA_ARI_CORE_C1) && + (state != TEGRA_ARI_CORE_C6) && + (state != TEGRA_ARI_CORE_C7)) { ERROR("%s: unknown cstate (%d)\n", __func__, state); - return EINVAL; - } - - /* clean the previous response state */ - ari_clobber_response(ari_base); - - ret = ari_request_wait(ari_base, 0, TEGRA_ARI_IS_SC7_ALLOWED, state, - wake_time); - if (ret) { - ERROR("%s: failed (%d)\n", __func__, ret); - return 0; + result = EINVAL; + } else { + /* clean the previous response state */ + ari_clobber_response(ari_base); + + ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_IS_SC7_ALLOWED, state, + wake_time); + if (ret != 0) { + ERROR("%s: failed (%d)\n", __func__, ret); + result = 0; + } else { + /* 1 = SC7 allowed, 0 = SC7 not allowed */ + result = (ari_get_response_low(ari_base) != 0U) ? 1 : 0; + } } - /* 1 = SC7 allowed, 0 = SC7 not allowed */ - return !!ari_get_response_low(ari_base); + return result; } -int ari_online_core(uint32_t ari_base, uint32_t core) +int32_t ari_online_core(uint32_t ari_base, uint32_t core) { - int cpu = read_mpidr() & MPIDR_CPU_MASK; - int cluster = (read_mpidr() & MPIDR_CLUSTER_MASK) >> - MPIDR_AFFINITY_BITS; - int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; + uint64_t cpu = read_mpidr() & (uint64_t)(MPIDR_CPU_MASK); + uint64_t cluster = (read_mpidr() & (uint64_t)(MPIDR_CLUSTER_MASK)) >> + (uint64_t)(MPIDR_AFFINITY_BITS); + uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; + int32_t ret; /* construct the current CPU # */ cpu |= (cluster << 2); /* sanity check target core id */ - if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) { + if ((core >= MCE_CORE_ID_MAX) || (cpu == (uint64_t)core)) { ERROR("%s: unsupported core id (%d)\n", __func__, core); - return EINVAL; - } - - /* - * The Denver cluster has 2 CPUs only - 0, 1. - */ - if (impl == DENVER_IMPL && ((core == 2) || (core == 3))) { - ERROR("%s: unknown core id (%d)\n", __func__, core); - return EINVAL; + ret = EINVAL; + } else { + /* + * The Denver cluster has 2 CPUs only - 0, 1. + */ + if ((impl == (uint32_t)DENVER_IMPL) && + ((core == 2U) || (core == 3U))) { + ERROR("%s: unknown core id (%d)\n", __func__, core); + ret = EINVAL; + } else { + /* clean the previous response state */ + ari_clobber_response(ari_base); + ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_ONLINE_CORE, core, 0U); + } } - /* clean the previous response state */ - ari_clobber_response(ari_base); - - return ari_request_wait(ari_base, 0, TEGRA_ARI_ONLINE_CORE, core, 0); + return ret; } -int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) +int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) { - int val; + uint32_t val; /* clean the previous response state */ ari_clobber_response(ari_base); @@ -338,12 +373,12 @@ int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable */ val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\ ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\ - (enable ? MCE_AUTO_CC3_ENABLE_BIT : 0)); + ((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U)); - return ari_request_wait(ari_base, 0, TEGRA_ARI_CC3_CTRL, val, 0); + return ari_request_wait(ari_base, 0U, TEGRA_ARI_CC3_CTRL, val, 0U); } -int ari_reset_vector_update(uint32_t ari_base) +int32_t ari_reset_vector_update(uint32_t ari_base) { /* clean the previous response state */ ari_clobber_response(ari_base); @@ -352,85 +387,97 @@ int ari_reset_vector_update(uint32_t ari_base) * Need to program the CPU reset vector one time during cold boot * and SC7 exit */ - ari_request_wait(ari_base, 0, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0, 0); + (void)ari_request_wait(ari_base, 0U, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0U, 0U); return 0; } -int ari_roc_flush_cache_trbits(uint32_t ari_base) +int32_t ari_roc_flush_cache_trbits(uint32_t ari_base) { /* clean the previous response state */ ari_clobber_response(ari_base); - return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS, - 0, 0); + return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS, + 0U, 0U); } -int ari_roc_flush_cache(uint32_t ari_base) +int32_t ari_roc_flush_cache(uint32_t ari_base) { /* clean the previous response state */ ari_clobber_response(ari_base); - return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY, - 0, 0); + return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY, + 0U, 0U); } -int ari_roc_clean_cache(uint32_t ari_base) +int32_t ari_roc_clean_cache(uint32_t ari_base) { /* clean the previous response state */ ari_clobber_response(ari_base); - return ari_request_wait(ari_base, 0, TEGRA_ARI_ROC_CLEAN_CACHE_ONLY, - 0, 0); + return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_CLEAN_CACHE_ONLY, + 0U, 0U); } -uint64_t ari_read_write_mca(uint32_t ari_base, mca_cmd_t cmd, uint64_t *data) +uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data) { - mca_arg_t mca_arg; - int ret; + uint64_t mca_arg_data, result = 0; + uint32_t resp_lo, resp_hi; + uint32_t mca_arg_err, mca_arg_finish; + int32_t ret; /* Set data (write) */ - mca_arg.data = data ? *data : 0ull; + mca_arg_data = (data != NULL) ? *data : 0ULL; /* Set command */ - ari_write_32(ari_base, cmd.input.low, ARI_RESPONSE_DATA_LO); - ari_write_32(ari_base, cmd.input.high, ARI_RESPONSE_DATA_HI); - - ret = ari_request_wait(ari_base, 0, TEGRA_ARI_MCA, mca_arg.arg.low, - mca_arg.arg.high); - if (!ret) { - mca_arg.arg.low = ari_get_response_low(ari_base); - mca_arg.arg.high = ari_get_response_high(ari_base); - if (!mca_arg.err.finish) - return (uint64_t)mca_arg.err.error; - - if (data) { - mca_arg.arg.low = ari_get_request_low(ari_base); - mca_arg.arg.high = ari_get_request_high(ari_base); - *data = mca_arg.data; + ari_write_32(ari_base, (uint32_t)cmd, ARI_RESPONSE_DATA_LO); + ari_write_32(ari_base, (uint32_t)(cmd >> 32U), ARI_RESPONSE_DATA_HI); + + ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MCA, + (uint32_t)mca_arg_data, + (uint32_t)(mca_arg_data >> 32UL)); + if (ret == 0) { + resp_lo = ari_get_response_low(ari_base); + resp_hi = ari_get_response_high(ari_base); + + mca_arg_err = resp_lo & MCA_ARG_ERROR_MASK; + mca_arg_finish = (resp_hi >> MCA_ARG_FINISH_SHIFT) & + MCA_ARG_FINISH_MASK; + + if (mca_arg_finish == 0U) { + result = (uint64_t)mca_arg_err; + } else { + if (data != NULL) { + resp_lo = ari_get_request_low(ari_base); + resp_hi = ari_get_request_high(ari_base); + *data = ((uint64_t)resp_hi << 32UL) | + (uint64_t)resp_lo; + } } } - return 0; + return result; } -int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx) +int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx) { + int32_t ret = 0; /* sanity check GSC ID */ - if (gsc_idx > TEGRA_ARI_GSC_VPR_IDX) - return EINVAL; - - /* clean the previous response state */ - ari_clobber_response(ari_base); - - /* - * The MCE code will read the GSC carveout value, corrseponding to - * the ID, from the MC registers and update the internal GSC registers - * of the CCPLEX. - */ - ari_request_wait(ari_base, 0, TEGRA_ARI_UPDATE_CCPLEX_GSC, gsc_idx, 0); + if (gsc_idx > (uint32_t)TEGRA_ARI_GSC_VPR_IDX) { + ret = EINVAL; + } else { + /* clean the previous response state */ + ari_clobber_response(ari_base); + + /* + * The MCE code will read the GSC carveout value, corrseponding to + * the ID, from the MC registers and update the internal GSC registers + * of the CCPLEX. + */ + (void)ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CCPLEX_GSC, gsc_idx, 0U); + } - return 0; + return ret; } void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx) @@ -441,48 +488,55 @@ void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx) /* * The MCE will shutdown or restart the entire system */ - (void)ari_request_wait(ari_base, 0, TEGRA_ARI_MISC_CCPLEX, state_idx, 0); + (void)ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC_CCPLEX, state_idx, 0U); } -int ari_read_write_uncore_perfmon(uint32_t ari_base, - uncore_perfmon_req_t req, uint64_t *data) +int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, uint64_t req, + uint64_t *data) { - int ret; + int32_t ret, result; uint32_t val; + uint8_t req_cmd, req_status; + + req_cmd = (uint8_t)(req >> UNCORE_PERFMON_CMD_SHIFT); /* clean the previous response state */ ari_clobber_response(ari_base); /* sanity check input parameters */ - if (req.perfmon_command.cmd == UNCORE_PERFMON_CMD_READ && !data) { + if ((req_cmd == UNCORE_PERFMON_CMD_READ) && (data == NULL)) { ERROR("invalid parameters\n"); - return EINVAL; + result = EINVAL; + } else { + /* + * For "write" commands get the value that has to be written + * to the uncore perfmon registers + */ + val = (req_cmd == UNCORE_PERFMON_CMD_WRITE) ? + (uint32_t)*data : 0UL; + + ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_PERFMON, val, + (uint32_t)req); + if (ret != 0) { + result = ret; + } else { + /* read the command status value */ + req_status = (uint8_t)ari_get_response_high(ari_base) & + UNCORE_PERFMON_RESP_STATUS_MASK; + + /* + * For "read" commands get the data from the uncore + * perfmon registers + */ + req_status >>= UNCORE_PERFMON_RESP_STATUS_SHIFT; + if ((req_status == 0U) && (req_cmd == UNCORE_PERFMON_CMD_READ)) { + *data = ari_get_response_low(ari_base); + } + result = (int32_t)req_status; + } } - /* - * For "write" commands get the value that has to be written - * to the uncore perfmon registers - */ - val = (req.perfmon_command.cmd == UNCORE_PERFMON_CMD_WRITE) ? - *data : 0; - - ret = ari_request_wait(ari_base, 0, TEGRA_ARI_PERFMON, val, req.data); - if (ret) - return ret; - - /* read the command status value */ - req.perfmon_status.val = ari_get_response_high(ari_base) & - UNCORE_PERFMON_RESP_STATUS_MASK; - - /* - * For "read" commands get the data from the uncore - * perfmon registers - */ - if ((req.perfmon_status.val == 0) && (req.perfmon_command.cmd == - UNCORE_PERFMON_CMD_READ)) - *data = ari_get_response_low(ari_base); - - return (int)req.perfmon_status.val; + return result; } void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value) @@ -494,12 +548,11 @@ void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value) if ((index > TEGRA_ARI_MISC_CCPLEX_EDBGREQ) || ((index == TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) && - (value > 1))) { + (value > 1U))) { ERROR("%s: invalid parameters \n", __func__); - return; + } else { + /* clean the previous response state */ + ari_clobber_response(ari_base); + (void)ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC_CCPLEX, index, value); } - - /* clean the previous response state */ - ari_clobber_response(ari_base); - (void)ari_request_wait(ari_base, 0, TEGRA_ARI_MISC_CCPLEX, index, value); } diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c index 6363ed7c..5435ce6e 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,7 +67,7 @@ static arch_mce_ops_t ari_mce_ops = { .misc_ccplex = ari_misc_ccplex }; -typedef struct mce_config { +typedef struct { uint32_t ari_base; arch_mce_ops_t *ops; } mce_config_t; @@ -108,9 +108,9 @@ static mce_config_t mce_cfg_table[MCE_ARI_APERTURES_MAX] = { static uint32_t mce_get_curr_cpu_ari_base(void) { - uint32_t mpidr = read_mpidr(); - int cpuid = mpidr & MPIDR_CPU_MASK; - int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; + uint64_t mpidr = read_mpidr(); + uint64_t cpuid = mpidr & (uint64_t)MPIDR_CPU_MASK; + uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK; /* * T186 has 2 CPU clusters, one with Denver CPUs and the other with @@ -119,17 +119,19 @@ static uint32_t mce_get_curr_cpu_ari_base(void) * struct, we have to convert the Denver CPU ids to the corresponding * indices in the mce_ops_table array. */ - if (impl == DENVER_IMPL) - cpuid |= 0x4; + if (impl == DENVER_IMPL) { + cpuid |= 0x4U; + } return mce_cfg_table[cpuid].ari_base; } static arch_mce_ops_t *mce_get_curr_cpu_ops(void) { - uint32_t mpidr = read_mpidr(); - int cpuid = mpidr & MPIDR_CPU_MASK; - int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; + uint64_t mpidr = read_mpidr(); + uint64_t cpuid = mpidr & (uint64_t)MPIDR_CPU_MASK; + uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & + (uint64_t)MIDR_IMPL_MASK; /* * T186 has 2 CPU clusters, one with Denver CPUs and the other with @@ -138,8 +140,9 @@ static arch_mce_ops_t *mce_get_curr_cpu_ops(void) * struct, we have to convert the Denver CPU ids to the corresponding * indices in the mce_ops_table array. */ - if (impl == DENVER_IMPL) - cpuid |= 0x4; + if (impl == DENVER_IMPL) { + cpuid |= 0x4U; + } return mce_cfg_table[cpuid].ops; } @@ -147,20 +150,16 @@ static arch_mce_ops_t *mce_get_curr_cpu_ops(void) /******************************************************************************* * Common handler for all MCE commands ******************************************************************************/ -int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, +int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, uint64_t arg2) { - arch_mce_ops_t *ops; + const arch_mce_ops_t *ops; + gp_regs_t *gp_regs = get_gpregs_ctx(cm_get_context(NON_SECURE)); uint32_t cpu_ari_base; uint64_t ret64 = 0, arg3, arg4, arg5; - int ret = 0; - mca_cmd_t mca_cmd; - uncore_perfmon_req_t req; - cpu_context_t *ctx = cm_get_context(NON_SECURE); - gp_regs_t *gp_regs = get_gpregs_ctx(ctx); + int32_t ret = 0; - assert(ctx); - assert(gp_regs); + assert(gp_regs != NULL); /* get a pointer to the CPU's arch_mce_ops_t struct */ ops = mce_get_curr_cpu_ops(); @@ -171,8 +170,9 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, switch (cmd) { case MCE_CMD_ENTER_CSTATE: ret = ops->enter_cstate(cpu_ari_base, arg0, arg1); - if (ret < 0) + if (ret < 0) { ERROR("%s: enter_cstate failed(%d)\n", __func__, ret); + } break; @@ -181,28 +181,30 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, * get the parameters required for the update cstate info * command */ - arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4); - arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5); - arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6); + arg3 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X4)); + arg4 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X5)); + arg5 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X6)); ret = ops->update_cstate_info(cpu_ari_base, (uint32_t)arg0, (uint32_t)arg1, (uint32_t)arg2, (uint8_t)arg3, (uint32_t)arg4, (uint8_t)arg5); - if (ret < 0) + if (ret < 0) { ERROR("%s: update_cstate_info failed(%d)\n", __func__, ret); + } - write_ctx_reg(gp_regs, CTX_GPREG_X4, 0); - write_ctx_reg(gp_regs, CTX_GPREG_X5, 0); - write_ctx_reg(gp_regs, CTX_GPREG_X6, 0); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X4), (0)); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X5), (0)); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X6), (0)); break; case MCE_CMD_UPDATE_CROSSOVER_TIME: ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1); - if (ret < 0) + if (ret < 0) { ERROR("%s: update_crossover_time failed(%d)\n", __func__, ret); + } break; @@ -210,16 +212,17 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, ret64 = ops->read_cstate_stats(cpu_ari_base, arg0); /* update context to return cstate stats value */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); - write_ctx_reg(gp_regs, CTX_GPREG_X2, ret64); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64)); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2), (ret64)); break; case MCE_CMD_WRITE_CSTATE_STATS: ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1); - if (ret < 0) + if (ret < 0) { ERROR("%s: write_cstate_stats failed(%d)\n", __func__, ret); + } break; @@ -231,7 +234,8 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, } /* update context to return CCx status value */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), + (uint64_t)(ret)); break; @@ -243,22 +247,26 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, } /* update context to return SC7 status value */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret); - write_ctx_reg(gp_regs, CTX_GPREG_X3, ret); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), + (uint64_t)(ret)); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X3), + (uint64_t)(ret)); break; case MCE_CMD_ONLINE_CORE: ret = ops->online_core(cpu_ari_base, arg0); - if (ret < 0) + if (ret < 0) { ERROR("%s: online_core failed(%d)\n", __func__, ret); + } break; case MCE_CMD_CC3_CTRL: ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2); - if (ret < 0) + if (ret < 0) { ERROR("%s: cc3_ctrl failed(%d)\n", __func__, ret); + } break; @@ -267,8 +275,10 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, arg0); /* update context to return if echo'd data matched source */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64 == arg0); - write_ctx_reg(gp_regs, CTX_GPREG_X2, ret64 == arg0); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), + ((ret64 == arg0) ? 1ULL : 0ULL)); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2), + ((ret64 == arg0) ? 1ULL : 0ULL)); break; @@ -280,8 +290,10 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, * version = minor(63:32) | major(31:0). Update context * to return major and minor version number. */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint32_t)ret64); - write_ctx_reg(gp_regs, CTX_GPREG_X2, (uint32_t)(ret64 >> 32)); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), + (ret64)); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2), + (ret64 >> 32ULL)); break; @@ -290,50 +302,51 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0); /* update context to return features value */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64)); break; case MCE_CMD_ROC_FLUSH_CACHE_TRBITS: ret = ops->roc_flush_cache_trbits(cpu_ari_base); - if (ret < 0) + if (ret < 0) { ERROR("%s: flush cache_trbits failed(%d)\n", __func__, ret); + } break; case MCE_CMD_ROC_FLUSH_CACHE: ret = ops->roc_flush_cache(cpu_ari_base); - if (ret < 0) + if (ret < 0) { ERROR("%s: flush cache failed(%d)\n", __func__, ret); + } break; case MCE_CMD_ROC_CLEAN_CACHE: ret = ops->roc_clean_cache(cpu_ari_base); - if (ret < 0) + if (ret < 0) { ERROR("%s: clean cache failed(%d)\n", __func__, ret); + } break; case MCE_CMD_ENUM_READ_MCA: - memcpy(&mca_cmd, &arg0, sizeof(arg0)); - ret64 = ops->read_write_mca(cpu_ari_base, mca_cmd, &arg1); + ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); /* update context to return MCA data/error */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); - write_ctx_reg(gp_regs, CTX_GPREG_X2, arg1); - write_ctx_reg(gp_regs, CTX_GPREG_X3, ret64); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64)); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X2), (arg1)); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X3), (ret64)); break; case MCE_CMD_ENUM_WRITE_MCA: - memcpy(&mca_cmd, &arg0, sizeof(arg0)); - ret64 = ops->read_write_mca(cpu_ari_base, mca_cmd, &arg1); + ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); /* update context to return MCA error */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, ret64); - write_ctx_reg(gp_regs, CTX_GPREG_X3, ret64); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (ret64)); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X3), (ret64)); break; @@ -357,11 +370,10 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, #endif case MCE_CMD_UNCORE_PERFMON_REQ: - memcpy(&req, &arg0, sizeof(arg0)); - ret = ops->read_write_uncore_perfmon(cpu_ari_base, req, &arg1); + ret = ops->read_write_uncore_perfmon(cpu_ari_base, arg0, &arg1); /* update context to return data */ - write_ctx_reg(gp_regs, CTX_GPREG_X1, arg1); + write_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X1), (arg1)); break; case MCE_CMD_MISC_CCPLEX: @@ -370,8 +382,9 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, break; default: - ERROR("unknown MCE command (%d)\n", cmd); - return EINVAL; + ERROR("unknown MCE command (%lu)\n", cmd); + ret = EINVAL; + break; } return ret; @@ -380,18 +393,18 @@ int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1, /******************************************************************************* * Handler to update the reset vector for CPUs ******************************************************************************/ -int mce_update_reset_vector(void) +int32_t mce_update_reset_vector(void) { - arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); + const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); ops->update_reset_vector(mce_get_curr_cpu_ari_base()); return 0; } -static int mce_update_ccplex_gsc(tegra_ari_gsc_index_t gsc_idx) +static int32_t mce_update_ccplex_gsc(tegra_ari_gsc_index_t gsc_idx) { - arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); + const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); ops->update_ccplex_gsc(mce_get_curr_cpu_ari_base(), gsc_idx); @@ -401,7 +414,7 @@ static int mce_update_ccplex_gsc(tegra_ari_gsc_index_t gsc_idx) /******************************************************************************* * Handler to update carveout values for Video Memory Carveout region ******************************************************************************/ -int mce_update_gsc_videomem(void) +int32_t mce_update_gsc_videomem(void) { return mce_update_ccplex_gsc(TEGRA_ARI_GSC_VPR_IDX); } @@ -409,7 +422,7 @@ int mce_update_gsc_videomem(void) /******************************************************************************* * Handler to update carveout values for TZDRAM aperture ******************************************************************************/ -int mce_update_gsc_tzdram(void) +int32_t mce_update_gsc_tzdram(void) { return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZ_DRAM_IDX); } @@ -417,7 +430,7 @@ int mce_update_gsc_tzdram(void) /******************************************************************************* * Handler to update carveout values for TZ SysRAM aperture ******************************************************************************/ -int mce_update_gsc_tzram(void) +int32_t mce_update_gsc_tzram(void) { return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZRAM); } @@ -427,28 +440,29 @@ int mce_update_gsc_tzram(void) ******************************************************************************/ __dead2 void mce_enter_ccplex_state(uint32_t state_idx) { - arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); + const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); /* sanity check state value */ - if (state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF && - state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT) + if ((state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) && + (state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT)) { panic(); + } ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(), state_idx); /* wait till the CCPLEX powers down */ - for (;;) + for (;;) { ; + } - panic(); } /******************************************************************************* * Handler to issue the UPDATE_CSTATE_INFO request ******************************************************************************/ -void mce_update_cstate_info(mce_cstate_info_t *cstate) +void mce_update_cstate_info(const mce_cstate_info_t *cstate) { - arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); + const arch_mce_ops_t *ops = mce_get_curr_cpu_ops(); /* issue the UPDATE_CSTATE_INFO request */ ops->update_cstate_info(mce_get_curr_cpu_ari_base(), cstate->cluster, @@ -462,7 +476,7 @@ void mce_update_cstate_info(mce_cstate_info_t *cstate) ******************************************************************************/ void mce_verify_firmware_version(void) { - arch_mce_ops_t *ops; + const arch_mce_ops_t *ops; uint32_t cpu_ari_base; uint64_t version; uint32_t major, minor; @@ -470,37 +484,40 @@ void mce_verify_firmware_version(void) /* * MCE firmware is not supported on simulation platforms. */ - if (tegra_platform_is_emulation()) - return; + if (tegra_platform_is_emulation()) { - /* get a pointer to the CPU's arch_mce_ops_t struct */ - ops = mce_get_curr_cpu_ops(); + INFO("MCE firmware is not supported\n"); - /* get the CPU's ARI base address */ - cpu_ari_base = mce_get_curr_cpu_ari_base(); + } else { + /* get a pointer to the CPU's arch_mce_ops_t struct */ + ops = mce_get_curr_cpu_ops(); - /* - * Read the MCE firmware version and extract the major and minor - * version fields - */ - version = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION, 0); - major = (uint32_t)version; - minor = (uint32_t)(version >> 32); + /* get the CPU's ARI base address */ + cpu_ari_base = mce_get_curr_cpu_ari_base(); - INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor, - TEGRA_ARI_VERSION_MAJOR, TEGRA_ARI_VERSION_MINOR); + /* + * Read the MCE firmware version and extract the major and minor + * version fields + */ + version = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION, 0); + major = (uint32_t)version; + minor = (uint32_t)(version >> 32); - /* - * Verify that the MCE firmware version and the interface header - * match - */ - if (major != TEGRA_ARI_VERSION_MAJOR) { - ERROR("ARI major version mismatch\n"); - panic(); - } + INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor, + TEGRA_ARI_VERSION_MAJOR, TEGRA_ARI_VERSION_MINOR); - if (minor < TEGRA_ARI_VERSION_MINOR) { - ERROR("ARI minor version mismatch\n"); - panic(); + /* + * Verify that the MCE firmware version and the interface header + * match + */ + if (major != TEGRA_ARI_VERSION_MAJOR) { + ERROR("ARI major version mismatch\n"); + panic(); + } + + if (minor < TEGRA_ARI_VERSION_MINOR) { + ERROR("ARI minor version mismatch\n"); + panic(); + } } } diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c index 0be1af1a..9c115bdd 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,57 +13,63 @@ #include <sys/errno.h> #include <t18x_ari.h> -extern void nvg_set_request_data(uint64_t req, uint64_t data); -extern void nvg_set_request(uint64_t req); -extern uint64_t nvg_get_result(void); - -int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) +int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) { + int32_t ret = 0; + + (void)ari_base; + /* check for allowed power state */ - if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 && - state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) { + if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) && + (state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) { ERROR("%s: unknown cstate (%d)\n", __func__, state); - return EINVAL; - } - - /* time (TSC ticks) until the core is expected to get a wake event */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time); + ret = EINVAL; + } else { + /* time (TSC ticks) until the core is expected to get a wake event */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time); - /* set the core cstate */ - write_actlr_el1(state); + /* set the core cstate */ + write_actlr_el1(state); + } - return 0; + return ret; } /* * This request allows updating of CLUSTER_CSTATE, CCPLEX_CSTATE and * SYSTEM_CSTATE values. */ -int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, +int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, uint8_t update_wake_mask) { - uint64_t val = 0; + uint64_t val = 0ULL; + + (void)ari_base; /* update CLUSTER_CSTATE? */ - if (cluster) - val |= (cluster & CLUSTER_CSTATE_MASK) | + if (cluster != 0U) { + val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | CLUSTER_CSTATE_UPDATE_BIT; + } /* update CCPLEX_CSTATE? */ - if (ccplex) - val |= (ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT | + if (ccplex != 0U) { + val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | CCPLEX_CSTATE_UPDATE_BIT; + } /* update SYSTEM_CSTATE? */ - if (system) - val |= ((system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | - ((sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) | + if (system != 0U) { + val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | + (((uint64_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) | SYSTEM_CSTATE_UPDATE_BIT); + } /* update wake mask value? */ - if (update_wake_mask) + if (update_wake_mask != 0U) { val |= CSTATE_WAKE_MASK_UPDATE_BIT; + } /* set the wake mask */ val &= CSTATE_WAKE_MASK_CLEAR; @@ -75,46 +81,60 @@ int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, return 0; } -int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) +int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) { - /* sanity check crossover type */ - if (type > TEGRA_ARI_CROSSOVER_CCP3_SC1) - return EINVAL; + int32_t ret = 0; - /* - * The crossover threshold limit types start from - * TEGRA_CROSSOVER_TYPE_C1_C6 to TEGRA_CROSSOVER_TYPE_CCP3_SC7. The - * command indices for updating the threshold can be generated - * by adding the type to the NVG_SET_THRESHOLD_CROSSOVER_C1_C6 - * command index. - */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 + type, - (uint64_t)time); + (void)ari_base; - return 0; + /* sanity check crossover type */ + if (type > TEGRA_ARI_CROSSOVER_CCP3_SC1) { + ret = EINVAL; + } else { + /* + * The crossover threshold limit types start from + * TEGRA_CROSSOVER_TYPE_C1_C6 to TEGRA_CROSSOVER_TYPE_CCP3_SC7. + * The command indices for updating the threshold be generated + * by adding the type to the NVG_SET_THRESHOLD_CROSSOVER_C1_C6 + * command index. + */ + nvg_set_request_data((TEGRA_NVG_CHANNEL_CROSSOVER_C1_C6 + + (uint64_t)type), (uint64_t)time); + } + + return ret; } uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state) { - /* sanity check state */ - if (state == 0) - return EINVAL; + uint64_t ret; - /* - * The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES - * to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for - * reading the threshold can be generated by adding the type to - * the NVG_CLEAR_CSTATE_STATS command index. - */ - nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + state); + (void)ari_base; - return (int64_t)nvg_get_result(); + /* sanity check state */ + if (state == 0U) { + ret = EINVAL; + } else { + /* + * The cstate types start from NVG_READ_CSTATE_STATS_SC7_ENTRIES + * to NVG_GET_LAST_CSTATE_ENTRY_A57_3. The command indices for + * reading the threshold can be generated by adding the type to + * the NVG_CLEAR_CSTATE_STATS command index. + */ + nvg_set_request((TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + + (uint64_t)state)); + ret = nvg_get_result(); + } + + return ret; } -int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) +int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) { uint64_t val; + (void)ari_base; + /* * The only difference between a CSTATE_STATS_WRITE and * CSTATE_STATS_READ is the usage of the 63:32 in the request. @@ -129,71 +149,88 @@ int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) * reading the threshold can be generated by adding the type to * the NVG_CLEAR_CSTATE_STATS command index. */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + state, val); + nvg_set_request_data((TEGRA_NVG_CHANNEL_CSTATE_STATS_CLEAR + + (uint64_t)state), val); return 0; } -int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) +int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) { + (void)ari_base; + (void)state; + (void)wake_time; + /* This does not apply to the Denver cluster */ return 0; } -int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) +int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) { uint64_t val; + int32_t ret; + + (void)ari_base; /* check for allowed power state */ - if (state != TEGRA_ARI_CORE_C0 && state != TEGRA_ARI_CORE_C1 && - state != TEGRA_ARI_CORE_C6 && state != TEGRA_ARI_CORE_C7) { + if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) && + (state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) { ERROR("%s: unknown cstate (%d)\n", __func__, state); - return EINVAL; + ret = EINVAL; + } else { + /* + * Request format - + * 63:32 = wake time + * 31:0 = C-state for this core + */ + val = ((uint64_t)wake_time << MCE_SC7_WAKE_TIME_SHIFT) | + ((uint64_t)state & MCE_SC7_ALLOWED_MASK); + + /* issue command to check if SC7 is allowed */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val); + + /* 1 = SC7 allowed, 0 = SC7 not allowed */ + ret = (nvg_get_result() != 0ULL) ? 1 : 0; } - /* - * Request format - - * 63:32 = wake time - * 31:0 = C-state for this core - */ - val = ((uint64_t)wake_time << MCE_SC7_WAKE_TIME_SHIFT) | - (state & MCE_SC7_ALLOWED_MASK); - - /* issue command to check if SC7 is allowed */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val); - - /* 1 = SC7 allowed, 0 = SC7 not allowed */ - return !!nvg_get_result(); + return ret; } -int nvg_online_core(uint32_t ari_base, uint32_t core) +int32_t nvg_online_core(uint32_t ari_base, uint32_t core) { - int cpu = read_mpidr() & MPIDR_CPU_MASK; - int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; + uint64_t cpu = read_mpidr() & (uint64_t)MPIDR_CPU_MASK; + uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & + (uint64_t)MIDR_IMPL_MASK; + int32_t ret = 0; + + (void)ari_base; /* sanity check code id */ - if ((core >= MCE_CORE_ID_MAX) || (cpu == core)) { + if ((core >= (uint32_t)MCE_CORE_ID_MAX) || (cpu == core)) { ERROR("%s: unsupported core id (%d)\n", __func__, core); - return EINVAL; + ret = EINVAL; + } else { + /* + * The Denver cluster has 2 CPUs only - 0, 1. + */ + if ((impl == DENVER_IMPL) && ((core == 2U) || (core == 3U))) { + ERROR("%s: unknown core id (%d)\n", __func__, core); + ret = EINVAL; + } else { + /* get a core online */ + nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE, + ((uint64_t)core & MCE_CORE_ID_MASK)); + } } - /* - * The Denver cluster has 2 CPUs only - 0, 1. - */ - if (impl == DENVER_IMPL && ((core == 2) || (core == 3))) { - ERROR("%s: unknown core id (%d)\n", __func__, core); - return EINVAL; - } - - /* get a core online */ - nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE, core & MCE_CORE_ID_MASK); - - return 0; + return ret; } -int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) +int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) { - int val; + uint32_t val; + + (void)ari_base; /* * If the enable bit is cleared, Auto-CC3 will be disabled by setting @@ -207,9 +244,9 @@ int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable */ val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\ ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\ - (enable ? MCE_AUTO_CC3_ENABLE_BIT : 0)); + ((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U)); - nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val); + nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val); return 0; } diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index 44b99dc4..095614e4 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -256,8 +256,8 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) int tegra_soc_pwr_domain_on(u_register_t mpidr) { - int target_cpu = mpidr & MPIDR_CPU_MASK; - int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> + uint32_t target_cpu = mpidr & MPIDR_CPU_MASK; + uint32_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; if (target_cluster > MPIDR_AFFLVL1) { diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c index 151b7570..ba245790 100644 --- a/plat/nvidia/tegra/soc/t186/plat_setup.c +++ b/plat/nvidia/tegra/soc/t186/plat_setup.c @@ -22,7 +22,7 @@ #include <tegra_private.h> #include <xlat_tables.h> -DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) extern uint64_t tegra_enable_l2_ecc_parity_prot; /******************************************************************************* @@ -172,7 +172,7 @@ void plat_early_platform_setup(void) if (val >= TEGRA186_VER_A02P) { val = read_l2ctlr_el1(); - val |= L2_ECC_PARITY_PROTECTION_BIT; + val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; write_l2ctlr_el1(val); /* diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c index bcaade64..3dff6539 100644 --- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c @@ -60,7 +60,7 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, /* * System powerdown request only for afflvl 2 */ - for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) + for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S index 8a7be740..1c8aefcb 100644 --- a/plat/rockchip/common/aarch64/plat_helpers.S +++ b/plat/rockchip/common/aarch64/plat_helpers.S @@ -43,9 +43,9 @@ handler_a72: * Set the L2 Data RAM latency for Cortex-A72. * Set the L2 Tag RAM latency to for Cortex-A72. */ - mov x0, #((5 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ + mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ (0x1 << 5)) - msr L2CTLR_EL1, x0 + msr CORTEX_A72_L2CTLR_EL1, x0 isb handler_end: ret diff --git a/services/spd/tlkd/tlkd_main.c b/services/spd/tlkd/tlkd_main.c index 27488683..948be5df 100644 --- a/services/spd/tlkd/tlkd_main.c +++ b/services/spd/tlkd/tlkd_main.c @@ -37,7 +37,7 @@ tlk_context_t tlk_ctx; /******************************************************************************* * CPU number on which TLK booted up ******************************************************************************/ -static int boot_cpu; +static uint32_t boot_cpu; /* TLK UID: RFC-4122 compliant UUID (version-5, sha-1) */ DEFINE_SVC_UUID(tlk_uuid, |