1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
|
; Test load-and-trap instructions (LAT/LGAT)
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
declare void @llvm.trap()
; Check LAT with no displacement.
define i32 @f1(i32 *%ptr) {
; CHECK-LABEL: f1:
; CHECK: lat %r2, 0(%r2)
; CHECK: br %r14
entry:
%val = load i32, i32 *%ptr
%cmp = icmp eq i32 %val, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @llvm.trap()
unreachable
if.end: ; preds = %entry
ret i32 %val
}
; Check the high end of the LAT range.
define i32 @f2(i32 *%src) {
; CHECK-LABEL: f2:
; CHECK: lat %r2, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 131071
%val = load i32, i32 *%ptr
%cmp = icmp eq i32 %val, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @llvm.trap()
unreachable
if.end: ; preds = %entry
ret i32 %val
}
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f3(i32 *%src) {
; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: lat %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i32, i32 *%src, i64 131072
%val = load i32, i32 *%ptr
%cmp = icmp eq i32 %val, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @llvm.trap()
unreachable
if.end: ; preds = %entry
ret i32 %val
}
; Check that LAT allows an index.
define i32 @f4(i64 %src, i64 %index) {
; CHECK-LABEL: f4:
; CHECK: lat %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524287
%ptr = inttoptr i64 %add2 to i32 *
%val = load i32, i32 *%ptr
%cmp = icmp eq i32 %val, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @llvm.trap()
unreachable
if.end: ; preds = %entry
ret i32 %val
}
; Check LGAT with no displacement.
define i64 @f5(i64 *%ptr) {
; CHECK-LABEL: f5:
; CHECK: lgat %r2, 0(%r2)
; CHECK: br %r14
entry:
%val = load i64, i64 *%ptr
%cmp = icmp eq i64 %val, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @llvm.trap()
unreachable
if.end: ; preds = %entry
ret i64 %val
}
; Check the high end of the LGAT range.
define i64 @f6(i64 *%src) {
; CHECK-LABEL: f6:
; CHECK: lgat %r2, 524280(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%src, i64 65535
%val = load i64, i64 *%ptr
%cmp = icmp eq i64 %val, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @llvm.trap()
unreachable
if.end: ; preds = %entry
ret i64 %val
}
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 *%src) {
; CHECK-LABEL: f7:
; CHECK: agfi %r2, 524288
; CHECK: lgat %r2, 0(%r2)
; CHECK: br %r14
%ptr = getelementptr i64, i64 *%src, i64 65536
%val = load i64, i64 *%ptr
%cmp = icmp eq i64 %val, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @llvm.trap()
unreachable
if.end: ; preds = %entry
ret i64 %val
}
; Check that LGAT allows an index.
define i64 @f8(i64 %src, i64 %index) {
; CHECK-LABEL: f8:
; CHECK: lgat %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
%add2 = add i64 %add1, 524287
%ptr = inttoptr i64 %add2 to i64 *
%val = load i64, i64 *%ptr
%cmp = icmp eq i64 %val, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @llvm.trap()
unreachable
if.end: ; preds = %entry
ret i64 %val
}
|
