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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llltuc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llltuc_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
; CHECK-NEXT: sradi r3, [[REG]], 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
}
; Function Attrs: norecurse nounwind
define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llltuc_store:
; CHECK: # %bb.0: # %entry
; CHECK: sub [[REG:r[2-9]+]], r3, r4
; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
; Function Attrs: norecurse nounwind
define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llltuc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK: sub [[REG:r[0-9]+]], r3, r4
; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1
ret void
}
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