1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
|
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull(i64 %a, i64 %b) {
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: test_llgeull:
; CHECK: subfc {{r[0-9]+}}, r4, r3
; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4
; CHECK-NEXT: addi r3, [[REG1]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull_sext(i64 %a, i64 %b) {
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeull_sext
; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull_z(i64 %a) {
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeull_z
; CHECK: li r3, 1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull_sext_z(i64 %a) {
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeull_sext_z
; CHECK: li r3, -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeull_store(i64 %a, i64 %b) {
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: test_llgeull_store:
; CHECK: subfc {{r[0-9]+}}, r4, r3
; CHECK: subfe [[REG1:r[0-9]+]], r4, r4
; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeull_sext_store(i64 %a, i64 %b) {
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: @test_llgeull_sext_store
; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
; CHECK: std [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeull_z_store(i64 %a) {
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
; CHECK-LABEL: @test_llgeull_z_store
; CHECK: li [[REG1:r[0-9]+]], 1
; CHECK: std [[REG1]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeull_sext_z_store(i64 %a) {
entry:
store i64 -1, i64* @glob
ret void
; CHECK-LABEL: @test_llgeull_sext_z_store
; CHECK: li [[REG1:r[0-9]+]], -1
; CHECK: std [[REG1]]
; CHECK: blr
}
|
