1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
|
//=- ARMScheduleA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Contains all of the Cortex-A57 specific SchedWriteRes types. The approach
// below is to define a generic SchedWriteRes for every combination of
// latency and microOps. The naming conventions is to use a prefix, one field
// for latency, and one or more microOp count/type designators.
// Prefix: A57Write
// Latency: #cyc
// MicroOp Count/Types: #(B|I|M|L|S|X|W|V)
//
// e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
// 11 micro-ops to be issued as follows: one to I pipe, six to S pipes and
// four to V pipes.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Define Generic 1 micro-op types
def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
let ResourceCycles = [17]; }
def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
let ResourceCycles = [18]; }
def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
let ResourceCycles = [19]; }
def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
let ResourceCycles = [20]; }
def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
def A57Write_2cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 2; }
def A57Write_3cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 3; }
def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
def A57Write_2cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 2; }
def A57Write_3cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 3; }
def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; }
def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
let ResourceCycles = [32]; }
def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
let ResourceCycles = [32]; }
def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
let ResourceCycles = [35]; }
def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; }
// A57Write_3cyc_1L - A57Write_20cyc_1L
foreach Lat = 3-20 in {
def A57Write_#Lat#cyc_1L : SchedWriteRes<[A57UnitL]> {
let Latency = Lat;
}
}
// A57Write_4cyc_1S - A57Write_16cyc_1S
foreach Lat = 4-16 in {
def A57Write_#Lat#cyc_1S : SchedWriteRes<[A57UnitS]> {
let Latency = Lat;
}
}
def A57Write_4cyc_1M : SchedWriteRes<[A57UnitL]> { let Latency = 4; }
def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
def A57Write_4cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 4; }
def A57Write_5cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 5; }
def A57Write_6cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 6; }
def A57Write_6cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 6; }
def A57Write_8cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 8; }
def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }
def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
//===----------------------------------------------------------------------===//
// Define Generic 2 micro-op types
def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
let Latency = 64;
let NumMicroOps = 2;
let ResourceCycles = [32, 32];
}
def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
A57UnitL]> {
let Latency = 6;
let NumMicroOps = 2;
}
def A57Write_6cyc_1V_1X : SchedWriteRes<[A57UnitV,
A57UnitX]> {
let Latency = 6;
let NumMicroOps = 2;
}
def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV,
A57UnitX]> {
let Latency = 7;
let NumMicroOps = 2;
}
def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL,
A57UnitV]> {
let Latency = 8;
let NumMicroOps = 2;
}
def A57Write_9cyc_1L_1V : SchedWriteRes<[A57UnitL,
A57UnitV]> {
let Latency = 9;
let NumMicroOps = 2;
}
def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
let Latency = 9;
let NumMicroOps = 2;
}
def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
let Latency = 8;
let NumMicroOps = 2;
}
def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> {
let Latency = 6;
let NumMicroOps = 2;
}
def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
let Latency = 6;
let NumMicroOps = 2;
}
def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
let Latency = 6;
let NumMicroOps = 2;
}
def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI,
A57UnitL]> {
let Latency = 5;
let NumMicroOps = 2;
}
def A57Write_5cyc_1I_1M : SchedWriteRes<[A57UnitI,
A57UnitM]> {
let Latency = 5;
let NumMicroOps = 2;
}
def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
let Latency = 5;
let NumMicroOps = 2;
}
def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
let Latency = 5;
let NumMicroOps = 2;
}
def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL,
A57UnitV]> {
let Latency = 10;
let NumMicroOps = 2;
}
def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
let Latency = 10;
let NumMicroOps = 2;
}
def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB,
A57UnitI]> {
let Latency = 1;
let NumMicroOps = 2;
}
def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI,
A57UnitS]> {
let Latency = 1;
let NumMicroOps = 2;
}
def A57Write_1cyc_1S_1I : SchedWriteRes<[A57UnitS,
A57UnitI]> {
let Latency = 1;
let NumMicroOps = 2;
}
def A57Write_2cyc_1S_1I : SchedWriteRes<[A57UnitS,
A57UnitI]> {
let Latency = 2;
let NumMicroOps = 2;
}
def A57Write_3cyc_1S_1I : SchedWriteRes<[A57UnitS,
A57UnitI]> {
let Latency = 3;
let NumMicroOps = 2;
}
def A57Write_1cyc_1S_1M : SchedWriteRes<[A57UnitS,
A57UnitM]> {
let Latency = 1;
let NumMicroOps = 2;
}
def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB,
A57UnitI]> {
let Latency = 2;
let NumMicroOps = 2;
}
def A57Write_3cyc_1B_1I : SchedWriteRes<[A57UnitB,
A57UnitI]> {
let Latency = 3;
let NumMicroOps = 2;
}
def A57Write_6cyc_1B_1L : SchedWriteRes<[A57UnitB,
A57UnitI]> {
let Latency = 6;
let NumMicroOps = 2;
}
def A57Write_2cyc_1I_1M : SchedWriteRes<[A57UnitI,
A57UnitM]> {
let Latency = 2;
let NumMicroOps = 2;
}
def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> {
let Latency = 2;
let NumMicroOps = 2;
}
def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
let Latency = 2;
let NumMicroOps = 2;
}
def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
let Latency = 36;
let NumMicroOps = 2;
let ResourceCycles = [18, 18];
}
def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
A57UnitM]> {
let Latency = 3;
let NumMicroOps = 2;
}
def A57Write_4cyc_1I_1M : SchedWriteRes<[A57UnitI,
A57UnitM]> {
let Latency = 4;
let NumMicroOps = 2;
}
// A57Write_3cyc_1L_1I - A57Write_20cyc_1L_1I
foreach Lat = 3-20 in {
def A57Write_#Lat#cyc_1L_1I : SchedWriteRes<[A57UnitL, A57UnitI]> {
let Latency = Lat; let NumMicroOps = 2;
}
}
def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI,
A57UnitS]> {
let Latency = 3;
let NumMicroOps = 2;
}
def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS,
A57UnitV]> {
let Latency = 3;
let NumMicroOps = 2;
}
def A57Write_4cyc_1S_1V : SchedWriteRes<[A57UnitS,
A57UnitV]> {
let Latency = 4;
let NumMicroOps = 2;
}
def A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
let Latency = 3;
let NumMicroOps = 2;
}
// A57Write_4cyc_1S_1I - A57Write_16cyc_1S_1I
foreach Lat = 4-16 in {
def A57Write_#Lat#cyc_1S_1I : SchedWriteRes<[A57UnitS, A57UnitI]> {
let Latency = Lat; let NumMicroOps = 2;
}
}
def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
let Latency = 4;
let NumMicroOps = 2;
}
//===----------------------------------------------------------------------===//
// Define Generic 3 micro-op types
def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
let Latency = 10;
let NumMicroOps = 3;
}
def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI,
A57UnitS, A57UnitS]> {
let Latency = 2;
let NumMicroOps = 3;
}
def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI,
A57UnitS,
A57UnitV]> {
let Latency = 3;
let NumMicroOps = 3;
}
def A57Write_3cyc_1S_1V_1I : SchedWriteRes<[A57UnitS,
A57UnitV,
A57UnitI]> {
let Latency = 3;
let NumMicroOps = 3;
}
def A57Write_4cyc_1S_1V_1I : SchedWriteRes<[A57UnitS,
A57UnitV,
A57UnitI]> {
let Latency = 4;
let NumMicroOps = 3;
}
def A57Write_4cyc_1I_1L_1M : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitM]> {
let Latency = 4;
let NumMicroOps = 3;
}
def A57Write_8cyc_1L_1V_1I : SchedWriteRes<[A57UnitL,
A57UnitV,
A57UnitI]> {
let Latency = 8;
let NumMicroOps = 3;
}
def A57Write_9cyc_1L_1V_1I : SchedWriteRes<[A57UnitL,
A57UnitV,
A57UnitI]> {
let Latency = 9;
let NumMicroOps = 3;
}
|
