1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
|
//===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file defines all the static objects used by AMDGPURegisterBankInfo.
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
namespace llvm {
namespace AMDGPU {
enum PartialMappingIdx {
None = - 1,
PM_SGPR1 = 0,
PM_SGPR16 = 4,
PM_SGPR32 = 5,
PM_SGPR64 = 6,
PM_SGPR128 = 7,
PM_SGPR256 = 8,
PM_SGPR512 = 9,
PM_VGPR1 = 10,
PM_VGPR16 = 14,
PM_VGPR32 = 15,
PM_VGPR64 = 16,
PM_VGPR128 = 17,
PM_VGPR256 = 18,
PM_VGPR512 = 19,
PM_SGPR96 = 20,
PM_VGPR96 = 21
};
const RegisterBankInfo::PartialMapping PartMappings[] {
// StartIdx, Length, RegBank
{0, 1, SCCRegBank},
{0, 16, SGPRRegBank},
{0, 32, SGPRRegBank},
{0, 64, SGPRRegBank},
{0, 128, SGPRRegBank},
{0, 256, SGPRRegBank},
{0, 512, SGPRRegBank},
{0, 1, SGPRRegBank},
{0, 16, VGPRRegBank},
{0, 32, VGPRRegBank},
{0, 64, VGPRRegBank},
{0, 128, VGPRRegBank},
{0, 256, VGPRRegBank},
{0, 512, VGPRRegBank},
{0, 96, SGPRRegBank},
{0, 96, VGPRRegBank},
};
const RegisterBankInfo::ValueMapping ValMappings[] {
{&PartMappings[0], 1},
{nullptr, 0},
{nullptr, 0},
{nullptr, 0},
{&PartMappings[1], 1},
{&PartMappings[2], 1},
{&PartMappings[3], 1},
{&PartMappings[4], 1},
{&PartMappings[5], 1},
{&PartMappings[6], 1},
{&PartMappings[7], 1},
{nullptr, 0},
{nullptr, 0},
{nullptr, 0},
{&PartMappings[8], 1},
{&PartMappings[9], 1},
{&PartMappings[10], 1},
{&PartMappings[11], 1},
{&PartMappings[12], 1},
{&PartMappings[13], 1},
{&PartMappings[14], 1},
{&PartMappings[15], 1}
};
enum ValueMappingIdx {
SGPRStartIdx = 0,
VGPRStartIdx = 10
};
const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
unsigned Size) {
unsigned Idx;
switch (Size) {
case 1:
Idx = BankID == AMDGPU::SCCRegBankID ? PM_SGPR1 : PM_VGPR1;
break;
case 96:
Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;
break;
default:
Idx = BankID == AMDGPU::VGPRRegBankID ? VGPRStartIdx : SGPRStartIdx;
Idx += Log2_32_Ceil(Size);
break;
}
return &ValMappings[Idx];
}
} // End AMDGPU namespace.
} // End llvm namespace.
|
