# RUN: llc -run-pass x86-domain-reassignment -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq -o - %s | FileCheck %s
--- |
  ; ModuleID = '../test/CodeGen/X86/gpr-to-mask.ll'
  source_filename = "../test/CodeGen/X86/gpr-to-mask.ll"
  target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
  target triple = "x86_64-unknown-unknown"
  
  define void @test_fcmp_storefloat(i1 %cond, float* %fptr, float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) #0 {
  entry:
    br i1 %cond, label %if, label %else
  
  if:                                               ; preds = %entry
    %cmp1 = fcmp oeq float %f3, %f4
    br label %exit
  
  else:                                             ; preds = %entry
    %cmp2 = fcmp oeq float %f5, %f6
    br label %exit
  
  exit:                                             ; preds = %else, %if
    %val = phi i1 [ %cmp1, %if ], [ %cmp2, %else ]
    %selected = select i1 %val, float %f1, float %f2
    store float %selected, float* %fptr
    ret void
  }

  define void @test_8bitops() #0 {
    ret void
  }
  define void @test_16bitops() #0 {
    ret void
  }
  define void @test_32bitops() #0 {
    ret void
  }
  define void @test_64bitops() #0 {
    ret void
  }
  define void @test_16bitext() #0 {
    ret void
  }
  define void @test_32bitext() #0 {
    ret void
  }
  define void @test_64bitext() #0 {
    ret void
  }
...
---
name:            test_fcmp_storefloat
# CHECK-LABEL: name: test_fcmp_storefloat
alignment:       4
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:       
  - { id: 0, class: gr8, preferred-register: '' }
  - { id: 1, class: gr8, preferred-register: '' }
  - { id: 2, class: gr8, preferred-register: '' }
  - { id: 3, class: gr32, preferred-register: '' }
  - { id: 4, class: gr64, preferred-register: '' }
  - { id: 5, class: vr128x, preferred-register: '' }
  - { id: 6, class: fr32x, preferred-register: '' }
  - { id: 7, class: fr32x, preferred-register: '' }
  - { id: 8, class: fr32x, preferred-register: '' }
  - { id: 9, class: fr32x, preferred-register: '' }
  - { id: 10, class: fr32x, preferred-register: '' }
  - { id: 11, class: gr8, preferred-register: '' }
  - { id: 12, class: vk1, preferred-register: '' }
  - { id: 13, class: gr32, preferred-register: '' }
  - { id: 14, class: vk1, preferred-register: '' }
  - { id: 15, class: gr32, preferred-register: '' }
  - { id: 16, class: gr32, preferred-register: '' }
  - { id: 17, class: gr32, preferred-register: '' }
  - { id: 18, class: vk1wm, preferred-register: '' }
  - { id: 19, class: vr128x, preferred-register: '' }
  - { id: 20, class: fr128, preferred-register: '' }
  - { id: 21, class: fr128, preferred-register: '' }
  - { id: 22, class: fr32x, preferred-register: '' }
liveins:         
  - { reg: '%edi', virtual-reg: '%3' }
  - { reg: '%rsi', virtual-reg: '%4' }
  - { reg: '%xmm0', virtual-reg: '%5' }
  - { reg: '%xmm1', virtual-reg: '%6' }
  - { reg: '%xmm2', virtual-reg: '%7' }
  - { reg: '%xmm3', virtual-reg: '%8' }
  - { reg: '%xmm4', virtual-reg: '%9' }
  - { reg: '%xmm5', virtual-reg: '%10' }
frameInfo:       
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    0
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 4294967295
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  savePoint:       ''
  restorePoint:    ''
fixedStack:      
stack:           
constants:       
body:             |
  bb.0.entry:
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: %edi, %rsi, %xmm0, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5
  
    %10 = COPY %xmm5
    %9 = COPY %xmm4
    %8 = COPY %xmm3
    %7 = COPY %xmm2
    %6 = COPY %xmm1
    %5 = COPY %xmm0
    %4 = COPY %rsi
    %3 = COPY %edi
    %11 = COPY %3.sub_8bit
    TEST8ri killed %11, 1, implicit-def %eflags
    JE_1 %bb.2, implicit %eflags
    JMP_1 %bb.1
  
  bb.1.if:
    successors: %bb.3(0x80000000)
  
    %14 = VCMPSSZrr %7, %8, 0

    ; check that cross domain copies are replaced with same domain copies.
    ; CHECK: %15:vk32 = COPY %14
    ; CHECK: %0:vk8 = COPY %15
    
    %15 = COPY %14
    %0 = COPY %15.sub_8bit
    JMP_1 %bb.3
  
  bb.2.else:
    successors: %bb.3(0x80000000)
    %12 = VCMPSSZrr %9, %10, 0

    ; check that cross domain copies are replaced with same domain copies.
    ; CHECK: %13:vk32 = COPY %12
    ; CHECK: %1:vk8 = COPY %13

    %13 = COPY %12
    %1 = COPY %13.sub_8bit
  
  bb.3.exit:

    ; check PHI, IMPLICIT_DEF, and INSERT_SUBREG replacers.
    ; CHECK: %2:vk8 = PHI %1, %bb.2, %0, %bb.1
    ; CHECK: %16:vk32 = COPY %2
    ; CHECK: %18:vk1wm = COPY %16
  
    %2 = PHI %1, %bb.2, %0, %bb.1
    %17 = IMPLICIT_DEF
    %16 = INSERT_SUBREG %17, %2, 1
    %18 = COPY %16
    %19 = COPY %6
    %21 = IMPLICIT_DEF
    %20 = VMOVSSZrrk %19, killed %18, killed %21, %5
    %22 = COPY %20
    VMOVSSZmr %4, 1, %noreg, 0, %noreg, killed %22 :: (store 4 into %ir.fptr)
    RET 0

...
---
name:            test_8bitops
# CHECK-LABEL: name: test_8bitops
alignment:       4
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:       
  - { id: 0, class: gr64, preferred-register: '' }
  - { id: 1, class: vr512, preferred-register: '' }
  - { id: 2, class: vr512, preferred-register: '' }
  - { id: 3, class: vr512, preferred-register: '' }
  - { id: 4, class: vr512, preferred-register: '' }
  - { id: 5, class: vk8, preferred-register: '' }
  - { id: 6, class: gr32, preferred-register: '' }
  - { id: 7, class: gr8, preferred-register: '' }
  - { id: 8, class: gr32, preferred-register: '' }
  - { id: 9, class: gr32, preferred-register: '' }
  - { id: 10, class: vk8wm, preferred-register: '' }
  - { id: 11, class: vr512, preferred-register: '' }
  - { id: 12, class: gr8, preferred-register: '' }
  - { id: 13, class: gr8, preferred-register: '' }
  - { id: 14, class: gr8, preferred-register: '' }
  - { id: 15, class: gr8, preferred-register: '' }
  - { id: 16, class: gr8, preferred-register: '' }
  - { id: 17, class: gr8, preferred-register: '' }
  - { id: 18, class: gr8, preferred-register: '' }
liveins:         
  - { reg: '%rdi', virtual-reg: '%0' }
  - { reg: '%zmm0', virtual-reg: '%1' }
  - { reg: '%zmm1', virtual-reg: '%2' }
  - { reg: '%zmm2', virtual-reg: '%3' }
  - { reg: '%zmm3', virtual-reg: '%4' }
frameInfo:       
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    0
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 4294967295
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  savePoint:       ''
  restorePoint:    ''
fixedStack:      
stack:           
constants:       
body:             |
  bb.0:
    liveins: %rdi, %zmm0, %zmm1, %zmm2, %zmm3
  
    %0 = COPY %rdi
    %1 = COPY %zmm0
    %2 = COPY %zmm1
    %3 = COPY %zmm2
    %4 = COPY %zmm3
  
    %5 = VCMPPDZrri %3, %4, 0
    ; CHECK: %6:vk32 = COPY %5
    ; CHECK: %7:vk8 = COPY %6
    %6 = COPY %5
    %7 = COPY %6.sub_8bit

    ; CHECK: %12:vk8 = KSHIFTRBri %7, 2
    ; CHECK: %13:vk8 = KSHIFTLBri %12, 1
    ; CHECK: %14:vk8 = KNOTBrr %13
    ; CHECK: %15:vk8 = KORBrr %14, %12
    ; CHECK: %16:vk8 = KANDBrr %15, %13
    ; CHECK: %17:vk8 = KXORBrr %16, %12
    ; CHECK: %18:vk8 = KADDBrr %17, %14
    %12 = SHR8ri %7, 2, implicit-def dead %eflags
    %13 = SHL8ri %12, 1, implicit-def dead %eflags
    %14 = NOT8r %13
    %15 = OR8rr %14, %12, implicit-def dead %eflags
    %16 = AND8rr %15, %13, implicit-def dead %eflags
    %17 = XOR8rr %16, %12, implicit-def dead %eflags
    %18 = ADD8rr %17, %14, implicit-def dead %eflags
  
    ; CHECK: %9:vk32 = COPY %18
    ; CHECK: %10:vk8wm = COPY %9
    %8 = IMPLICIT_DEF
    %9 = INSERT_SUBREG %8, %18, 1
    %10 = COPY %9
    %11 = VMOVAPDZrrk %2, killed %10, %1
    VMOVAPDZmr %0, 1, %noreg, 0, %noreg, killed %11 

    ; CHECK: KTESTBrr %18, %18, implicit-def %eflags
    TEST8rr %18, %18, implicit-def %eflags
    JE_1 %bb.1, implicit %eflags
    JMP_1 %bb.2

  bb.1:

  bb.2:
    RET 0

...
---
name:            test_16bitops
# CHECK-LABEL: name: test_16bitops
alignment:       4
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:       
  - { id: 0, class: gr64, preferred-register: '' }
  - { id: 1, class: vr512, preferred-register: '' }
  - { id: 2, class: vr512, preferred-register: '' }
  - { id: 3, class: vr512, preferred-register: '' }
  - { id: 4, class: vr512, preferred-register: '' }
  - { id: 5, class: vk16, preferred-register: '' }
  - { id: 6, class: gr32, preferred-register: '' }
  - { id: 7, class: gr16, preferred-register: '' }
  - { id: 8, class: gr32, preferred-register: '' }
  - { id: 9, class: gr32, preferred-register: '' }
  - { id: 10, class: vk16wm, preferred-register: '' }
  - { id: 11, class: vr512, preferred-register: '' }
  - { id: 12, class: gr16, preferred-register: '' }
  - { id: 13, class: gr16, preferred-register: '' }
  - { id: 14, class: gr16, preferred-register: '' }
  - { id: 15, class: gr16, preferred-register: '' }
  - { id: 16, class: gr16, preferred-register: '' }
  - { id: 17, class: gr16, preferred-register: '' }
liveins:         
  - { reg: '%rdi', virtual-reg: '%0' }
  - { reg: '%zmm0', virtual-reg: '%1' }
  - { reg: '%zmm1', virtual-reg: '%2' }
  - { reg: '%zmm2', virtual-reg: '%3' }
  - { reg: '%zmm3', virtual-reg: '%4' }
frameInfo:       
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    0
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 4294967295
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  savePoint:       ''
  restorePoint:    ''
fixedStack:      
stack:           
constants:       
body:             |
  bb.0:
    liveins: %rdi, %zmm0, %zmm1, %zmm2, %zmm3
  
    %0 = COPY %rdi
    %1 = COPY %zmm0
    %2 = COPY %zmm1
    %3 = COPY %zmm2
    %4 = COPY %zmm3
  
    %5 = VCMPPSZrri %3, %4, 0
    ; CHECK: %6:vk32 = COPY %5
    ; CHECK: %7:vk16 = COPY %6
    %6 = COPY %5
    %7 = COPY %6.sub_16bit

    ; CHECK: %12:vk16 = KSHIFTRWri %7, 2
    ; CHECK: %13:vk16 = KSHIFTLWri %12, 1
    ; CHECK: %14:vk16 = KNOTWrr %13
    ; CHECK: %15:vk16 = KORWrr %14, %12
    ; CHECK: %16:vk16 = KANDWrr %15, %13
    ; CHECK: %17:vk16 = KXORWrr %16, %12
    %12 = SHR16ri %7, 2, implicit-def dead %eflags
    %13 = SHL16ri %12, 1, implicit-def dead %eflags
    %14 = NOT16r %13
    %15 = OR16rr %14, %12, implicit-def dead %eflags
    %16 = AND16rr %15, %13, implicit-def dead %eflags
    %17 = XOR16rr %16, %12, implicit-def dead %eflags
  
    ; CHECK: %9:vk32 = COPY %17
    ; CHECK: %10:vk16wm = COPY %9
    %8 = IMPLICIT_DEF
    %9 = INSERT_SUBREG %8, %17, 3
    %10 = COPY %9
    %11 = VMOVAPSZrrk %2, killed %10, %1
    VMOVAPSZmr %0, 1, %noreg, 0, %noreg, killed %11 

    ; CHECK: KTESTWrr %17, %17, implicit-def %eflags
    TEST16rr %17, %17, implicit-def %eflags
    JE_1 %bb.1, implicit %eflags
    JMP_1 %bb.2

  bb.1:

  bb.2:
    RET 0

...
---
name:            test_32bitops
# CHECK-LABEL: name: test_32bitops
alignment:       4
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:       
  - { id: 0, class: gr64, preferred-register: '' }
  - { id: 1, class: vr512, preferred-register: '' }
  - { id: 2, class: vr512, preferred-register: '' }
  - { id: 3, class: vk32wm, preferred-register: '' }
  - { id: 4, class: vr512, preferred-register: '' }
  - { id: 5, class: gr32, preferred-register: '' }
  - { id: 6, class: gr32, preferred-register: '' }
  - { id: 7, class: gr32, preferred-register: '' }
  - { id: 8, class: gr32, preferred-register: '' }
  - { id: 9, class: gr32, preferred-register: '' }
  - { id: 10, class: gr32, preferred-register: '' }
  - { id: 11, class: gr32, preferred-register: '' }
  - { id: 12, class: gr32, preferred-register: '' }
  - { id: 13, class: gr32, preferred-register: '' }
liveins:         
  - { reg: '%rdi', virtual-reg: '%0' }
  - { reg: '%zmm0', virtual-reg: '%1' }
  - { reg: '%zmm1', virtual-reg: '%2' }
frameInfo:       
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    0
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 4294967295
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  savePoint:       ''
  restorePoint:    ''
fixedStack:      
stack:           
constants:       
body:             |
  bb.0:
    liveins: %rdi, %zmm0, %zmm1
  
    %0 = COPY %rdi
    %1 = COPY %zmm0
    %2 = COPY %zmm1
  
    ; CHECK: %5:vk32 = KMOVDkm %0, 1, %noreg, 0, %noreg
    ; CHECK: %6:vk32 = KSHIFTRDri %5, 2
    ; CHECK: %7:vk32 = KSHIFTLDri %6, 1
    ; CHECK: %8:vk32 = KNOTDrr %7
    ; CHECK: %9:vk32 = KORDrr %8, %6
    ; CHECK: %10:vk32 = KANDDrr %9, %7
    ; CHECK: %11:vk32 = KXORDrr %10, %6
    ; CHECK: %12:vk32 = KANDNDrr %11, %9
    ; CHECK: %13:vk32 = KADDDrr %12, %11
    %5 = MOV32rm %0, 1, %noreg, 0, %noreg
    %6 = SHR32ri %5, 2, implicit-def dead %eflags
    %7 = SHL32ri %6, 1, implicit-def dead %eflags
    %8 = NOT32r %7
    %9 = OR32rr %8, %6, implicit-def dead %eflags
    %10 = AND32rr %9, %7, implicit-def dead %eflags
    %11 = XOR32rr %10, %6, implicit-def dead %eflags
    %12 = ANDN32rr %11, %9, implicit-def dead %eflags
    %13 = ADD32rr %12, %11, implicit-def dead %eflags
  
    ; CHECK: %3:vk32wm = COPY %13
    %3 = COPY %13
    %4 = VMOVDQU16Zrrk %2, killed %3, %1
    VMOVDQA32Zmr %0, 1, %noreg, 0, %noreg, killed %4

    ; CHECK: KTESTDrr %13, %13, implicit-def %eflags
    TEST32rr %13, %13, implicit-def %eflags
    JE_1 %bb.1, implicit %eflags
    JMP_1 %bb.2

  bb.1:

  bb.2:
    RET 0

...
---
name:            test_64bitops
# CHECK-LABEL: name: test_64bitops
alignment:       4
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:       
  - { id: 0, class: gr64, preferred-register: '' }
  - { id: 1, class: vr512, preferred-register: '' }
  - { id: 2, class: vr512, preferred-register: '' }
  - { id: 3, class: vk64wm, preferred-register: '' }
  - { id: 4, class: vr512, preferred-register: '' }
  - { id: 5, class: gr64, preferred-register: '' }
  - { id: 6, class: gr64, preferred-register: '' }
  - { id: 7, class: gr64, preferred-register: '' }
  - { id: 8, class: gr64, preferred-register: '' }
  - { id: 9, class: gr64, preferred-register: '' }
  - { id: 10, class: gr64, preferred-register: '' }
  - { id: 11, class: gr64, preferred-register: '' }
  - { id: 12, class: gr64, preferred-register: '' }
  - { id: 13, class: gr64, preferred-register: '' }
liveins:         
  - { reg: '%rdi', virtual-reg: '%0' }
  - { reg: '%zmm0', virtual-reg: '%1' }
  - { reg: '%zmm1', virtual-reg: '%2' }
frameInfo:       
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    0
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 4294967295
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  savePoint:       ''
  restorePoint:    ''
fixedStack:      
stack:           
constants:       
body:             |
  bb.0:
    liveins: %rdi, %zmm0, %zmm1
  
    %0 = COPY %rdi
    %1 = COPY %zmm0
    %2 = COPY %zmm1
  
    ; CHECK: %5:vk64 = KMOVQkm %0, 1, %noreg, 0, %noreg
    ; CHECK: %6:vk64 = KSHIFTRQri %5, 2
    ; CHECK: %7:vk64 = KSHIFTLQri %6, 1
    ; CHECK: %8:vk64 = KNOTQrr %7
    ; CHECK: %9:vk64 = KORQrr %8, %6
    ; CHECK: %10:vk64 = KANDQrr %9, %7
    ; CHECK: %11:vk64 = KXORQrr %10, %6
    ; CHECK: %12:vk64 = KANDNQrr %11, %9
    ; CHECK: %13:vk64 = KADDQrr %12, %11
    %5 = MOV64rm %0, 1, %noreg, 0, %noreg
    %6 = SHR64ri %5, 2, implicit-def dead %eflags
    %7 = SHL64ri %6, 1, implicit-def dead %eflags
    %8 = NOT64r %7
    %9 = OR64rr %8, %6, implicit-def dead %eflags
    %10 = AND64rr %9, %7, implicit-def dead %eflags
    %11 = XOR64rr %10, %6, implicit-def dead %eflags
    %12 = ANDN64rr %11, %9, implicit-def dead %eflags
    %13 = ADD64rr %12, %11, implicit-def dead %eflags
  
    ; CHECK: %3:vk64wm = COPY %13
    %3 = COPY %13
    %4 = VMOVDQU8Zrrk %2, killed %3, %1
    VMOVDQA32Zmr %0, 1, %noreg, 0, %noreg, killed %4

    ; CHECK: KTESTQrr %13, %13, implicit-def %eflags
    TEST64rr %13, %13, implicit-def %eflags
    JE_1 %bb.1, implicit %eflags
    JMP_1 %bb.2

  bb.1:

  bb.2:
    RET 0

...
---
name:            test_16bitext
# CHECK-LABEL: name: test_16bitext
alignment:       4
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:       
  - { id: 0, class: gr64, preferred-register: '' }
  - { id: 1, class: vr512, preferred-register: '' }
  - { id: 2, class: vr512, preferred-register: '' }
  - { id: 3, class: vk16wm, preferred-register: '' }
  - { id: 4, class: vr512, preferred-register: '' }
  - { id: 5, class: gr16, preferred-register: '' }
  - { id: 6, class: gr16, preferred-register: '' }
liveins:         
  - { reg: '%rdi', virtual-reg: '%0' }
  - { reg: '%zmm0', virtual-reg: '%1' }
  - { reg: '%zmm1', virtual-reg: '%2' }
frameInfo:       
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    0
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 4294967295
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  savePoint:       ''
  restorePoint:    ''
fixedStack:      
stack:           
constants:       
body:             |
  bb.0:
    liveins: %rdi, %zmm0, %zmm1
  
    %0 = COPY %rdi
    %1 = COPY %zmm0
    %2 = COPY %zmm1
  
    ; CHECK: %7:vk8 = KMOVBkm %0, 1, %noreg, 0, %noreg
    ; CHECK: %5:vk16 = COPY %7
    ; CHECK: %6:vk16 = KNOTWrr %5
    %5 = MOVZX16rm8 %0, 1, %noreg, 0, %noreg
    %6 = NOT16r %5

    ; CHECK: %3:vk16wm = COPY %6
    %3 = COPY %6
    %4 = VMOVAPSZrrk %2, killed %3, %1
    VMOVAPSZmr %0, 1, %noreg, 0, %noreg, killed %4
    RET 0

...
---
name:            test_32bitext
# CHECK-LABEL: name: test_32bitext
alignment:       4
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:       
  - { id: 0, class: gr64, preferred-register: '' }
  - { id: 1, class: vr512, preferred-register: '' }
  - { id: 2, class: vr512, preferred-register: '' }
  - { id: 3, class: vk64wm, preferred-register: '' }
  - { id: 4, class: vr512, preferred-register: '' }
  - { id: 5, class: gr32, preferred-register: '' }
  - { id: 6, class: gr32, preferred-register: '' }
  - { id: 7, class: gr32, preferred-register: '' }
liveins:         
  - { reg: '%rdi', virtual-reg: '%0' }
  - { reg: '%zmm0', virtual-reg: '%1' }
  - { reg: '%zmm1', virtual-reg: '%2' }
frameInfo:       
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    0
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 4294967295
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  savePoint:       ''
  restorePoint:    ''
fixedStack:      
stack:           
constants:       
body:             |
  bb.0:
    liveins: %rdi, %zmm0, %zmm1
  
    %0 = COPY %rdi
    %1 = COPY %zmm0
    %2 = COPY %zmm1
  
    ; CHECK: %8:vk8 = KMOVBkm %0, 1, %noreg, 0, %noreg
    ; CHECK: %5:vk32 = COPY %8
    ; CHECK: %9:vk16 = KMOVWkm %0, 1, %noreg, 0, %noreg
    ; CHECK: %6:vk32 = COPY %9
    ; CHECK: %7:vk32 = KADDDrr %5, %6
    %5 = MOVZX32rm8 %0, 1, %noreg, 0, %noreg
    %6 = MOVZX32rm16 %0, 1, %noreg, 0, %noreg
    %7 = ADD32rr %5, %6, implicit-def dead %eflags

    ; CHECK: %3:vk64wm = COPY %7
    %3 = COPY %7
    %4 = VMOVDQU16Zrrk %2, killed %3, %1
    VMOVDQA32Zmr %0, 1, %noreg, 0, %noreg, killed %4
    RET 0

...
---
name:            test_64bitext
# CHECK-LABEL: name: test_64bitext
alignment:       4
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:       
  - { id: 0, class: gr64, preferred-register: '' }
  - { id: 1, class: vr512, preferred-register: '' }
  - { id: 2, class: vr512, preferred-register: '' }
  - { id: 3, class: vk64wm, preferred-register: '' }
  - { id: 4, class: vr512, preferred-register: '' }
  - { id: 5, class: gr64, preferred-register: '' }
  - { id: 6, class: gr64, preferred-register: '' }
  - { id: 7, class: gr64, preferred-register: '' }
liveins:         
  - { reg: '%rdi', virtual-reg: '%0' }
  - { reg: '%zmm0', virtual-reg: '%1' }
  - { reg: '%zmm1', virtual-reg: '%2' }
frameInfo:       
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    0
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 4294967295
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  savePoint:       ''
  restorePoint:    ''
fixedStack:      
stack:           
constants:       
body:             |
  bb.0:
    liveins: %rdi, %zmm0, %zmm1
  
    %0 = COPY %rdi
    %1 = COPY %zmm0
    %2 = COPY %zmm1
  
    ; CHECK: %8:vk8 = KMOVBkm %0, 1, %noreg, 0, %noreg
    ; CHECK: %5:vk64 = COPY %8
    ; CHECK: %9:vk16 = KMOVWkm %0, 1, %noreg, 0, %noreg
    ; CHECK: %6:vk64 = COPY %9
    ; CHECK: %7:vk64 = KADDQrr %5, %6
    %5 = MOVZX64rm8 %0, 1, %noreg, 0, %noreg
    %6 = MOVZX64rm16 %0, 1, %noreg, 0, %noreg
    %7 = ADD64rr %5, %6, implicit-def dead %eflags

    ; CHECK: %3:vk64wm = COPY %7
    %3 = COPY %7
    %4 = VMOVDQU8Zrrk %2, killed %3, %1
    VMOVDQA32Zmr %0, 1, %noreg, 0, %noreg, killed %4
    RET 0

...