; RUN: llc -march=hexagon < %s | FileCheck %s ; This testcase is to check that we use REG_SEQUENCE for reordering whole ; vectors. ; Note: some of the vcombines generated are unnecessary. If the codegen ; improves to eliminate them, this testcase will need to be updated. ; CHECK-LABEL: test_00: ; CHECK: v1 = v0 ; Result: v1:0 = vcombine(v0,v0) define <128 x i8> @test_00(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_01: ; CHECK-NOT: = ; Result: v1:0 = vcombine(v1,v0) define <128 x i8> @test_01(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_02: ; CHECK: v1 = v2 ; Result: v1:0 = vcombine(v2,v0) define <128 x i8> @test_02(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_03: ; CHECK: v1 = v3 ; Result: v1:0 = vcombine(v3,v0) define <128 x i8> @test_03(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_10: ; CHECK: vcombine(v0,v1) ; Result: v1:0 = vcombine(v0,v1) define <128 x i8> @test_10(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_11: ; CHECK: v0 = v1 ; Result: v1:0 = vcombine(v1,v1) define <128 x i8> @test_11(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_12: ; CHECK: vcombine(v2,v1) ; Result: v1:0 = vcombine(v2,v1) define <128 x i8> @test_12(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_13: ; CHECK: v2 = v1 ; CHECK: vcombine(v3,v2) ; Result: v1:0 = vcombine(v3,v1) define <128 x i8> @test_13(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_20: ; CHECK: v3 = v0 ; CHECK: vcombine(v3,v2) ; Result: v1:0 = vcombine(v0,v2) define <128 x i8> @test_20(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_21: ; CHECK: v3 = v1 ; CHECK: vcombine(v3,v2) ; Result: v1:0 = vcombine(v1,v2) define <128 x i8> @test_21(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_22: ; CHECK: v3 = v2 ; CHECK: vcombine(v3,v2) ; Result: v1:0 = vcombine(v2,v2) define <128 x i8> @test_22(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_23: ; CHECK: vcombine(v3,v2) ; Result: v1:0 = vcombine(v3,v2) define <128 x i8> @test_23(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_30: ; CHECK: vcombine(v0,v3) ; Result: v1:0 = vcombine(v0,v3) define <128 x i8> @test_30(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_31: ; CHECK: v0 = v3 ; Result: v1:0 = vcombine(v1,v3) define <128 x i8> @test_31(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_32: ; CHECK: vcombine(v2,v3) ; Result: v1:0 = vcombine(v2,v3) define <128 x i8> @test_32(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } ; CHECK-LABEL: test_33: ; CHECK: v2 = v3 ; CHECK: vcombine(v3,v2) ; Result: v1:0 = vcombine(v3,v3) define <128 x i8> @test_33(<128 x i8> %a0, <128 x i8> %a1) #0 { b2: %v3 = shufflevector <128 x i8> %a0, <128 x i8> %a1, <128 x i32> ret <128 x i8> %v3 } attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }