# RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_mla() #0 { ret void } define void @test_mla_commutative() #0 { ret void } define void @test_mla_v5() #1 { ret void } define void @test_mls() #2 { ret void } define void @test_no_mls() { ret void } define void @test_shifts_to_revsh() #0 { ret void } define void @test_shifts_to_revsh_commutative() #0 { ret void } define void @test_shifts_no_revsh_features() #1 { ret void } define void @test_shifts_no_revsh_constants() #0 { ret void } define void @test_bicrr() { ret void } define void @test_bicrr_commutative() { ret void } define void @test_bicri() { ret void } define void @test_bicri_commutative_xor() { ret void } define void @test_bicri_commutative_and() { ret void } define void @test_bicri_commutative_both() { ret void } define void @test_pkhbt() #0 { ret void } define void @test_pkhbt_commutative() #0 { ret void } define void @test_pkhbt_imm16_31() #0 { ret void } define void @test_pkhbt_unshifted() #0 { ret void } define void @test_pkhtb_imm16() #0 { ret void } define void @test_pkhtb_imm1_15() #0 { ret void } define void @test_movti16_0xffff() #2 { ret void } attributes #0 = { "target-features"="+v6" } attributes #1 = { "target-features"="-v6" } attributes #2 = { "target-features"="+v6t2" } ... --- name: test_mla # CHECK-LABEL: name: test_mla legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } body: | bb.0: liveins: %r0, %r1, %r2 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s32) = COPY %r2 ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2 %3(s32) = G_MUL %0, %1 %4(s32) = G_ADD %3, %2 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_mla_commutative # CHECK-LABEL: name: test_mla_commutative legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } body: | bb.0: liveins: %r0, %r1, %r2 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s32) = COPY %r2 ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2 %3(s32) = G_MUL %0, %1 %4(s32) = G_ADD %2, %3 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_mla_v5 # CHECK-LABEL: name: test_mla_v5 legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } body: | bb.0: liveins: %r0, %r1, %r2 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s32) = COPY %r2 ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY %r2 %3(s32) = G_MUL %0, %1 %4(s32) = G_ADD %3, %2 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_mls # CHECK-LABEL: name: test_mls legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } body: | bb.0: liveins: %r0, %r1, %r2 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s32) = COPY %r2 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY %r2 %3(s32) = G_MUL %0, %1 %4(s32) = G_SUB %2, %3 ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_no_mls # CHECK-LABEL: name: test_no_mls legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } body: | bb.0: liveins: %r0, %r1, %r2 %0(s32) = COPY %r0 %1(s32) = COPY %r1 %2(s32) = COPY %r2 ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY %r2 %3(s32) = G_MUL %0, %1 %4(s32) = G_SUB %2, %3 ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, %noreg, %noreg ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_shifts_to_revsh # CHECK-LABEL: name: test_shifts_to_revsh legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } - { id: 5, class: gprb } - { id: 6, class: gprb } - { id: 7, class: gprb } - { id: 8, class: gprb } - { id: 9, class: gprb } body: | bb.0: liveins: %r0 %0(s32) = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 %1(s32) = G_CONSTANT i32 24 %2(s32) = G_SHL %0(s32), %1(s32) %3(s32) = G_CONSTANT i32 16 %4(s32) = G_ASHR %2(s32), %3(s32) %5(s32) = G_CONSTANT i32 8 %6(s32) = G_LSHR %0(s32), %5(s32) %7(s32) = G_CONSTANT 255 %8(s32) = G_AND %6(s32), %7(s32) %9(s32) = G_OR %4(s32), %8(s32) ; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]] %r0 = COPY %9(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_shifts_to_revsh_commutative # CHECK-LABEL: name: test_shifts_to_revsh_commutative legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } - { id: 5, class: gprb } - { id: 6, class: gprb } - { id: 7, class: gprb } - { id: 8, class: gprb } - { id: 9, class: gprb } body: | bb.0: liveins: %r0 %0(s32) = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 %1(s32) = G_CONSTANT i32 24 %2(s32) = G_SHL %0(s32), %1(s32) %3(s32) = G_CONSTANT i32 16 %4(s32) = G_ASHR %2(s32), %3(s32) %5(s32) = G_CONSTANT i32 8 %6(s32) = G_LSHR %0(s32), %5(s32) %7(s32) = G_CONSTANT 255 %8(s32) = G_AND %6(s32), %7(s32) %9(s32) = G_OR %8(s32), %4(s32) ; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]] %r0 = COPY %9(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_shifts_no_revsh_features # CHECK-LABEL: name: test_shifts_no_revsh legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } - { id: 5, class: gprb } - { id: 6, class: gprb } - { id: 7, class: gprb } - { id: 8, class: gprb } - { id: 9, class: gprb } body: | bb.0: liveins: %r0 %0(s32) = COPY %r0 %1(s32) = G_CONSTANT i32 24 %2(s32) = G_SHL %0(s32), %1(s32) %3(s32) = G_CONSTANT i32 16 %4(s32) = G_ASHR %2(s32), %3(s32) %5(s32) = G_CONSTANT i32 8 %6(s32) = G_LSHR %0(s32), %5(s32) %7(s32) = G_CONSTANT 255 %8(s32) = G_AND %6(s32), %7(s32) %9(s32) = G_OR %4(s32), %8(s32) ; We don't really care how this is folded as long as it's not into a REVSH. ; CHECK-NOT: REVSH %r0 = COPY %9(s32) BX_RET 14, %noreg, implicit %r0 ... --- name: test_shifts_no_revsh_constants # CHECK-LABEL: name: test_shifts_no_revsh_constants legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } - { id: 5, class: gprb } - { id: 6, class: gprb } - { id: 7, class: gprb } - { id: 8, class: gprb } - { id: 9, class: gprb } body: | bb.0: liveins: %r0 %0(s32) = COPY %r0 %1(s32) = G_CONSTANT i32 16 ; REVSH needs 24 here %2(s32) = G_SHL %0(s32), %1(s32) %3(s32) = G_CONSTANT i32 24 ; REVSH needs 16 here %4(s32) = G_ASHR %2(s32), %3(s32) %5(s32) = G_CONSTANT i32 8 %6(s32) = G_LSHR %0(s32), %5(s32) %7(s32) = G_CONSTANT 255 %8(s32) = G_AND %6(s32), %7(s32) %9(s32) = G_OR %4(s32), %8(s32) ; We don't really care how this is folded as long as it's not into a REVSH. ; CHECK-NOT: REVSH %r0 = COPY %9(s32) BX_RET 14, %noreg, implicit %r0 ... --- name: test_bicrr # CHECK-LABEL: name: test_bicrr legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } body: | bb.0: liveins: %r0, %r1 %0(s32) = COPY %r0 %1(s32) = COPY %r1 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %0, %3 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_bicrr_commutative # CHECK-LABEL: name: test_bicrr_commutative legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } body: | bb.0: liveins: %r0, %r1 %0(s32) = COPY %r0 %1(s32) = COPY %r1 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %3, %0 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_bicri # CHECK-LABEL: name: test_bicri legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } body: | bb.0: liveins: %r0 %0(s32) = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 ; This test and the following ones are a bit contrived, since they use a ; G_XOR that can be constant-folded. They exist mostly to validate the ; TableGen pattern that defines BICri. We also have a pattern for matching a ; G_AND with a G_CONSTANT operand directly, which is the more common case, ; but that will be covered by different tests. %1(s32) = G_CONSTANT i32 192 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %0, %3 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_bicri_commutative_xor # CHECK-LABEL: name: test_bicri_commutative_xor legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } body: | bb.0: liveins: %r0 %0(s32) = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 %1(s32) = G_CONSTANT i32 192 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %2, %1 %4(s32) = G_AND %0, %3 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_bicri_commutative_and # CHECK-LABEL: name: test_bicri_commutative_and legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } body: | bb.0: liveins: %r0 %0(s32) = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 %1(s32) = G_CONSTANT i32 192 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %3, %0 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_bicri_commutative_both # CHECK-LABEL: name: test_bicri_commutative_both legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } body: | bb.0: liveins: %r0 %0(s32) = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 %1(s32) = G_CONSTANT i32 192 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %2, %1 %4(s32) = G_AND %3, %0 ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, %noreg, %noreg %r0 = COPY %4(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_pkhbt # CHECK-LABEL: name: test_pkhbt legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } - { id: 5, class: gprb } - { id: 6, class: gprb } - { id: 7, class: gprb } - { id: 8, class: gprb } body: | bb.0: liveins: %r0, %r1 %0(s32) = COPY %r0 %1(s32) = COPY %r1 ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF %3(s32) = G_AND %0, %2 %4(s32) = G_CONSTANT i32 7 %5(s32) = G_SHL %1, %4 %6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 %7(s32) = G_AND %5, %6 %8(s32) = G_OR %3, %7 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, %noreg %r0 = COPY %8(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_pkhbt_commutative # CHECK-LABEL: name: test_pkhbt_commutative legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } - { id: 5, class: gprb } - { id: 6, class: gprb } - { id: 7, class: gprb } - { id: 8, class: gprb } body: | bb.0: liveins: %r0, %r1 %0(s32) = COPY %r0 %1(s32) = COPY %r1 ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF %3(s32) = G_AND %0, %2 %4(s32) = G_CONSTANT i32 7 %5(s32) = G_SHL %1, %4 %6(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 %7(s32) = G_AND %5, %6 %8(s32) = G_OR %7, %3 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, %noreg %r0 = COPY %8(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_pkhbt_imm16_31 # CHECK-LABEL: name: test_pkhbt_imm16_31 legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } - { id: 5, class: gprb } - { id: 6, class: gprb } body: | bb.0: liveins: %r0, %r1 %0(s32) = COPY %r0 %1(s32) = COPY %r1 ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF %3(s32) = G_AND %0, %2 %4(s32) = G_CONSTANT i32 17 %5(s32) = G_SHL %1, %4 %6(s32) = G_OR %3, %5 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14, %noreg %r0 = COPY %6(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_pkhbt_unshifted # CHECK-LABEL: name: test_pkhbt_unshifted legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } - { id: 5, class: gprb } - { id: 6, class: gprb } body: | bb.0: liveins: %r0, %r1 %0(s32) = COPY %r0 %1(s32) = COPY %r1 ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 %2(s32) = G_CONSTANT i32 65535 ; 0xFFFF %3(s32) = G_AND %0, %2 %4(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 %5(s32) = G_AND %1, %4 %6(s32) = G_OR %3, %5 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14, %noreg %r0 = COPY %6(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_pkhtb_imm16 # CHECK-LABEL: name: test_pkhtb_imm16 legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } - { id: 5, class: gprb } - { id: 6, class: gprb } body: | bb.0: liveins: %r0, %r1 %0(s32) = COPY %r0 %1(s32) = COPY %r1 ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 %2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 %3(s32) = G_AND %0, %2 %4(s32) = G_CONSTANT i32 16 %5(s32) = G_LSHR %1, %4 %6(s32) = G_OR %3, %5 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14, %noreg %r0 = COPY %6(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_pkhtb_imm1_15 # CHECK-LABEL: name: test_pkhtb_imm1_15 legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } - { id: 3, class: gprb } - { id: 4, class: gprb } - { id: 5, class: gprb } - { id: 6, class: gprb } - { id: 7, class: gprb } - { id: 8, class: gprb } body: | bb.0: liveins: %r0, %r1 %0(s32) = COPY %r0 %1(s32) = COPY %r1 ; CHECK-DAG: [[VREGX:%[0-9]+]]:gprnopc = COPY %r0 ; CHECK-DAG: [[VREGY:%[0-9]+]]:gprnopc = COPY %r1 %2(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 %3(s32) = G_AND %0, %2 %4(s32) = G_CONSTANT i32 7 %5(s32) = G_LSHR %1, %4 %6(s32) = G_CONSTANT i32 65535 ; 0xFFFF %7(s32) = G_AND %5, %6 %8(s32) = G_OR %3, %7 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14, %noreg %r0 = COPY %8(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ... --- name: test_movti16_0xffff # CHECK-LABEL: name: test_movti16_0xffff legalized: true regBankSelected: true selected: false # CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } - { id: 2, class: gprb } body: | bb.0: liveins: %r0 %0(s32) = COPY %r0 ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0 %1(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 %2(s32) = G_OR %0, %1 ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MOVTi16 [[VREGX]], 65535, 14, %noreg %r0 = COPY %2(s32) ; CHECK: %r0 = COPY [[VREGR]] BX_RET 14, %noreg, implicit %r0 ; CHECK: BX_RET 14, %noreg, implicit %r0 ...