From 0bd30eea1adce20305938afcaf22492ef9481172 Mon Sep 17 00:00:00 2001 From: Hans Wennborg Date: Wed, 14 Feb 2018 09:41:04 +0000 Subject: Merging r324497: ------------------------------------------------------------------------ r324497 | ctopper | 2018-02-07 19:32:15 +0100 (Wed, 07 Feb 2018) | 1 line [X86] Regenerate test using update_mir_test_checks.py. NFC ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@325105 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/domain-reassignment.mir | 423 ++++++++++++++++++++----------- 1 file changed, 268 insertions(+), 155 deletions(-) (limited to 'test') diff --git a/test/CodeGen/X86/domain-reassignment.mir b/test/CodeGen/X86/domain-reassignment.mir index 3cb4b5dd139..b687bd84811 100644 --- a/test/CodeGen/X86/domain-reassignment.mir +++ b/test/CodeGen/X86/domain-reassignment.mir @@ -1,22 +1,23 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -run-pass x86-domain-reassignment -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq -o - %s | FileCheck %s --- | ; ModuleID = '../test/CodeGen/X86/gpr-to-mask.ll' source_filename = "../test/CodeGen/X86/gpr-to-mask.ll" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-unknown" - + define void @test_fcmp_storefloat(i1 %cond, float* %fptr, float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) #0 { entry: br i1 %cond, label %if, label %else - + if: ; preds = %entry %cmp1 = fcmp oeq float %f3, %f4 br label %exit - + else: ; preds = %entry %cmp2 = fcmp oeq float %f5, %f6 br label %exit - + exit: ; preds = %else, %if %val = phi i1 [ %cmp1, %if ], [ %cmp2, %else ] %selected = select i1 %val, float %f1, float %f2 @@ -48,14 +49,13 @@ ... --- name: test_fcmp_storefloat -# CHECK-LABEL: name: test_fcmp_storefloat alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false selected: false tracksRegLiveness: true -registers: +registers: - { id: 0, class: gr8, preferred-register: '' } - { id: 1, class: gr8, preferred-register: '' } - { id: 2, class: gr8, preferred-register: '' } @@ -79,7 +79,7 @@ registers: - { id: 20, class: fr128, preferred-register: '' } - { id: 21, class: fr128, preferred-register: '' } - { id: 22, class: fr32x, preferred-register: '' } -liveins: +liveins: - { reg: '%edi', virtual-reg: '%3' } - { reg: '%rsi', virtual-reg: '%4' } - { reg: '%xmm0', virtual-reg: '%5' } @@ -88,7 +88,7 @@ liveins: - { reg: '%xmm3', virtual-reg: '%8' } - { reg: '%xmm4', virtual-reg: '%9' } - { reg: '%xmm5', virtual-reg: '%10' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -105,14 +105,51 @@ frameInfo: hasMustTailInVarArgFunc: false savePoint: '' restorePoint: '' -fixedStack: -stack: -constants: +fixedStack: +stack: +constants: body: | + ; CHECK-LABEL: name: test_fcmp_storefloat + ; CHECK: bb.0.entry: + ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK: liveins: %edi, %rsi, %xmm0, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5 + ; CHECK: [[COPY:%[0-9]+]]:fr32x = COPY %xmm5 + ; CHECK: [[COPY1:%[0-9]+]]:fr32x = COPY %xmm4 + ; CHECK: [[COPY2:%[0-9]+]]:fr32x = COPY %xmm3 + ; CHECK: [[COPY3:%[0-9]+]]:fr32x = COPY %xmm2 + ; CHECK: [[COPY4:%[0-9]+]]:fr32x = COPY %xmm1 + ; CHECK: [[COPY5:%[0-9]+]]:vr128x = COPY %xmm0 + ; CHECK: [[COPY6:%[0-9]+]]:gr64 = COPY %rsi + ; CHECK: [[COPY7:%[0-9]+]]:gr32 = COPY %edi + ; CHECK: [[COPY8:%[0-9]+]]:gr8 = COPY [[COPY7]].sub_8bit + ; CHECK: TEST8ri killed [[COPY8]], 1, implicit-def %eflags + ; CHECK: JE_1 %bb.2, implicit %eflags + ; CHECK: JMP_1 %bb.1 + ; CHECK: bb.1.if: + ; CHECK: successors: %bb.3(0x80000000) + ; CHECK: [[VCMPSSZrr:%[0-9]+]]:vk1 = VCMPSSZrr [[COPY3]], [[COPY2]], 0 + ; CHECK: [[COPY9:%[0-9]+]]:vk32 = COPY [[VCMPSSZrr]] + ; CHECK: [[COPY10:%[0-9]+]]:vk8 = COPY [[COPY9]] + ; CHECK: JMP_1 %bb.3 + ; CHECK: bb.2.else: + ; CHECK: successors: %bb.3(0x80000000) + ; CHECK: [[VCMPSSZrr1:%[0-9]+]]:vk1 = VCMPSSZrr [[COPY1]], [[COPY]], 0 + ; CHECK: [[COPY11:%[0-9]+]]:vk32 = COPY [[VCMPSSZrr1]] + ; CHECK: [[COPY12:%[0-9]+]]:vk8 = COPY [[COPY11]] + ; CHECK: bb.3.exit: + ; CHECK: [[PHI:%[0-9]+]]:vk8 = PHI [[COPY12]], %bb.2, [[COPY10]], %bb.1 + ; CHECK: [[COPY13:%[0-9]+]]:vk32 = COPY [[PHI]] + ; CHECK: [[COPY14:%[0-9]+]]:vk1wm = COPY [[COPY13]] + ; CHECK: [[COPY15:%[0-9]+]]:vr128x = COPY [[COPY4]] + ; CHECK: [[DEF:%[0-9]+]]:fr128 = IMPLICIT_DEF + ; CHECK: [[VMOVSSZrrk:%[0-9]+]]:fr128 = VMOVSSZrrk [[COPY15]], killed [[COPY14]], killed [[DEF]], [[COPY5]] + ; CHECK: [[COPY16:%[0-9]+]]:fr32x = COPY [[VMOVSSZrrk]] + ; CHECK: VMOVSSZmr [[COPY6]], 1, %noreg, 0, %noreg, killed [[COPY16]] :: (store 4 into %ir.fptr) + ; CHECK: RET 0 bb.0.entry: successors: %bb.1(0x40000000), %bb.2(0x40000000) liveins: %edi, %rsi, %xmm0, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5 - + %10 = COPY %xmm5 %9 = COPY %xmm4 %8 = COPY %xmm3 @@ -125,38 +162,31 @@ body: | TEST8ri killed %11, 1, implicit-def %eflags JE_1 %bb.2, implicit %eflags JMP_1 %bb.1 - + bb.1.if: successors: %bb.3(0x80000000) - + %14 = VCMPSSZrr %7, %8, 0 ; check that cross domain copies are replaced with same domain copies. - ; CHECK: %15:vk32 = COPY %14 - ; CHECK: %0:vk8 = COPY %15 - + %15 = COPY %14 %0 = COPY %15.sub_8bit JMP_1 %bb.3 - + bb.2.else: successors: %bb.3(0x80000000) %12 = VCMPSSZrr %9, %10, 0 ; check that cross domain copies are replaced with same domain copies. - ; CHECK: %13:vk32 = COPY %12 - ; CHECK: %1:vk8 = COPY %13 %13 = COPY %12 %1 = COPY %13.sub_8bit - + bb.3.exit: ; check PHI, IMPLICIT_DEF, and INSERT_SUBREG replacers. - ; CHECK: %2:vk8 = PHI %1, %bb.2, %0, %bb.1 - ; CHECK: %16:vk32 = COPY %2 - ; CHECK: %18:vk1wm = COPY %16 - + %2 = PHI %1, %bb.2, %0, %bb.1 %17 = IMPLICIT_DEF %16 = INSERT_SUBREG %17, %2, 1 @@ -171,14 +201,13 @@ body: | ... --- name: test_8bitops -# CHECK-LABEL: name: test_8bitops alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false selected: false tracksRegLiveness: true -registers: +registers: - { id: 0, class: gr64, preferred-register: '' } - { id: 1, class: vr512, preferred-register: '' } - { id: 2, class: vr512, preferred-register: '' } @@ -198,13 +227,13 @@ registers: - { id: 16, class: gr8, preferred-register: '' } - { id: 17, class: gr8, preferred-register: '' } - { id: 18, class: gr8, preferred-register: '' } -liveins: +liveins: - { reg: '%rdi', virtual-reg: '%0' } - { reg: '%zmm0', virtual-reg: '%1' } - { reg: '%zmm1', virtual-reg: '%2' } - { reg: '%zmm2', virtual-reg: '%3' } - { reg: '%zmm3', virtual-reg: '%4' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -221,32 +250,53 @@ frameInfo: hasMustTailInVarArgFunc: false savePoint: '' restorePoint: '' -fixedStack: -stack: -constants: +fixedStack: +stack: +constants: body: | + ; CHECK-LABEL: name: test_8bitops + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK: liveins: %rdi, %zmm0, %zmm1, %zmm2, %zmm3 + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm0 + ; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY %zmm1 + ; CHECK: [[COPY3:%[0-9]+]]:vr512 = COPY %zmm2 + ; CHECK: [[COPY4:%[0-9]+]]:vr512 = COPY %zmm3 + ; CHECK: [[VCMPPDZrri:%[0-9]+]]:vk8 = VCMPPDZrri [[COPY3]], [[COPY4]], 0 + ; CHECK: [[COPY5:%[0-9]+]]:vk32 = COPY [[VCMPPDZrri]] + ; CHECK: [[COPY6:%[0-9]+]]:vk8 = COPY [[COPY5]] + ; CHECK: [[KSHIFTRBri:%[0-9]+]]:vk8 = KSHIFTRBri [[COPY6]], 2 + ; CHECK: [[KSHIFTLBri:%[0-9]+]]:vk8 = KSHIFTLBri [[KSHIFTRBri]], 1 + ; CHECK: [[KNOTBrr:%[0-9]+]]:vk8 = KNOTBrr [[KSHIFTLBri]] + ; CHECK: [[KORBrr:%[0-9]+]]:vk8 = KORBrr [[KNOTBrr]], [[KSHIFTRBri]] + ; CHECK: [[KANDBrr:%[0-9]+]]:vk8 = KANDBrr [[KORBrr]], [[KSHIFTLBri]] + ; CHECK: [[KXORBrr:%[0-9]+]]:vk8 = KXORBrr [[KANDBrr]], [[KSHIFTRBri]] + ; CHECK: [[KADDBrr:%[0-9]+]]:vk8 = KADDBrr [[KXORBrr]], [[KNOTBrr]] + ; CHECK: [[COPY7:%[0-9]+]]:vk32 = COPY [[KADDBrr]] + ; CHECK: [[COPY8:%[0-9]+]]:vk8wm = COPY [[COPY7]] + ; CHECK: [[VMOVAPDZrrk:%[0-9]+]]:vr512 = VMOVAPDZrrk [[COPY2]], killed [[COPY8]], [[COPY1]] + ; CHECK: VMOVAPDZmr [[COPY]], 1, %noreg, 0, %noreg, killed [[VMOVAPDZrrk]] + ; CHECK: KTESTBrr [[KADDBrr]], [[KADDBrr]], implicit-def %eflags + ; CHECK: JE_1 %bb.1, implicit %eflags + ; CHECK: JMP_1 %bb.2 + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: bb.2: + ; CHECK: RET 0 bb.0: liveins: %rdi, %zmm0, %zmm1, %zmm2, %zmm3 - + %0 = COPY %rdi %1 = COPY %zmm0 %2 = COPY %zmm1 %3 = COPY %zmm2 %4 = COPY %zmm3 - + %5 = VCMPPDZrri %3, %4, 0 - ; CHECK: %6:vk32 = COPY %5 - ; CHECK: %7:vk8 = COPY %6 %6 = COPY %5 %7 = COPY %6.sub_8bit - ; CHECK: %12:vk8 = KSHIFTRBri %7, 2 - ; CHECK: %13:vk8 = KSHIFTLBri %12, 1 - ; CHECK: %14:vk8 = KNOTBrr %13 - ; CHECK: %15:vk8 = KORBrr %14, %12 - ; CHECK: %16:vk8 = KANDBrr %15, %13 - ; CHECK: %17:vk8 = KXORBrr %16, %12 - ; CHECK: %18:vk8 = KADDBrr %17, %14 %12 = SHR8ri %7, 2, implicit-def dead %eflags %13 = SHL8ri %12, 1, implicit-def dead %eflags %14 = NOT8r %13 @@ -254,16 +304,13 @@ body: | %16 = AND8rr %15, %13, implicit-def dead %eflags %17 = XOR8rr %16, %12, implicit-def dead %eflags %18 = ADD8rr %17, %14, implicit-def dead %eflags - - ; CHECK: %9:vk32 = COPY %18 - ; CHECK: %10:vk8wm = COPY %9 + %8 = IMPLICIT_DEF %9 = INSERT_SUBREG %8, %18, 1 %10 = COPY %9 %11 = VMOVAPDZrrk %2, killed %10, %1 - VMOVAPDZmr %0, 1, %noreg, 0, %noreg, killed %11 + VMOVAPDZmr %0, 1, %noreg, 0, %noreg, killed %11 - ; CHECK: KTESTBrr %18, %18, implicit-def %eflags TEST8rr %18, %18, implicit-def %eflags JE_1 %bb.1, implicit %eflags JMP_1 %bb.2 @@ -276,14 +323,13 @@ body: | ... --- name: test_16bitops -# CHECK-LABEL: name: test_16bitops alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false selected: false tracksRegLiveness: true -registers: +registers: - { id: 0, class: gr64, preferred-register: '' } - { id: 1, class: vr512, preferred-register: '' } - { id: 2, class: vr512, preferred-register: '' } @@ -302,13 +348,13 @@ registers: - { id: 15, class: gr16, preferred-register: '' } - { id: 16, class: gr16, preferred-register: '' } - { id: 17, class: gr16, preferred-register: '' } -liveins: +liveins: - { reg: '%rdi', virtual-reg: '%0' } - { reg: '%zmm0', virtual-reg: '%1' } - { reg: '%zmm1', virtual-reg: '%2' } - { reg: '%zmm2', virtual-reg: '%3' } - { reg: '%zmm3', virtual-reg: '%4' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -325,47 +371,65 @@ frameInfo: hasMustTailInVarArgFunc: false savePoint: '' restorePoint: '' -fixedStack: -stack: -constants: +fixedStack: +stack: +constants: body: | + ; CHECK-LABEL: name: test_16bitops + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK: liveins: %rdi, %zmm0, %zmm1, %zmm2, %zmm3 + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm0 + ; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY %zmm1 + ; CHECK: [[COPY3:%[0-9]+]]:vr512 = COPY %zmm2 + ; CHECK: [[COPY4:%[0-9]+]]:vr512 = COPY %zmm3 + ; CHECK: [[VCMPPSZrri:%[0-9]+]]:vk16 = VCMPPSZrri [[COPY3]], [[COPY4]], 0 + ; CHECK: [[COPY5:%[0-9]+]]:vk32 = COPY [[VCMPPSZrri]] + ; CHECK: [[COPY6:%[0-9]+]]:vk16 = COPY [[COPY5]] + ; CHECK: [[KSHIFTRWri:%[0-9]+]]:vk16 = KSHIFTRWri [[COPY6]], 2 + ; CHECK: [[KSHIFTLWri:%[0-9]+]]:vk16 = KSHIFTLWri [[KSHIFTRWri]], 1 + ; CHECK: [[KNOTWrr:%[0-9]+]]:vk16 = KNOTWrr [[KSHIFTLWri]] + ; CHECK: [[KORWrr:%[0-9]+]]:vk16 = KORWrr [[KNOTWrr]], [[KSHIFTRWri]] + ; CHECK: [[KANDWrr:%[0-9]+]]:vk16 = KANDWrr [[KORWrr]], [[KSHIFTLWri]] + ; CHECK: [[KXORWrr:%[0-9]+]]:vk16 = KXORWrr [[KANDWrr]], [[KSHIFTRWri]] + ; CHECK: [[COPY7:%[0-9]+]]:vk32 = COPY [[KXORWrr]] + ; CHECK: [[COPY8:%[0-9]+]]:vk16wm = COPY [[COPY7]] + ; CHECK: [[VMOVAPSZrrk:%[0-9]+]]:vr512 = VMOVAPSZrrk [[COPY2]], killed [[COPY8]], [[COPY1]] + ; CHECK: VMOVAPSZmr [[COPY]], 1, %noreg, 0, %noreg, killed [[VMOVAPSZrrk]] + ; CHECK: KTESTWrr [[KXORWrr]], [[KXORWrr]], implicit-def %eflags + ; CHECK: JE_1 %bb.1, implicit %eflags + ; CHECK: JMP_1 %bb.2 + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: bb.2: + ; CHECK: RET 0 bb.0: liveins: %rdi, %zmm0, %zmm1, %zmm2, %zmm3 - + %0 = COPY %rdi %1 = COPY %zmm0 %2 = COPY %zmm1 %3 = COPY %zmm2 %4 = COPY %zmm3 - + %5 = VCMPPSZrri %3, %4, 0 - ; CHECK: %6:vk32 = COPY %5 - ; CHECK: %7:vk16 = COPY %6 %6 = COPY %5 %7 = COPY %6.sub_16bit - ; CHECK: %12:vk16 = KSHIFTRWri %7, 2 - ; CHECK: %13:vk16 = KSHIFTLWri %12, 1 - ; CHECK: %14:vk16 = KNOTWrr %13 - ; CHECK: %15:vk16 = KORWrr %14, %12 - ; CHECK: %16:vk16 = KANDWrr %15, %13 - ; CHECK: %17:vk16 = KXORWrr %16, %12 %12 = SHR16ri %7, 2, implicit-def dead %eflags %13 = SHL16ri %12, 1, implicit-def dead %eflags %14 = NOT16r %13 %15 = OR16rr %14, %12, implicit-def dead %eflags %16 = AND16rr %15, %13, implicit-def dead %eflags %17 = XOR16rr %16, %12, implicit-def dead %eflags - - ; CHECK: %9:vk32 = COPY %17 - ; CHECK: %10:vk16wm = COPY %9 + %8 = IMPLICIT_DEF %9 = INSERT_SUBREG %8, %17, 3 %10 = COPY %9 %11 = VMOVAPSZrrk %2, killed %10, %1 - VMOVAPSZmr %0, 1, %noreg, 0, %noreg, killed %11 + VMOVAPSZmr %0, 1, %noreg, 0, %noreg, killed %11 - ; CHECK: KTESTWrr %17, %17, implicit-def %eflags TEST16rr %17, %17, implicit-def %eflags JE_1 %bb.1, implicit %eflags JMP_1 %bb.2 @@ -378,14 +442,13 @@ body: | ... --- name: test_32bitops -# CHECK-LABEL: name: test_32bitops alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false selected: false tracksRegLiveness: true -registers: +registers: - { id: 0, class: gr64, preferred-register: '' } - { id: 1, class: vr512, preferred-register: '' } - { id: 2, class: vr512, preferred-register: '' } @@ -400,11 +463,11 @@ registers: - { id: 11, class: gr32, preferred-register: '' } - { id: 12, class: gr32, preferred-register: '' } - { id: 13, class: gr32, preferred-register: '' } -liveins: +liveins: - { reg: '%rdi', virtual-reg: '%0' } - { reg: '%zmm0', virtual-reg: '%1' } - { reg: '%zmm1', virtual-reg: '%2' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -421,26 +484,43 @@ frameInfo: hasMustTailInVarArgFunc: false savePoint: '' restorePoint: '' -fixedStack: -stack: -constants: +fixedStack: +stack: +constants: body: | + ; CHECK-LABEL: name: test_32bitops + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK: liveins: %rdi, %zmm0, %zmm1 + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm0 + ; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY %zmm1 + ; CHECK: [[KMOVDkm:%[0-9]+]]:vk32 = KMOVDkm [[COPY]], 1, %noreg, 0, %noreg + ; CHECK: [[KSHIFTRDri:%[0-9]+]]:vk32 = KSHIFTRDri [[KMOVDkm]], 2 + ; CHECK: [[KSHIFTLDri:%[0-9]+]]:vk32 = KSHIFTLDri [[KSHIFTRDri]], 1 + ; CHECK: [[KNOTDrr:%[0-9]+]]:vk32 = KNOTDrr [[KSHIFTLDri]] + ; CHECK: [[KORDrr:%[0-9]+]]:vk32 = KORDrr [[KNOTDrr]], [[KSHIFTRDri]] + ; CHECK: [[KANDDrr:%[0-9]+]]:vk32 = KANDDrr [[KORDrr]], [[KSHIFTLDri]] + ; CHECK: [[KXORDrr:%[0-9]+]]:vk32 = KXORDrr [[KANDDrr]], [[KSHIFTRDri]] + ; CHECK: [[KANDNDrr:%[0-9]+]]:vk32 = KANDNDrr [[KXORDrr]], [[KORDrr]] + ; CHECK: [[KADDDrr:%[0-9]+]]:vk32 = KADDDrr [[KANDNDrr]], [[KXORDrr]] + ; CHECK: [[COPY3:%[0-9]+]]:vk32wm = COPY [[KADDDrr]] + ; CHECK: [[VMOVDQU16Zrrk:%[0-9]+]]:vr512 = VMOVDQU16Zrrk [[COPY2]], killed [[COPY3]], [[COPY1]] + ; CHECK: VMOVDQA32Zmr [[COPY]], 1, %noreg, 0, %noreg, killed [[VMOVDQU16Zrrk]] + ; CHECK: KTESTDrr [[KADDDrr]], [[KADDDrr]], implicit-def %eflags + ; CHECK: JE_1 %bb.1, implicit %eflags + ; CHECK: JMP_1 %bb.2 + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: bb.2: + ; CHECK: RET 0 bb.0: liveins: %rdi, %zmm0, %zmm1 - + %0 = COPY %rdi %1 = COPY %zmm0 %2 = COPY %zmm1 - - ; CHECK: %5:vk32 = KMOVDkm %0, 1, %noreg, 0, %noreg - ; CHECK: %6:vk32 = KSHIFTRDri %5, 2 - ; CHECK: %7:vk32 = KSHIFTLDri %6, 1 - ; CHECK: %8:vk32 = KNOTDrr %7 - ; CHECK: %9:vk32 = KORDrr %8, %6 - ; CHECK: %10:vk32 = KANDDrr %9, %7 - ; CHECK: %11:vk32 = KXORDrr %10, %6 - ; CHECK: %12:vk32 = KANDNDrr %11, %9 - ; CHECK: %13:vk32 = KADDDrr %12, %11 + %5 = MOV32rm %0, 1, %noreg, 0, %noreg %6 = SHR32ri %5, 2, implicit-def dead %eflags %7 = SHL32ri %6, 1, implicit-def dead %eflags @@ -450,13 +530,11 @@ body: | %11 = XOR32rr %10, %6, implicit-def dead %eflags %12 = ANDN32rr %11, %9, implicit-def dead %eflags %13 = ADD32rr %12, %11, implicit-def dead %eflags - - ; CHECK: %3:vk32wm = COPY %13 + %3 = COPY %13 %4 = VMOVDQU16Zrrk %2, killed %3, %1 VMOVDQA32Zmr %0, 1, %noreg, 0, %noreg, killed %4 - ; CHECK: KTESTDrr %13, %13, implicit-def %eflags TEST32rr %13, %13, implicit-def %eflags JE_1 %bb.1, implicit %eflags JMP_1 %bb.2 @@ -469,14 +547,13 @@ body: | ... --- name: test_64bitops -# CHECK-LABEL: name: test_64bitops alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false selected: false tracksRegLiveness: true -registers: +registers: - { id: 0, class: gr64, preferred-register: '' } - { id: 1, class: vr512, preferred-register: '' } - { id: 2, class: vr512, preferred-register: '' } @@ -491,11 +568,11 @@ registers: - { id: 11, class: gr64, preferred-register: '' } - { id: 12, class: gr64, preferred-register: '' } - { id: 13, class: gr64, preferred-register: '' } -liveins: +liveins: - { reg: '%rdi', virtual-reg: '%0' } - { reg: '%zmm0', virtual-reg: '%1' } - { reg: '%zmm1', virtual-reg: '%2' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -512,26 +589,43 @@ frameInfo: hasMustTailInVarArgFunc: false savePoint: '' restorePoint: '' -fixedStack: -stack: -constants: +fixedStack: +stack: +constants: body: | + ; CHECK-LABEL: name: test_64bitops + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK: liveins: %rdi, %zmm0, %zmm1 + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm0 + ; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY %zmm1 + ; CHECK: [[KMOVQkm:%[0-9]+]]:vk64 = KMOVQkm [[COPY]], 1, %noreg, 0, %noreg + ; CHECK: [[KSHIFTRQri:%[0-9]+]]:vk64 = KSHIFTRQri [[KMOVQkm]], 2 + ; CHECK: [[KSHIFTLQri:%[0-9]+]]:vk64 = KSHIFTLQri [[KSHIFTRQri]], 1 + ; CHECK: [[KNOTQrr:%[0-9]+]]:vk64 = KNOTQrr [[KSHIFTLQri]] + ; CHECK: [[KORQrr:%[0-9]+]]:vk64 = KORQrr [[KNOTQrr]], [[KSHIFTRQri]] + ; CHECK: [[KANDQrr:%[0-9]+]]:vk64 = KANDQrr [[KORQrr]], [[KSHIFTLQri]] + ; CHECK: [[KXORQrr:%[0-9]+]]:vk64 = KXORQrr [[KANDQrr]], [[KSHIFTRQri]] + ; CHECK: [[KANDNQrr:%[0-9]+]]:vk64 = KANDNQrr [[KXORQrr]], [[KORQrr]] + ; CHECK: [[KADDQrr:%[0-9]+]]:vk64 = KADDQrr [[KANDNQrr]], [[KXORQrr]] + ; CHECK: [[COPY3:%[0-9]+]]:vk64wm = COPY [[KADDQrr]] + ; CHECK: [[VMOVDQU8Zrrk:%[0-9]+]]:vr512 = VMOVDQU8Zrrk [[COPY2]], killed [[COPY3]], [[COPY1]] + ; CHECK: VMOVDQA32Zmr [[COPY]], 1, %noreg, 0, %noreg, killed [[VMOVDQU8Zrrk]] + ; CHECK: KTESTQrr [[KADDQrr]], [[KADDQrr]], implicit-def %eflags + ; CHECK: JE_1 %bb.1, implicit %eflags + ; CHECK: JMP_1 %bb.2 + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: bb.2: + ; CHECK: RET 0 bb.0: liveins: %rdi, %zmm0, %zmm1 - + %0 = COPY %rdi %1 = COPY %zmm0 %2 = COPY %zmm1 - - ; CHECK: %5:vk64 = KMOVQkm %0, 1, %noreg, 0, %noreg - ; CHECK: %6:vk64 = KSHIFTRQri %5, 2 - ; CHECK: %7:vk64 = KSHIFTLQri %6, 1 - ; CHECK: %8:vk64 = KNOTQrr %7 - ; CHECK: %9:vk64 = KORQrr %8, %6 - ; CHECK: %10:vk64 = KANDQrr %9, %7 - ; CHECK: %11:vk64 = KXORQrr %10, %6 - ; CHECK: %12:vk64 = KANDNQrr %11, %9 - ; CHECK: %13:vk64 = KADDQrr %12, %11 + %5 = MOV64rm %0, 1, %noreg, 0, %noreg %6 = SHR64ri %5, 2, implicit-def dead %eflags %7 = SHL64ri %6, 1, implicit-def dead %eflags @@ -541,13 +635,11 @@ body: | %11 = XOR64rr %10, %6, implicit-def dead %eflags %12 = ANDN64rr %11, %9, implicit-def dead %eflags %13 = ADD64rr %12, %11, implicit-def dead %eflags - - ; CHECK: %3:vk64wm = COPY %13 + %3 = COPY %13 %4 = VMOVDQU8Zrrk %2, killed %3, %1 VMOVDQA32Zmr %0, 1, %noreg, 0, %noreg, killed %4 - ; CHECK: KTESTQrr %13, %13, implicit-def %eflags TEST64rr %13, %13, implicit-def %eflags JE_1 %bb.1, implicit %eflags JMP_1 %bb.2 @@ -560,14 +652,13 @@ body: | ... --- name: test_16bitext -# CHECK-LABEL: name: test_16bitext alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false selected: false tracksRegLiveness: true -registers: +registers: - { id: 0, class: gr64, preferred-register: '' } - { id: 1, class: vr512, preferred-register: '' } - { id: 2, class: vr512, preferred-register: '' } @@ -575,11 +666,11 @@ registers: - { id: 4, class: vr512, preferred-register: '' } - { id: 5, class: gr16, preferred-register: '' } - { id: 6, class: gr16, preferred-register: '' } -liveins: +liveins: - { reg: '%rdi', virtual-reg: '%0' } - { reg: '%zmm0', virtual-reg: '%1' } - { reg: '%zmm1', virtual-reg: '%2' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -596,24 +687,32 @@ frameInfo: hasMustTailInVarArgFunc: false savePoint: '' restorePoint: '' -fixedStack: -stack: -constants: +fixedStack: +stack: +constants: body: | bb.0: liveins: %rdi, %zmm0, %zmm1 - + + ; CHECK-LABEL: name: test_16bitext + ; CHECK: liveins: %rdi, %zmm0, %zmm1 + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm0 + ; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY %zmm1 + ; CHECK: [[KMOVBkm:%[0-9]+]]:vk8 = KMOVBkm [[COPY]], 1, %noreg, 0, %noreg + ; CHECK: [[COPY3:%[0-9]+]]:vk16 = COPY [[KMOVBkm]] + ; CHECK: [[KNOTWrr:%[0-9]+]]:vk16 = KNOTWrr [[COPY3]] + ; CHECK: [[COPY4:%[0-9]+]]:vk16wm = COPY [[KNOTWrr]] + ; CHECK: [[VMOVAPSZrrk:%[0-9]+]]:vr512 = VMOVAPSZrrk [[COPY2]], killed [[COPY4]], [[COPY1]] + ; CHECK: VMOVAPSZmr [[COPY]], 1, %noreg, 0, %noreg, killed [[VMOVAPSZrrk]] + ; CHECK: RET 0 %0 = COPY %rdi %1 = COPY %zmm0 %2 = COPY %zmm1 - - ; CHECK: %7:vk8 = KMOVBkm %0, 1, %noreg, 0, %noreg - ; CHECK: %5:vk16 = COPY %7 - ; CHECK: %6:vk16 = KNOTWrr %5 + %5 = MOVZX16rm8 %0, 1, %noreg, 0, %noreg %6 = NOT16r %5 - ; CHECK: %3:vk16wm = COPY %6 %3 = COPY %6 %4 = VMOVAPSZrrk %2, killed %3, %1 VMOVAPSZmr %0, 1, %noreg, 0, %noreg, killed %4 @@ -622,14 +721,13 @@ body: | ... --- name: test_32bitext -# CHECK-LABEL: name: test_32bitext alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false selected: false tracksRegLiveness: true -registers: +registers: - { id: 0, class: gr64, preferred-register: '' } - { id: 1, class: vr512, preferred-register: '' } - { id: 2, class: vr512, preferred-register: '' } @@ -638,11 +736,11 @@ registers: - { id: 5, class: gr32, preferred-register: '' } - { id: 6, class: gr32, preferred-register: '' } - { id: 7, class: gr32, preferred-register: '' } -liveins: +liveins: - { reg: '%rdi', virtual-reg: '%0' } - { reg: '%zmm0', virtual-reg: '%1' } - { reg: '%zmm1', virtual-reg: '%2' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -659,27 +757,35 @@ frameInfo: hasMustTailInVarArgFunc: false savePoint: '' restorePoint: '' -fixedStack: -stack: -constants: +fixedStack: +stack: +constants: body: | bb.0: liveins: %rdi, %zmm0, %zmm1 - + + ; CHECK-LABEL: name: test_32bitext + ; CHECK: liveins: %rdi, %zmm0, %zmm1 + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm0 + ; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY %zmm1 + ; CHECK: [[KMOVBkm:%[0-9]+]]:vk8 = KMOVBkm [[COPY]], 1, %noreg, 0, %noreg + ; CHECK: [[COPY3:%[0-9]+]]:vk32 = COPY [[KMOVBkm]] + ; CHECK: [[KMOVWkm:%[0-9]+]]:vk16 = KMOVWkm [[COPY]], 1, %noreg, 0, %noreg + ; CHECK: [[COPY4:%[0-9]+]]:vk32 = COPY [[KMOVWkm]] + ; CHECK: [[KADDDrr:%[0-9]+]]:vk32 = KADDDrr [[COPY3]], [[COPY4]] + ; CHECK: [[COPY5:%[0-9]+]]:vk64wm = COPY [[KADDDrr]] + ; CHECK: [[VMOVDQU16Zrrk:%[0-9]+]]:vr512 = VMOVDQU16Zrrk [[COPY2]], killed [[COPY5]], [[COPY1]] + ; CHECK: VMOVDQA32Zmr [[COPY]], 1, %noreg, 0, %noreg, killed [[VMOVDQU16Zrrk]] + ; CHECK: RET 0 %0 = COPY %rdi %1 = COPY %zmm0 %2 = COPY %zmm1 - - ; CHECK: %8:vk8 = KMOVBkm %0, 1, %noreg, 0, %noreg - ; CHECK: %5:vk32 = COPY %8 - ; CHECK: %9:vk16 = KMOVWkm %0, 1, %noreg, 0, %noreg - ; CHECK: %6:vk32 = COPY %9 - ; CHECK: %7:vk32 = KADDDrr %5, %6 + %5 = MOVZX32rm8 %0, 1, %noreg, 0, %noreg %6 = MOVZX32rm16 %0, 1, %noreg, 0, %noreg %7 = ADD32rr %5, %6, implicit-def dead %eflags - ; CHECK: %3:vk64wm = COPY %7 %3 = COPY %7 %4 = VMOVDQU16Zrrk %2, killed %3, %1 VMOVDQA32Zmr %0, 1, %noreg, 0, %noreg, killed %4 @@ -688,14 +794,13 @@ body: | ... --- name: test_64bitext -# CHECK-LABEL: name: test_64bitext alignment: 4 exposesReturnsTwice: false legalized: false regBankSelected: false selected: false tracksRegLiveness: true -registers: +registers: - { id: 0, class: gr64, preferred-register: '' } - { id: 1, class: vr512, preferred-register: '' } - { id: 2, class: vr512, preferred-register: '' } @@ -704,11 +809,11 @@ registers: - { id: 5, class: gr64, preferred-register: '' } - { id: 6, class: gr64, preferred-register: '' } - { id: 7, class: gr64, preferred-register: '' } -liveins: +liveins: - { reg: '%rdi', virtual-reg: '%0' } - { reg: '%zmm0', virtual-reg: '%1' } - { reg: '%zmm1', virtual-reg: '%2' } -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -725,27 +830,35 @@ frameInfo: hasMustTailInVarArgFunc: false savePoint: '' restorePoint: '' -fixedStack: -stack: -constants: +fixedStack: +stack: +constants: body: | bb.0: liveins: %rdi, %zmm0, %zmm1 - + + ; CHECK-LABEL: name: test_64bitext + ; CHECK: liveins: %rdi, %zmm0, %zmm1 + ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY %rdi + ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY %zmm0 + ; CHECK: [[COPY2:%[0-9]+]]:vr512 = COPY %zmm1 + ; CHECK: [[KMOVBkm:%[0-9]+]]:vk8 = KMOVBkm [[COPY]], 1, %noreg, 0, %noreg + ; CHECK: [[COPY3:%[0-9]+]]:vk64 = COPY [[KMOVBkm]] + ; CHECK: [[KMOVWkm:%[0-9]+]]:vk16 = KMOVWkm [[COPY]], 1, %noreg, 0, %noreg + ; CHECK: [[COPY4:%[0-9]+]]:vk64 = COPY [[KMOVWkm]] + ; CHECK: [[KADDQrr:%[0-9]+]]:vk64 = KADDQrr [[COPY3]], [[COPY4]] + ; CHECK: [[COPY5:%[0-9]+]]:vk64wm = COPY [[KADDQrr]] + ; CHECK: [[VMOVDQU8Zrrk:%[0-9]+]]:vr512 = VMOVDQU8Zrrk [[COPY2]], killed [[COPY5]], [[COPY1]] + ; CHECK: VMOVDQA32Zmr [[COPY]], 1, %noreg, 0, %noreg, killed [[VMOVDQU8Zrrk]] + ; CHECK: RET 0 %0 = COPY %rdi %1 = COPY %zmm0 %2 = COPY %zmm1 - - ; CHECK: %8:vk8 = KMOVBkm %0, 1, %noreg, 0, %noreg - ; CHECK: %5:vk64 = COPY %8 - ; CHECK: %9:vk16 = KMOVWkm %0, 1, %noreg, 0, %noreg - ; CHECK: %6:vk64 = COPY %9 - ; CHECK: %7:vk64 = KADDQrr %5, %6 + %5 = MOVZX64rm8 %0, 1, %noreg, 0, %noreg %6 = MOVZX64rm16 %0, 1, %noreg, 0, %noreg %7 = ADD64rr %5, %6, implicit-def dead %eflags - ; CHECK: %3:vk64wm = COPY %7 %3 = COPY %7 %4 = VMOVDQU8Zrrk %2, killed %3, %1 VMOVDQA32Zmr %0, 1, %noreg, 0, %noreg, killed %4 -- cgit v1.2.3