From 086791eca2260c03c7bbdd37a53626d16656f0ca Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 10 Dec 2013 10:36:34 +0000 Subject: Add TargetLowering::prepareVolatileOrAtomicLoad One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196905 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/SystemZ/spill-01.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'test/CodeGen/SystemZ/spill-01.ll') diff --git a/test/CodeGen/SystemZ/spill-01.ll b/test/CodeGen/SystemZ/spill-01.ll index ca64a88f2a0..c1f780c55d3 100644 --- a/test/CodeGen/SystemZ/spill-01.ll +++ b/test/CodeGen/SystemZ/spill-01.ll @@ -400,6 +400,7 @@ define void @f10() { ; CHECK: stgrl [[REG]], h8 ; CHECK: br %r14 entry: + %val8 = load volatile i64 *@h8 %val0 = load volatile i64 *@h0 %val1 = load volatile i64 *@h1 %val2 = load volatile i64 *@h2 @@ -408,7 +409,6 @@ entry: %val5 = load volatile i64 *@h5 %val6 = load volatile i64 *@h6 %val7 = load volatile i64 *@h7 - %val8 = load volatile i64 *@h8 %val9 = load volatile i64 *@h9 call void @foo() -- cgit v1.2.3