From 6c0ae87241fcdd95aacfd89d70216fb3fb9aba07 Mon Sep 17 00:00:00 2001 From: Nemanja Ivanovic Date: Mon, 11 Dec 2017 14:35:48 +0000 Subject: [PowerPC] Sign-extend negative constant stores Second part of https://reviews.llvm.org/D40348. Revision r318436 has extended all constants feeding a store to 64 bits to allow for CSE on the SDAG. However, negative constants were zero extended which made the constant being loaded appear to be a positive value larger than 16 bits. This resulted in long sequences to materialize such constants rather than simply a "load immediate". This patch just sign-extends those updated constants so that they remain 16-bit signed immediates if they started out that way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320368 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/PowerPC/testComparesigeui.ll | 6 ++---- test/CodeGen/PowerPC/testComparesllgeui.ll | 6 ++---- 2 files changed, 4 insertions(+), 8 deletions(-) (limited to 'test/CodeGen/PowerPC') diff --git a/test/CodeGen/PowerPC/testComparesigeui.ll b/test/CodeGen/PowerPC/testComparesigeui.ll index a77cea72cfa..ac55500432f 100644 --- a/test/CodeGen/PowerPC/testComparesigeui.ll +++ b/test/CodeGen/PowerPC/testComparesigeui.ll @@ -105,10 +105,8 @@ entry: store i32 %conv1, i32* @glob ret void ; CHECK-LABEL: @test_igeui_sext_z_store -; CHECK: li [[REG1:r[0-9]+]], 0 -; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535 -; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535 -; CHECK: stw [[REG3]] +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: stw [[REG1]] ; CHECK: blr } diff --git a/test/CodeGen/PowerPC/testComparesllgeui.ll b/test/CodeGen/PowerPC/testComparesllgeui.ll index 856d3a0f3cc..9e971b140de 100644 --- a/test/CodeGen/PowerPC/testComparesllgeui.ll +++ b/test/CodeGen/PowerPC/testComparesllgeui.ll @@ -105,10 +105,8 @@ entry: store i32 %sub, i32* @glob ret void ; CHECK-LABEL: @test_llgeui_sext_z_store -; CHECK: li [[REG1:r[0-9]+]], 0 -; CHECK: oris [[REG2:r[0-9]+]], [[REG1]], 65535 -; CHECK: ori [[REG3:r[0-9]+]], [[REG2]], 65535 -; CHECK: stw [[REG3]] +; CHECK: li [[REG1:r[0-9]+]], -1 +; CHECK: stw [[REG1]] ; CHECK: blr } -- cgit v1.2.3