From 7164288c3eb52e20454fc757440f867f04eb13a4 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 19 Jun 2012 21:14:34 +0000 Subject: Implement PPCInstrInfo::isCoalescableExtInstr(). The PPC::EXTSW instruction preserves the low 32 bits of its input, just like some of the x86 instructions. Use it to reduce register pressure when the low 32 bits have multiple uses. This requires a small change to PeepholeOptimizer since EXTSW takes a 64-bit input register. This is related to PR5997. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/PowerPC/coalesce-ext.ll | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 test/CodeGen/PowerPC/coalesce-ext.ll (limited to 'test/CodeGen/PowerPC/coalesce-ext.ll') diff --git a/test/CodeGen/PowerPC/coalesce-ext.ll b/test/CodeGen/PowerPC/coalesce-ext.ll new file mode 100644 index 00000000000..08a2cc773fd --- /dev/null +++ b/test/CodeGen/PowerPC/coalesce-ext.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=ppc64 < %s | FileCheck %s +; Check that the peephole optimizer knows about sext and zext instructions. +; CHECK: test1sext +define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind { + %C = add i64 %A, %B + ; CHECK: add [[SUM:r[0-9]+]], r3, r4 + %D = trunc i64 %C to i32 + %E = shl i64 %C, 32 + %F = ashr i64 %E, 32 + ; CHECK: extsw [[EXT:r[0-9]+]], [[SUM]] + store volatile i64 %F, i64 *%P2 + ; CHECK: std [[EXT]] + store volatile i32 %D, i32* %P + ; Reuse low bits of extended register, don't extend live range of SUM. + ; CHECK: stw [[EXT]] + ret i32 %D +} -- cgit v1.2.3