From fd11bc081304b8ca3bf7a657eb45af7a6a24246f Mon Sep 17 00:00:00 2001 From: Francis Visoiu Mistrih Date: Thu, 7 Dec 2017 10:40:31 +0000 Subject: [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. Work towards the unification of MIR and debug output by refactoring the interfaces. For MachineOperand::print, keep a simple version that can be easily called from `dump()`, and a more complex one which will be called from both the MIRPrinter and MachineInstr::print. Add extra checks inside MachineOperand for detached operands (operands with getParent() == nullptr). https://reviews.llvm.org/D40836 * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)/kill: \1 def \2 \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)/kill: \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)/kill: def \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's///g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/implicit killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/implicit-def dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/implicit-def \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/implicit \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/internal \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)/undef \1/g' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320022 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 24 +++---- .../AArch64/GlobalISel/verify-regbankselected.mir | 4 +- .../CodeGen/AArch64/GlobalISel/verify-selected.mir | 6 +- .../AArch64/aarch64-a57-fp-load-balancing.ll | 2 +- .../CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll | 2 +- test/CodeGen/AArch64/arm64-csldst-mmo.ll | 2 +- .../CodeGen/AArch64/arm64-dead-register-def-bug.ll | 2 +- test/CodeGen/AArch64/arm64-fast-isel-rem.ll | 6 +- test/CodeGen/AArch64/arm64-ldp-cluster.ll | 52 +++++++-------- .../AArch64/arm64-misched-forwarding-A53.ll | 2 +- test/CodeGen/AArch64/arm64-misched-memdep-bug.ll | 4 +- test/CodeGen/AArch64/arm64-misched-multimmo.ll | 2 +- test/CodeGen/AArch64/loh.mir | 78 +++++++++++----------- test/CodeGen/AArch64/machine-copy-prop.ll | 12 ++-- test/CodeGen/AArch64/scheduledag-constreg.mir | 8 +-- test/CodeGen/AArch64/tailcall_misched_graph.ll | 6 +- 16 files changed, 106 insertions(+), 106 deletions(-) (limited to 'test/CodeGen/AArch64') diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index aa81c3aff89..72069f0e62e 100644 --- a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -43,7 +43,7 @@ define [1 x double] @constant() { ; The key problem here is that we may fail to create an MBB referenced by a ; PHI. If so, we cannot complete the G_PHI and mustn't try or bad things ; happen. -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: cannot select: G_STORE %6, %2; mem:ST4[%addr] GPR:%6,%2 (in function: pending_phis) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: cannot select: G_STORE %6(s32), %2(p0); mem:ST4[%addr] GPR:%6,%2 (in function: pending_phis) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for pending_phis ; FALLBACK-WITH-REPORT-OUT-LABEL: pending_phis: define i32 @pending_phis(i1 %tst, i32 %val, i32* %addr) { @@ -63,7 +63,7 @@ false: } ; General legalizer inability to handle types whose size wasn't a power of 2. -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1, %0; mem:ST6[%addr](align=8) (in function: odd_type) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1(s42), %0(p0); mem:ST6[%addr](align=8) (in function: odd_type) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type: define void @odd_type(i42* %addr) { @@ -72,7 +72,7 @@ define void @odd_type(i42* %addr) { ret void } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1, %0; mem:ST28[%addr](align=32) (in function: odd_vector) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1(<7 x s32>), %0(p0); mem:ST28[%addr](align=32) (in function: odd_vector) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_vector ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_vector: define void @odd_vector(<7 x i32>* %addr) { @@ -91,7 +91,7 @@ define i128 @sequence_sizes([8 x i8] %in) { } ; Just to make sure we don't accidentally emit a normal load/store. -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: cannot select: %2(s64) = G_LOAD %0; mem:LD8[%addr] GPR:%2,%0 (in function: atomic_ops) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: cannot select: %2:gpr(s64) = G_LOAD %0(p0); mem:LD8[%addr] GPR:%2,%0 (in function: atomic_ops) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for atomic_ops ; FALLBACK-WITH-REPORT-LABEL: atomic_ops: define i64 @atomic_ops(i64* %addr) { @@ -132,14 +132,14 @@ continue: } ; Check that we fallback on invoke translation failures. -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %0(s128) = G_FCONSTANT quad 2 +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %0:_(s128) = G_FCONSTANT quad 2 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_quad_dump ; FALLBACK-WITH-REPORT-OUT-LABEL: test_quad_dump: define fp128 @test_quad_dump() { ret fp128 0xL00000000000000004000000000000000 } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %0(p0) = G_EXTRACT_VECTOR_ELT %1, %2; (in function: vector_of_pointers_extractelement) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %0:_(p0) = G_EXTRACT_VECTOR_ELT %1(<2 x p0>), %2(s32); (in function: vector_of_pointers_extractelement) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_extractelement ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_extractelement: @var = global <2 x i16*> zeroinitializer @@ -156,7 +156,7 @@ end: br label %block } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %0, %4; mem:ST16[undef] (in function: vector_of_pointers_insertelement) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %0(<2 x p0>), %4(p0); mem:ST16[undef] (in function: vector_of_pointers_insertelement) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement: define void @vector_of_pointers_insertelement() { @@ -172,7 +172,7 @@ end: br label %block } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1, %3; mem:ST12[undef](align=4) (in function: nonpow2_insertvalue_narrowing) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1(s96), %3(p0); mem:ST12[undef](align=4) (in function: nonpow2_insertvalue_narrowing) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_insertvalue_narrowing ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_insertvalue_narrowing: %struct96 = type { float, float, float } @@ -213,7 +213,7 @@ define void @nonpow2_load_narrowing() { ret void } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %3, %0; mem:ST12[%c](align=16) (in function: nonpow2_store_narrowing +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %3(s96), %0(p0); mem:ST12[%c](align=16) (in function: nonpow2_store_narrowing ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_store_narrowing ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_store_narrowing: define void @nonpow2_store_narrowing(i96* %c) { @@ -223,7 +223,7 @@ define void @nonpow2_store_narrowing(i96* %c) { ret void } -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %0, %1; mem:ST12[undef](align=16) (in function: nonpow2_constant_narrowing) +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %0(s96), %1(p0); mem:ST12[undef](align=16) (in function: nonpow2_constant_narrowing) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_constant_narrowing ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_constant_narrowing: define void @nonpow2_constant_narrowing() { @@ -233,8 +233,8 @@ define void @nonpow2_constant_narrowing() { ; Currently can't handle vector lengths that aren't an exact multiple of ; natively supported vector lengths. Test that the fall-back works for those. -; FALLBACK-WITH-REPORT-ERR-G_IMPLICIT_DEF-LEGALIZABLE: (FIXME: this is what is expected once we can legalize non-pow-of-2 G_IMPLICIT_DEF) remark: :0:0: unable to legalize instruction: %1(<7 x s64>) = G_ADD %0, %0; (in function: nonpow2_vector_add_fewerelements -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %2(s64) = G_EXTRACT_VECTOR_ELT %1, %3; (in function: nonpow2_vector_add_fewerelements) +; FALLBACK-WITH-REPORT-ERR-G_IMPLICIT_DEF-LEGALIZABLE: (FIXME: this is what is expected once we can legalize non-pow-of-2 G_IMPLICIT_DEF) remark: :0:0: unable to legalize instruction: %1(<7 x s64>) = G_ADD %0, %0; (in function: nonpow2_vector_add_fewerelements +; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %2:_(s64) = G_EXTRACT_VECTOR_ELT %1(<7 x s64>), %3(s64); (in function: nonpow2_vector_add_fewerelements) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_vector_add_fewerelements ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_vector_add_fewerelements: define void @nonpow2_vector_add_fewerelements() { diff --git a/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir b/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir index 7d0c9a37d17..94a9134072a 100644 --- a/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir +++ b/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir @@ -9,8 +9,8 @@ ... --- # CHECK: *** Bad machine code: Generic virtual register must have a bank in a RegBankSelected function *** -# CHECK: instruction: %0(s64) = COPY -# CHECK: operand 0: %0 +# CHECK: instruction: %0:_(s64) = COPY +# CHECK: operand 0: %0 name: test regBankSelected: true registers: diff --git a/test/CodeGen/AArch64/GlobalISel/verify-selected.mir b/test/CodeGen/AArch64/GlobalISel/verify-selected.mir index a182cf53173..772233ec103 100644 --- a/test/CodeGen/AArch64/GlobalISel/verify-selected.mir +++ b/test/CodeGen/AArch64/GlobalISel/verify-selected.mir @@ -22,11 +22,11 @@ body: | %0 = COPY %x0 ; CHECK: *** Bad machine code: Unexpected generic instruction in a Selected function *** - ; CHECK: instruction: %1 = G_ADD + ; CHECK: instruction: %1:gpr64 = G_ADD %1 = G_ADD %0, %0 ; CHECK: *** Bad machine code: Generic virtual register invalid in a Selected function *** - ; CHECK: instruction: %2(s64) = COPY - ; CHECK: operand 0: %2 + ; CHECK: instruction: %2:gpr(s64) = COPY + ; CHECK: operand 0: %2 %2(s64) = COPY %x0 ... diff --git a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll index 3ad9442b674..55f6c01cbd9 100644 --- a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll +++ b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll @@ -296,7 +296,7 @@ declare double @hh(double) #1 ; Check that we correctly deal with repeated operands. ; The following testcase creates: -; %d1 = FADDDrr %d0, %d0 +; %d1 = FADDDrr killed %d0, %d0 ; We'll get a crash if we naively look at the first operand, remove it ; from the substitution list then look at the second operand. diff --git a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll index a21b6f2b0d9..bd0028c7452 100644 --- a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll +++ b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm64-apple-ios -verify-machineinstrs | FileCheck %s ; LdStOpt bug created illegal instruction: -; %d1, %d2 = LDPSi %x0, 1 +; %d1, %d2 = LDPSi %x0, 1 ; rdar://11512047 %0 = type opaque diff --git a/test/CodeGen/AArch64/arm64-csldst-mmo.ll b/test/CodeGen/AArch64/arm64-csldst-mmo.ll index b0059193d34..c69779add59 100644 --- a/test/CodeGen/AArch64/arm64-csldst-mmo.ll +++ b/test/CodeGen/AArch64/arm64-csldst-mmo.ll @@ -11,7 +11,7 @@ ; CHECK: Before post-MI-sched: ; CHECK-LABEL: # Machine code for function test1: ; CHECK: SU(2): STRWui %wzr -; CHECK: SU(3): %x21, %x20 = LDPXi %sp +; CHECK: SU(3): %x21, %x20 = LDPXi %sp ; CHECK: Predecessors: ; CHECK-NEXT: SU(0): Out ; CHECK-NEXT: SU(0): Out diff --git a/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll b/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll index 03d05429308..d43efa7ee79 100644 --- a/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll +++ b/test/CodeGen/AArch64/arm64-dead-register-def-bug.ll @@ -3,7 +3,7 @@ ; Check that the dead register definition pass is considering implicit defs. ; When rematerializing through truncates, the coalescer may produce instructions ; with dead defs, but live implicit-defs of subregs: -; E.g. %x1 = MOVi64imm 2, %w1; %x1:GPR64, %w1:GPR32 +; E.g. dead %x1 = MOVi64imm 2, implicit-def %w1; %x1:GPR64, %w1:GPR32 ; These instructions are live, and their definitions should not be rewritten. ; ; diff --git a/test/CodeGen/AArch64/arm64-fast-isel-rem.ll b/test/CodeGen/AArch64/arm64-fast-isel-rem.ll index 58f414432ac..c26bfa8bcfe 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-rem.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-rem.ll @@ -4,9 +4,9 @@ ; CHECK-SSA-LABEL: Machine code for function t1 -; CHECK-SSA: [[QUOTREG:%[0-9]+]] = SDIVWr -; CHECK-SSA-NOT: [[QUOTREG]] = -; CHECK-SSA: {{%[0-9]+}} = MSUBWrrr [[QUOTREG]] +; CHECK-SSA: [[QUOTREG:%[0-9]+]]:gpr32 = SDIVWr +; CHECK-SSA-NOT: [[QUOTREG]] = +; CHECK-SSA: {{%[0-9]+}}:gpr32 = MSUBWrrr killed [[QUOTREG]] ; CHECK-SSA-LABEL: Machine code for function t2 diff --git a/test/CodeGen/AArch64/arm64-ldp-cluster.ll b/test/CodeGen/AArch64/arm64-ldp-cluster.ll index 370db233fcb..75b02b9d913 100644 --- a/test/CodeGen/AArch64/arm64-ldp-cluster.ll +++ b/test/CodeGen/AArch64/arm64-ldp-cluster.ll @@ -6,13 +6,13 @@ ; CHECK: ********** MI Scheduling ********** ; CHECK-LABEL: ldr_int:%bb.0 ; CHECK: Cluster ld/st SU(1) - SU(2) -; CHECK: SU(1): %{{[0-9]+}} = LDRWui -; CHECK: SU(2): %{{[0-9]+}} = LDRWui +; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui +; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui ; EXYNOS: ********** MI Scheduling ********** ; EXYNOS-LABEL: ldr_int:%bb.0 ; EXYNOS: Cluster ld/st SU(1) - SU(2) -; EXYNOS: SU(1): %{{[0-9]+}} = LDRWui -; EXYNOS: SU(2): %{{[0-9]+}} = LDRWui +; EXYNOS: SU(1): %{{[0-9]+}}:gpr32 = LDRWui +; EXYNOS: SU(2): %{{[0-9]+}}:gpr32 = LDRWui define i32 @ldr_int(i32* %a) nounwind { %p1 = getelementptr inbounds i32, i32* %a, i32 1 %tmp1 = load i32, i32* %p1, align 2 @@ -26,13 +26,13 @@ define i32 @ldr_int(i32* %a) nounwind { ; CHECK: ********** MI Scheduling ********** ; CHECK-LABEL: ldp_sext_int:%bb.0 ; CHECK: Cluster ld/st SU(1) - SU(2) -; CHECK: SU(1): %{{[0-9]+}} = LDRSWui -; CHECK: SU(2): %{{[0-9]+}} = LDRSWui +; CHECK: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui +; CHECK: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui ; EXYNOS: ********** MI Scheduling ********** ; EXYNOS-LABEL: ldp_sext_int:%bb.0 ; EXYNOS: Cluster ld/st SU(1) - SU(2) -; EXYNOS: SU(1): %{{[0-9]+}} = LDRSWui -; EXYNOS: SU(2): %{{[0-9]+}} = LDRSWui +; EXYNOS: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui +; EXYNOS: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui define i64 @ldp_sext_int(i32* %p) nounwind { %tmp = load i32, i32* %p, align 4 %add.ptr = getelementptr inbounds i32, i32* %p, i64 1 @@ -47,13 +47,13 @@ define i64 @ldp_sext_int(i32* %p) nounwind { ; CHECK: ********** MI Scheduling ********** ; CHECK-LABEL: ldur_int:%bb.0 ; CHECK: Cluster ld/st SU(2) - SU(1) -; CHECK: SU(1): %{{[0-9]+}} = LDURWi -; CHECK: SU(2): %{{[0-9]+}} = LDURWi +; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDURWi +; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDURWi ; EXYNOS: ********** MI Scheduling ********** ; EXYNOS-LABEL: ldur_int:%bb.0 ; EXYNOS: Cluster ld/st SU(2) - SU(1) -; EXYNOS: SU(1): %{{[0-9]+}} = LDURWi -; EXYNOS: SU(2): %{{[0-9]+}} = LDURWi +; EXYNOS: SU(1): %{{[0-9]+}}:gpr32 = LDURWi +; EXYNOS: SU(2): %{{[0-9]+}}:gpr32 = LDURWi define i32 @ldur_int(i32* %a) nounwind { %p1 = getelementptr inbounds i32, i32* %a, i32 -1 %tmp1 = load i32, i32* %p1, align 2 @@ -67,13 +67,13 @@ define i32 @ldur_int(i32* %a) nounwind { ; CHECK: ********** MI Scheduling ********** ; CHECK-LABEL: ldp_half_sext_zext_int:%bb.0 ; CHECK: Cluster ld/st SU(3) - SU(4) -; CHECK: SU(3): %{{[0-9]+}} = LDRSWui -; CHECK: SU(4): %{{[0-9]+}}:sub_32 = LDRWui +; CHECK: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui +; CHECK: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui ; EXYNOS: ********** MI Scheduling ********** ; EXYNOS-LABEL: ldp_half_sext_zext_int:%bb.0 ; EXYNOS: Cluster ld/st SU(3) - SU(4) -; EXYNOS: SU(3): %{{[0-9]+}} = LDRSWui -; EXYNOS: SU(4): %{{[0-9]+}}:sub_32 = LDRWui +; EXYNOS: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui +; EXYNOS: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind { %tmp0 = load i64, i64* %q, align 4 %tmp = load i32, i32* %p, align 4 @@ -90,13 +90,13 @@ define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind { ; CHECK: ********** MI Scheduling ********** ; CHECK-LABEL: ldp_half_zext_sext_int:%bb.0 ; CHECK: Cluster ld/st SU(3) - SU(4) -; CHECK: SU(3): %{{[0-9]+}}:sub_32 = LDRWui -; CHECK: SU(4): %{{[0-9]+}} = LDRSWui +; CHECK: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui +; CHECK: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui ; EXYNOS: ********** MI Scheduling ********** ; EXYNOS-LABEL: ldp_half_zext_sext_int:%bb.0 ; EXYNOS: Cluster ld/st SU(3) - SU(4) -; EXYNOS: SU(3): %{{[0-9]+}}:sub_32 = LDRWui -; EXYNOS: SU(4): %{{[0-9]+}} = LDRSWui +; EXYNOS: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui +; EXYNOS: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind { %tmp0 = load i64, i64* %q, align 4 %tmp = load i32, i32* %p, align 4 @@ -113,13 +113,13 @@ define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind { ; CHECK: ********** MI Scheduling ********** ; CHECK-LABEL: ldr_int_volatile:%bb.0 ; CHECK-NOT: Cluster ld/st -; CHECK: SU(1): %{{[0-9]+}} = LDRWui -; CHECK: SU(2): %{{[0-9]+}} = LDRWui +; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui +; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui ; EXYNOS: ********** MI Scheduling ********** ; EXYNOS-LABEL: ldr_int_volatile:%bb.0 ; EXYNOS-NOT: Cluster ld/st -; EXYNOS: SU(1): %{{[0-9]+}} = LDRWui -; EXYNOS: SU(2): %{{[0-9]+}} = LDRWui +; EXYNOS: SU(1): %{{[0-9]+}}:gpr32 = LDRWui +; EXYNOS: SU(2): %{{[0-9]+}}:gpr32 = LDRWui define i32 @ldr_int_volatile(i32* %a) nounwind { %p1 = getelementptr inbounds i32, i32* %a, i32 1 %tmp1 = load volatile i32, i32* %p1, align 2 @@ -133,8 +133,8 @@ define i32 @ldr_int_volatile(i32* %a) nounwind { ; CHECK: ********** MI Scheduling ********** ; CHECK-LABEL: ldq_cluster:%bb.0 ; CHECK: Cluster ld/st SU(1) - SU(3) -; CHECK: SU(1): %{{[0-9]+}} = LDRQui -; CHECK: SU(3): %{{[0-9]+}} = LDRQui +; CHECK: SU(1): %{{[0-9]+}}:fpr128 = LDRQui +; CHECK: SU(3): %{{[0-9]+}}:fpr128 = LDRQui ; EXYNOS: ********** MI Scheduling ********** ; EXYNOS-LABEL: ldq_cluster:%bb.0 ; EXYNOS-NOT: Cluster ld/st diff --git a/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll b/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll index b4e07fe76c1..bbb699bbb46 100644 --- a/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll +++ b/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll @@ -6,7 +6,7 @@ ; ; CHECK: ********** MI Scheduling ********** ; CHECK: shiftable -; CHECK: SU(2): %2 = SUBXri %1, 20, 0 +; CHECK: SU(2): %2:gpr64common = SUBXri %1, 20, 0 ; CHECK: Successors: ; CHECK-NEXT: SU(4): Data Latency=1 Reg=%2 ; CHECK-NEXT: SU(3): Data Latency=2 Reg=%2 diff --git a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll index 8c81cf43e68..36de403a0c8 100644 --- a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll +++ b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll @@ -5,7 +5,7 @@ ; ; CHECK: ********** MI Scheduling ********** ; CHECK: misched_bug:%bb.0 entry -; CHECK: SU(2): %2 = LDRWui %0, 1; mem:LD4[%ptr1_plus1] GPR32:%2 GPR64common:%0 +; CHECK: SU(2): %2:gpr32 = LDRWui %0, 1; mem:LD4[%ptr1_plus1] GPR32:%2 GPR64common:%0 ; CHECK: Successors: ; CHECK-NEXT: SU(5): Data Latency=4 Reg=%2 ; CHECK-NEXT: SU(4): Ord Latency=0 @@ -13,7 +13,7 @@ ; CHECK: Successors: ; CHECK: SU(4): Ord Latency=0 ; CHECK: SU(4): STRWui %wzr, %1, 0; mem:ST4[%ptr2] GPR64common:%1 -; CHECK: SU(5): %w0 = COPY %2; GPR32:%2 +; CHECK: SU(5): %w0 = COPY %2; GPR32:%2 ; CHECK: ** ScheduleDAGMI::schedule picking next node define i32 @misched_bug(i32* %ptr1, i32* %ptr2) { entry: diff --git a/test/CodeGen/AArch64/arm64-misched-multimmo.ll b/test/CodeGen/AArch64/arm64-misched-multimmo.ll index 9d92f96a208..bdd4f49d174 100644 --- a/test/CodeGen/AArch64/arm64-misched-multimmo.ll +++ b/test/CodeGen/AArch64/arm64-misched-multimmo.ll @@ -8,7 +8,7 @@ ; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling. ; ; CHECK-LABEL: # Machine code for function foo: -; CHECK: SU(2): %w{{[0-9]+}}, %w{{[0-9]+}} = LDPWi +; CHECK: SU(2): %w{{[0-9]+}}, %w{{[0-9]+}} = LDPWi ; CHECK: Successors: ; CHECK-NOT: ch SU(4) ; CHECK: SU(3) diff --git a/test/CodeGen/AArch64/loh.mir b/test/CodeGen/AArch64/loh.mir index 001e7755829..1e42ecfd599 100644 --- a/test/CodeGen/AArch64/loh.mir +++ b/test/CodeGen/AArch64/loh.mir @@ -22,14 +22,14 @@ tracksRegLiveness: true body: | bb.0: ; CHECK: Adding MCLOH_AdrpAdrp: - ; CHECK-NEXT: %x1 = ADRP - ; CHECK-NEXT: %x1 = ADRP + ; CHECK-NEXT: %x1 = ADRP + ; CHECK-NEXT: %x1 = ADRP ; CHECK-NEXT: Adding MCLOH_AdrpAdrp: - ; CHECK-NEXT: %x1 = ADRP - ; CHECK-NEXT: %x1 = ADRP + ; CHECK-NEXT: %x1 = ADRP + ; CHECK-NEXT: %x1 = ADRP ; CHECK-NEXT: Adding MCLOH_AdrpAdrp: - ; CHECK-NEXT: %x0 = ADRP - ; CHECK-NEXT: %x0 = ADRP + ; CHECK-NEXT: %x0 = ADRP + ; CHECK-NEXT: %x0 = ADRP %x0 = ADRP target-flags(aarch64-page) @g0 %x0 = ADRP target-flags(aarch64-page) @g1 %x1 = ADRP target-flags(aarch64-page) @g2 @@ -38,11 +38,11 @@ body: | bb.1: ; CHECK-NEXT: Adding MCLOH_AdrpAdd: - ; CHECK-NEXT: %x20 = ADRP - ; CHECK-NEXT: %x3 = ADDXri %x20, + ; CHECK-NEXT: %x20 = ADRP + ; CHECK-NEXT: %x3 = ADDXri %x20, ; CHECK-NEXT: Adding MCLOH_AdrpAdd: - ; CHECK-NEXT: %x1 = ADRP - ; CHECK-NEXT: %x1 = ADDXri %x1, + ; CHECK-NEXT: %x1 = ADRP + ; CHECK-NEXT: %x1 = ADDXri %x1, %x1 = ADRP target-flags(aarch64-page) @g0 %x9 = SUBXri undef %x11, 5, 0 ; should not affect MCLOH formation %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g0, 0 @@ -73,11 +73,11 @@ body: | bb.5: ; CHECK-NEXT: Adding MCLOH_AdrpLdr: - ; CHECK-NEXT: %x5 = ADRP - ; CHECK-NEXT: %s6 = LDRSui %x5, + ; CHECK-NEXT: %x5 = ADRP + ; CHECK-NEXT: %s6 = LDRSui %x5, ; CHECK-NEXT: Adding MCLOH_AdrpLdr: - ; CHECK-NEXT: %x4 = ADRP - ; CHECK-NEXT: %x4 = LDRXui %x4, + ; CHECK-NEXT: %x4 = ADRP + ; CHECK-NEXT: %x4 = LDRXui %x4, %x4 = ADRP target-flags(aarch64-page) @g2 %x4 = LDRXui %x4, target-flags(aarch64-pageoff) @g2 %x5 = ADRP target-flags(aarch64-page) @g2 @@ -85,11 +85,11 @@ body: | bb.6: ; CHECK-NEXT: Adding MCLOH_AdrpLdrGot: - ; CHECK-NEXT: %x5 = ADRP - ; CHECK-NEXT: %x6 = LDRXui %x5, + ; CHECK-NEXT: %x5 = ADRP + ; CHECK-NEXT: %x6 = LDRXui %x5, ; CHECK-NEXT: Adding MCLOH_AdrpLdrGot: - ; CHECK-NEXT: %x4 = ADRP - ; CHECK-NEXT: %x4 = LDRXui %x4, + ; CHECK-NEXT: %x4 = ADRP + ; CHECK-NEXT: %x4 = LDRXui %x4, %x4 = ADRP target-flags(aarch64-page, aarch64-got) @g2 %x4 = LDRXui %x4, target-flags(aarch64-pageoff, aarch64-got) @g2 %x5 = ADRP target-flags(aarch64-page, aarch64-got) @g2 @@ -104,23 +104,23 @@ body: | bb.8: ; CHECK-NEXT: Adding MCLOH_AdrpAddLdr: - ; CHECK-NEXT: %x7 = ADRP [TF=1] - ; CHECK-NEXT: %x8 = ADDXri %x7, - ; CHECK-NEXT: %d1 = LDRDui %x8, 8 + ; CHECK-NEXT: %x7 = ADRP [TF=1] + ; CHECK-NEXT: %x8 = ADDXri %x7, + ; CHECK-NEXT: %d1 = LDRDui %x8, 8 %x7 = ADRP target-flags(aarch64-page) @g3 %x8 = ADDXri %x7, target-flags(aarch64-pageoff) @g3, 0 %d1 = LDRDui %x8, 8 bb.9: ; CHECK-NEXT: Adding MCLOH_AdrpAdd: - ; CHECK-NEXT: %x3 = ADRP - ; CHECK-NEXT: %x3 = ADDXri %x3, + ; CHECK-NEXT: %x3 = ADRP + ; CHECK-NEXT: %x3 = ADDXri %x3, ; CHECK-NEXT: Adding MCLOH_AdrpAdd: - ; CHECK-NEXT: %x5 = ADRP - ; CHECK-NEXT: %x2 = ADDXri %x5, + ; CHECK-NEXT: %x5 = ADRP + ; CHECK-NEXT: %x2 = ADDXri %x5, ; CHECK-NEXT: Adding MCLOH_AdrpAddStr: - ; CHECK-NEXT: %x1 = ADRP - ; CHECK-NEXT: %x1 = ADDXri %x1, + ; CHECK-NEXT: %x1 = ADRP + ; CHECK-NEXT: %x1 = ADDXri %x1, ; CHECK-NEXT: STRXui %xzr, %x1, 16 %x1 = ADRP target-flags(aarch64-page) @g3 %x1 = ADDXri %x1, target-flags(aarch64-pageoff) @g3, 0 @@ -138,12 +138,12 @@ body: | bb.10: ; CHECK-NEXT: Adding MCLOH_AdrpLdr: - ; CHECK-NEXT: %x2 = ADRP - ; CHECK-NEXT: %x2 = LDRXui %x2, + ; CHECK-NEXT: %x2 = ADRP + ; CHECK-NEXT: %x2 = LDRXui %x2, ; CHECK-NEXT: Adding MCLOH_AdrpLdrGotLdr: - ; CHECK-NEXT: %x1 = ADRP - ; CHECK-NEXT: %x1 = LDRXui %x1, - ; CHECK-NEXT: %x1 = LDRXui %x1, 24 + ; CHECK-NEXT: %x1 = ADRP + ; CHECK-NEXT: %x1 = LDRXui %x1, + ; CHECK-NEXT: %x1 = LDRXui %x1, 24 %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4 %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4 %x1 = LDRXui %x1, 24 @@ -154,11 +154,11 @@ body: | bb.11: ; CHECK-NEXT: Adding MCLOH_AdrpLdr - ; CHECK-NEXT: %x5 = ADRP - ; CHECK-NEXT: %x5 = LDRXui %x5, + ; CHECK-NEXT: %x5 = ADRP + ; CHECK-NEXT: %x5 = LDRXui %x5, ; CHECK-NEXT: Adding MCLOH_AdrpLdrGotStr: - ; CHECK-NEXT: %x1 = ADRP - ; CHECK-NEXT: %x1 = LDRXui %x1, + ; CHECK-NEXT: %x1 = ADRP + ; CHECK-NEXT: %x1 = LDRXui %x1, ; CHECK-NEXT: STRXui %xzr, %x1, 32 %x1 = ADRP target-flags(aarch64-page, aarch64-got) @g4 %x1 = LDRXui %x1, target-flags(aarch64-pageoff, aarch64-got) @g4 @@ -171,9 +171,9 @@ body: | bb.12: ; CHECK-NOT: MCLOH_AdrpAdrp ; CHECK: Adding MCLOH_AdrpAddLdr - ; %x9 = ADRP - ; %x9 = ADDXri %x9, - ; %x5 = LDRXui %x9, 0 + ; %x9 = ADRP + ; %x9 = ADDXri %x9, + ; %x5 = LDRXui %x9, 0 %x9 = ADRP target-flags(aarch64-page, aarch64-got) @g4 %x9 = ADDXri %x9, target-flags(aarch64-pageoff, aarch64-got) @g4, 0 %x5 = LDRXui %x9, 0 diff --git a/test/CodeGen/AArch64/machine-copy-prop.ll b/test/CodeGen/AArch64/machine-copy-prop.ll index ed0955ccf48..2ac87f00048 100644 --- a/test/CodeGen/AArch64/machine-copy-prop.ll +++ b/test/CodeGen/AArch64/machine-copy-prop.ll @@ -2,18 +2,18 @@ ; This file check a bug in MachineCopyPropagation pass. The last COPY will be ; incorrectly removed if the machine instructions are as follows: -; %q5_q6 = COPY %q2_q3 -; %d5 = -; %d3 = -; %d3 = COPY %d6 +; %q5_q6 = COPY %q2_q3 +; %d5 = +; %d3 = +; %d3 = COPY %d6 ; This is caused by a bug in function SourceNoLongerAvailable(), which fails to -; remove the relationship of D6 and "%q5_q6 = COPY %q2_q3". +; remove the relationship of D6 and "%q5_q6 = COPY %q2_q3". @failed = internal unnamed_addr global i1 false ; CHECK-LABEL: foo: ; CHECK: ld2 -; CHECK-NOT: // kill: D{{[0-9]+}} D{{[0-9]+}} +; CHECK-NOT: // kill: def D{{[0-9]+}} killed D{{[0-9]+}} define void @foo(<2 x i32> %shuffle251, <8 x i8> %vtbl1.i, i8* %t2, <2 x i32> %vrsubhn_v2.i1364) { entry: %val0 = alloca [2 x i64], align 8 diff --git a/test/CodeGen/AArch64/scheduledag-constreg.mir b/test/CodeGen/AArch64/scheduledag-constreg.mir index 1f97fe1360c..013f59f52a9 100644 --- a/test/CodeGen/AArch64/scheduledag-constreg.mir +++ b/test/CodeGen/AArch64/scheduledag-constreg.mir @@ -7,16 +7,16 @@ # Check that the instructions are not dependent on each other, even though # they all read/write to the zero register. # CHECK-LABEL: MI Scheduling -# CHECK: SU(0): %wzr = SUBSWri %w1, 0, 0, %nzcv +# CHECK: SU(0): dead %wzr = SUBSWri %w1, 0, 0, implicit-def dead %nzcv # CHECK: # succs left : 0 # CHECK-NOT: Successors: -# CHECK: SU(1): %w2 = COPY %wzr +# CHECK: SU(1): %w2 = COPY %wzr # CHECK: # succs left : 0 # CHECK-NOT: Successors: -# CHECK: SU(2): %wzr = SUBSWri %w3, 0, 0, %nzcv +# CHECK: SU(2): dead %wzr = SUBSWri %w3, 0, 0, implicit-def dead %nzcv # CHECK: # succs left : 0 # CHECK-NOT: Successors: -# CHECK: SU(3): %w4 = COPY %wzr +# CHECK: SU(3): %w4 = COPY %wzr # CHECK: # succs left : 0 # CHECK-NOT: Successors: name: func diff --git a/test/CodeGen/AArch64/tailcall_misched_graph.ll b/test/CodeGen/AArch64/tailcall_misched_graph.ll index cb42fcced8d..860853a0675 100644 --- a/test/CodeGen/AArch64/tailcall_misched_graph.ll +++ b/test/CodeGen/AArch64/tailcall_misched_graph.ll @@ -26,15 +26,15 @@ declare void @callee2(i8*, i8*, i8*, i8*, i8*, ; CHECK: fi#-2: {{.*}} fixed, at location [SP+8] ; CHECK: fi#-1: {{.*}} fixed, at location [SP] -; CHECK: [[VRA:%.*]] = LDRXui -; CHECK: [[VRB:%.*]] = LDRXui +; CHECK: [[VRA:%.*]]:gpr64 = LDRXui +; CHECK: [[VRB:%.*]]:gpr64 = LDRXui ; CHECK: STRXui %{{.*}}, ; CHECK: STRXui [[VRB]], ; Make sure that there is an dependence edge between fi#-2 and fi#-4. ; Without this edge the scheduler would be free to move the store accross the load. -; CHECK: SU({{.*}}): [[VRB]] = LDRXui +; CHECK: SU({{.*}}): [[VRB]]:gpr64 = LDRXui ; CHECK-NOT: SU ; CHECK: Successors: ; CHECK: SU([[DEPSTOREB:.*]]): Ord Latency=0 -- cgit v1.2.3